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| IDT5V551 1:4 CLOCK BUFFER INDUSTRIAL TEMPERATURE RANGE 1:4 CLOCK BUFFER IDT5V551 FEATURES: * * * * * * * * * * Advanced, low power CMOS process 5V tolerant inputs Low skew outputs (<250ps) Input/Output frequency up to 160MHz Non-inverting output clock Ideal for networking clocks Operating voltage of 3V Output enable mode tri-states outputs Lead-free packaging available Available in SOIC package DESCRIPTION: The 5V551 clock driver is built using advanced CMOS technology. This low skew clock driver offers 1:4 fanout. The fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. The 5V551 offers low capacitance inputs. Typical applications are clock and signal distribution. FUNCTIONAL BLOCK DIAGRAM Q1 PIN CONFIGURATION ICLK 1 2 3 4 8 7 6 5 OE VDD GND Q4 Q2 ICLK Q3 Q1 Q2 Q3 Q4 SOIC TOP VIEW OUTPUT ENABLE The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 c 2006 Integrated Device Technology, Inc. MAY 2006 DSC - 6567/10 IDT5V551 1:4 CLOCK BUFFER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD VTERM TA TSTG TJ TSOLDER Description Supply Voltage All Inputs All Outputs Ambient Operating Temp Storage Temperature Junction Temperature Soldering Temperature Max. -0.5 to +4.6 -0.5 to +7 -0.5 to VDD + 0.5 -40 to +85 -65 to +150 150 260 C C C C Unit V V PIN DESCRIPTION Name ICLK Qn GND VDD OE Type Input Output PWR PWR Input Clock Outputs Connect to Ground Connect to 3.3V Output Enable. Tri-states outputs when LOW. Internal pull-up resistor. Description Clock Input, internal pull-up resistor NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. EXTERNAL COMPONENTS A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than one inch. RECOMMENDED OPERATING RANGE Symbol TA VDD Description Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. -40 3 Typ. -- -- Max. +85 3.6 Unit C V DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified TA = -40C to +85C, VDD = 3.3V 5% Symbol VDD VIH VIL VIH VIL VOH VOL VOH IDD ZO RPU CIN IOS Parameter Operating Voltage Input HIGH Voltage, ICLK(1) Input LOW Voltage, ICLK(1) Input HIGH Voltage, OE Input LOW Voltage, OE Output HIGH Voltage Output LOW Voltage Output HIGH Voltage (CMOS) Operating Supply Current Nominal Output Impedance Internal Pull-Up Resistor Input Capacitance Short Circuit Current ICLK, OE = 0V OE Pin ICLK IOH = -25mA IOL = 25mA IOH = -12mA No Load, 135MHz Test Conditions Min. 3.15 VDD/2 + 0.7 -- 2 -- 2.4 -- VDD - 0.4 -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- 18 20 350 5 3 90 Max. 3.45 -- VDD/2 - 0.7 -- 0.8 -- 0.4 -- -- -- -- -- -- -- mA Unit V V V V V V V V mA k pF NOTE: 1. Nominal switching threshold is VDD/2. 2 IDT5V551 1:4 CLOCK BUFFER INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified TA = -40C to +85C, VDD = 3.3V 5% Symbol FIN FOUT Parameter Input Frequency Output Frequency(1) Output Clock Rise Time Output Clock Fall Time Propagation Delay(2) Output to Output Skew(3) Test Conditions 15pF load 0.8V to 2V 2V to 0.8V 135MHz Rising edges at VDD/2 Min. 0 -- -- -- 2 -- Typ. -- -- -- -- 4 -- Max. 160 160 1.5 1.5 8 250 Unit MHz MHz ns ns ns ps tOR tOF tPD tSK(O) NOTES: 1. With external series resistor of 33 positioned close to each output pin. 2. With rail-to-rail input clock. 3. Between any two outputs with equal loading. 4. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators. TEST CIRCUIT VDD VIN Pulse Generator RT D.U.T. RL VOUT CL TEST CONDITIONS Symbol CL RT RL tR/tF VDD = 3.3V 5% 15 ZOUT of pulse generator 33 1 (0V to 3V or 3V to 0V) Unit pF ns DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to the ZOUT of the pulse generator. tR/tF = Rise/Fall time of the input stimulus from the pulse generator. 3 IDT5V551 1:4 CLOCK BUFFER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXX Device Type X Package X Temp. Range I DC DCG 5V551 Industrial (-40C to +85C) Small Outline IC SOIC - Green 1:4 Clock Buffer CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 4 for Tech Support: clockhelp@idt.com |
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