 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CY241V08A-11 MPEG Clock Generator with VCXO Features * * * * Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs VCXO with analog adjust 3.3V operation Benefits * Highest-performance PLL tailored for multimedia applications * Meets critical timing requirements in complex system designs * Application compatibility for a wide variety of designs Table 1. Frequency Table Part Number CY241V08A-11 Outputs 1 Input Frequency Range Output Frequencies VCXO Control Curve Other Features Pinout-compatible with CY2411 13.5-MHz pullable crystal input One copy of 54 MHz linear per Cypress specification Block Diagram 13.5 XIN XOUT OSC PLL OUTPUT DIVIDER 54 MHz VCXO VDD VSS Pin Configuration CY241V08A-11 8-pin SOIC XIN VDD VCXO VSS 1 2 3 4 8 7 6 5 XOUT VSS 54MHz VDD Cypress Semiconductor Corporation Document #: 38-07654 Rev. *A * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised April 22, 2004 CY241V08A-11 Pin Descriptions Name XIN VDD VCXO VSS 54MHz XOUT Pin Number 1 2,5 3 4,7 6 8 Reference crystal input. Voltage supply. Input analog control for VCXO. Ground. 54MHz clock output. Reference crystal output. Description Document #: 38-07654 Rev. *A Page 2 of 6 CY241V08A-11 Absolute Maximum Conditions Supply Voltage (VDD) ........................................-0.5 to +7.0V DC Input Voltage...................................... -0.5V to VDD + 0.5 Storage Temperature (Non-condensing)..... -55C to +125C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C................................> 10 years Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883................. > 2000V (Above which the useful life may be impaired. For user guidelines, not tested.) Pullable Crystal Specifications[1] Parameter FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed Comments Parallel resonance, fundamental mode, AT cut Min. - - - 3 150 300 - - 180 14.4 Description Operating Voltage Ambient Temperature Max. Load Capacitance Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) Min. 3.135 0 - 0.05 Typ. 3.3 - - - Typ. Max. Unit 13.5 14 - - - - - - - 18 - - 25 - - - 7 250 21.6 Max. 3.465 70 15 500 MHz pF - W ppm pF - fF Unit V C pF ms Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance -150 ppm Recommended Operating Conditions Parameter VDD TA CLOAD tPU DC Electrical Specifications Parameter IOH IOL CIN VVCXO fXO [2] Name Output HIGH Current Output LOW Current Input Capacitance VCXO Input Range VCXO Pullability Range Supply Current 3.3V)[3] Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Low Side High Side Description VOH = VDD - 0.5V, VDD = 3.3V VOL = 0.5V, VDD = 3.3V Except XIN, XOUT pins Min. 12 12 - 0 - 115 - Typ. 24 24 - - - - 30 Min. 45 0.8 0.8 - - Typ. 50 1.4 1.4 - - Max. - - 7 VDD -115 - 35 Max. 55 - - 100 3 Unit mA mA pF V ppm ppm mA Unit % V/ns V/ns ps ms IVDD Parameter[3] DC ER EF t9 t10 AC Electrical Specifications (VDD = Description Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. Peak-to-peak period jitter Notes: 1. Crystals that meet this specification include: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. 2. -115/+115 ppm assumes 2.5pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance. 3. Not 100% tested. Document #: 38-07654 Rev. *A Page 3 of 6 CY241V08A-11 Test and Measurement Set-up VDD 0.1 F DUT Outputs CLOAD GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code CY241V08ASC-11 CY241V08ASC-11T Package Name S8 S8 Package Type 8-pin SOIC Operating Range Commercial Operating Voltage 3.3V 3.3V Features Linear VCXO control curve Linear VCXO control curve 8-pin SOIC - Tape and Reel Commercial Document #: 38-07654 Rev. *A Page 4 of 6 CY241V08A-11 Package Drawing and Dimensions 8 Lead (150 Mil) SOIC S08 8-lead (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07654 Rev. *A Page 5 of 6 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY241V08A-11 Document History Page Document Title: CY241V08A-11 MPEG Clock Generator with VCXO Document Number: 38-07654 REV. ** *A ECN NO. 214071 220461 Issue Date See ECN See ECN Orig. of Change RGL RGL New Data Sheet Minor Change: To post on web Description of Change Document #: 38-07654 Rev. *A Page 6 of 6 |
Price & Availability of CY241V08A-11
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |