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M48Z2M1Y M48Z2M1V
5V or 3.3V, 16 Mbit (2Mb x 8) ZEROPOWER(R) SRAM
FEATURES SUMMARY

INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERIES CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z2M1Y: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V - M48Z2M1V: VCC = 3.0 to 3.6V 2.8V VPFD 3.0V BATTERIES ARE INTERNALLY ISOLATED UNTIL POWER IS APPLIED PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 2Mb x 8 SRAMs
Figure 1. 36-pin, DIP Module
36 1
PLDIP36 (PL) Module
March 2005
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M48Z2M1Y, M48Z2M1V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 36-pin, DIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . Signal Names . . DIP Connections Block Diagram . . ................... ................... ................... ................... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....4 .....5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Address Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . 6 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12.PLDIP36 - 36-pin Plastic DIP Long Module, Package Outline . . . . . . . . . . . . . . . . . . . . 14 Table 11. PLDIP36 - 36-pin Plastic DIP Long Module, Package Mechanical Data . . . . . . . . . . . . 14 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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M48Z2M1Y, M48Z2M1V
SUMMARY DESCRIPTION
The M48Z2M1Y/V ZEROPOWER(R) RAM is a nonvolatile 16,777,216-bit, Static RAM organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries, CMOS SRAMs and a control circuit in a plastic 36-pin DIP, long Module. The ZEROPOWER RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A20 DQ0-DQ7 Address Inputs Data Inputs / Outputs Chip Enable Output Enable WRITE Enable Supply Voltage Ground Not Connected Internally
21 A0-A20 M48Z2M1Y M48Z2M1V
8 DQ0-DQ7
E G W VCC VSS NC
W E G
VSS
AI02048
Figure 3. DIP Connections
NC A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 36 2 35 34 3 33 4 5 32 6 31 30 7 29 8 M48Z2M1Y 9 M48Z2M1V 28 27 10 26 11 25 12 24 13 14 23 15 22 16 21 17 20 18 19
AI02049
VCC A19 NC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
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Figure 4. Block Diagram
VCC
A0-A20
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
2048K x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERIES
VSS
AI02050
OPERATION MODES
The M48Z2M1Y/V has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of Table 2. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) 3.0 to 3.6V or 4.5 to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
data security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the batteries which sustain data until valid power returns.
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10., page 13 for details.
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READ Mode The M48Z2M1Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 16,777,216 locations in the static storage array. Thus, the unique address specified by the 21 Address Inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 5. Address Controlled, READ Mode AC Waveforms
A0-A20 tAVAV tAVQV DQ0-DQ7 DATA VALID
AI02051
tAXQX
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV A0-A20 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI02052
VALID tAXQX tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
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Table 3. READ Mode AC Characteristics
M48Z2M1Y Symbol Parameter
(1)
M48Z2M1V -85 Unit Max ns 85 5 ns ns 35 85 5 ns ns ns 35 45 5 ns ns ns
-70 Min Max Min 85 70 5 30 70 5 25 35 5
tAVAV tAVQV(2) tAXQX(2) tEHQZ(3) tELQV(2) tELQX(3) tGHQZ(3) tGLQV(2) tGLQX(3)
READ Cycle Time Address Valid to Output Valid Address Transition to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition
70
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 100pF or 50pF (see Figure 10., page 11). 3. CL = 5pF (see Figure 10., page 11).
WRITE Mode The M48Z2M1Y/V is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A20 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI02053
tWHAX
tWHQX
Note: Output Enable (G) = High.
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Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A20 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI02054
tELEH
tEHAX
Note: Output Enable (G) = High.
Table 4. WRITE Mode AC Characteristics
M48Z2M1Y Symbol Parameter(1) Min tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tWHAX tWHDX tWHQX(2,3) tWLQZ(2,3) tWLWH WRITE Cycle Time Address Valid to Chip Enable High Address Valid to Chip Enable Low Address Valid to WRITE Enable High Address Valid to WRITE Enable Low Input Valid to Chip Enable High Input Valid to WRITE Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition WRITE Enable High to Input Transition WRITE Enable High to Output Transition WRITE Enable Low to Output Hi-Z WRITE Enable Pulse Width 55 70 65 0 65 0 30 30 15 10 55 5 0 5 25 65 -70 Max Min 85 75 0 75 0 35 35 15 15 75 5 0 5 30 M48Z2M1V -85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF (see Figure 10., page 11). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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Data Retention Mode With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "Don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the batteries are disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on Battery Storage life refer to the Application Note AN1012. VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 9.) is recommended in order to provide the needed filtering.
VSS
In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 9. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
AI02169
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MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 5. Absolute Maximum Ratings
Symbol TA TSTG TBIAS TSLD
(1)
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Temperature Under Bias Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation M48Z2M1Y M48Z2M1V M48Z2M1Y M48Z2M1V
Value 0 to 70 -40 to 85 -40 to 85 260 -0.3 to 7 -0.3 to 4.6 -0.3 to 7 -0.3 to 4.6 20 1
Unit C C C C V V V V mA W
VIO VCC IO PD
Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). No preheat above 150C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery.
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
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M48Z2M1Y, M48Z2M1V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 6. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M48Z2M1Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5
M48Z2M1V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5
Unit V C pF ns V V
Figure 10. AC Testing Load Circuit
5V
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF (Y) 50pF or 5pF (V)
CL includes JIG capacitance
AI07816
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M48Z2M1Y, M48Z2M1V
Table 7. Capacitance
Symbol CIN CIO(3) Input Capacitance Input / Output Capacitance Parameter(1,2) Min Max 40 40 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. Outputs deselected. 3. At 25C.
Table 8. DC Characteristics
Sym ILI(2) ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 Test Condition(1) 0V VIN VCC 0V VOUT VCC E = VIL, Outputs open E = VIH E VCC - 0.2V -0.3 2.2 M48Z2M1Y Min Max 4 4 140 10 8 0.8 VCC + 0.3 0.4 2.2 -0.3 2.2 M48Z2M1V Unit Min Max 4 4 70 2 1 0.6 VCC + 0.3 0.4 A A mA mA mA V V V V
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. Outputs deselected.
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Figure 11. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWP E
RECOGNIZED
tDR tRB
tR
tER DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
Table 9. Power Down/Up AC Characteristics
Symbol tER tF(2) tFB(3) tR tWP E Recovery Time VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time Write Protect Time from VCC = VPFD M48Z2M1Y M48Z2M1V M48Z2M1Y M48Z2M1V Parameter(1) Min 40 300 10 150 10 40 40 150 250 Max 120 Unit ms s s s s s s
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol VPFD Parameter(1,2) M48Z2M1Y Power-fail Deselect Voltage M48Z2M1V M48Z2M1Y VSO tDR(3) Battery Back-up Switchover Voltage M48Z2M1V Expected Data Retention Time 10 2.45 V YEARS 2.8 2.9 3.0 3.0 V V Min 4.2 Typ 4.3 Max 4.5 Unit V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 3. At 25C; VCC = 0V.
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M48Z2M1Y, M48Z2M1V
PACKAGE MECHANICAL INFORMATION
Figure 12. PLDIP36 - 36-pin Plastic DIP Long Module, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Note: Drawing is not to scale.
Table 11. PLDIP36 - 36-pin Plastic DIP Long Module, Package Mechanical Data
mm Symb Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 52.58 18.03 2.30 38.86 14.99 3.05 4.45 36 0.59 0.33 53.34 18.80 2.81 47.50 16.00 3.81 5.33 Max 9.52 Typ Min 0.3650 0.0150 0.0169 0.0079 2.0701 0.7098 0.0906 1.5300 0.5902 0.1201 0.1752 36 0.0232 0.0130 2.1000 0.7402 0.1106 1.8701 0.6299 0.1500 0.2098 Max 0.3748 inches
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M48Z2M1Y, M48Z2M1V
PART NUMBERING
Table 12. Ordering Information Scheme
Example: M48Z 2M1Y -70 PL 1
Device Type M48Z
Supply Voltage and Write Protect Voltage 2M1Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V 2M1V = VCC = 3.0 to 3.6V; VPFD = 2.8 to 3.0V
Speed -70 = 70ns (Y) -85 = 85ns (V)
Package PL = PLDIP36
Temperature Range 1 = 0 to 70C 9(1) = Extended Temperature
Shipping Method blank = Tubes
Note: 1. Contact Sales Offices for availability of Extended Temperature.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
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M48Z2M1Y, M48Z2M1V
REVISION HISTORY
Table 13. Document Revision History
Date July 1999 31-Aug-00 20-Mar-02 29-May-02 28-Mar-03 02-Jul-03 18-Feb-05 Rev. No. 1.0 2.0 3.0 3.1 3.2 3.3 4.0 First Issue From Preliminary Data to Data Sheet Reformatted; Temperature information added to tables (Table 7, 8, 3, 4, 9, 10) Modified "VCC Noise and Negative Going Transients" text Remove 5V/5%, add 3V part (Figure 2, 3, 10; Table 5, 6, 8, 2, 3, 4, 9, 10, 12) Changed characteristic (Table 8) Reformatted; IR reflow update (Table 5) Revision Details
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M48Z2M1Y, M48Z2M1V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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