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CS49DV8C Data Sheet
FEATURES
* 32-bit Post-Processor Audio DSP supports Multichannel Dolby(R) Volume * Programmable through DSP ComposerTM * CS49DV8, supports up to 7.1 Channels of Dolby Volume processing at 48 kHz, 44.1 kHz or 32 kHz.
-- Input Configurable for all input/output digital audio types (I2S, LJ/RJ, and TDM) -- 32-bit data path delivers uncompromised dynamic range -- 192 kHz capable integrated S/PDIF transmitter -- DAO can operate in master or slave mode (SCLK & LRCLK) Integrated Clock Manager/PLL -- Capable of operating from a wide variety of external crystals or external oscillators Input Fs Auto Detection, Reporting and Handling Sample rate conversion. Master & Slave Host Boot Capability via Serial Interface SPI interface capable of running up to 25 MHz during run time 1.8V Core and a 3.3V I/O that is tolerant to 5V input
32-bit Dual Audio DSP Engine featuring Multichannel Dolby(R) Volume
The new CS49DV8C is the fastest time-to-market, massproduction ready Multichannel Dolby Volume solution available. The target applications for the CS49DV8C DSP are: -- -- -- -- -- -- Soundbars DTVs with Integrated Soundbars HDTV Stands/Furniture with Integrated Soundbars Automotive Head Units Automotive Outboard Amplifiers Blu-ray Disc(R) & DVD Receivers / HTiBs
*
* * * * *
All of these applications and many more that use volume control and are subject to playback from sources that do not have consistent volume levels will benefit from the CS49DV8C Dolby Volume solution.
Ordering Information See page 27 for ordering information.
Serial Control 1
Serial Control 2
UART
GPIO
Debug
8 Ch. Audio In 32-bit DSP A
S/PDIF S/PDIF
STC D M A Y P 32-bit DSP B X Y TMR1 TMR2
P
X
8 Ch PCM Audio Out Ext. Memory Controller PLL
Preliminary Product Information
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. SEPT `08 DS868PP2
Copyright 2008 Cirrus Logic (All Rights Reserved) http://www.cirrus.com
CS49DV8C Data Sheet 32-bit Audio DSP Family
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com.
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Dolby is a registered trademarks of Dolby Laboratories, Inc. Dolby Volume is a trademark of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. Motorola and SPI are trademarks of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor. Logic7 is a registered trademark of Harmon International Industries, Inc. iPod is a registered trademark of Apple Computer, Inc. Blu-ray and Blu-ray Disc are trademarks of SONY KABUSHIKI KAISHA CORPORATION .
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CS49DV8C Data Sheet 32-bit Audio DSP Family
Table of Contents
1. Documentation Strategy .................................................................................................................5 2. Overview ..........................................................................................................................................5
2.1 Licensing .........................................................................................................................................................7
3. Firmware Supported .......................................................................................................................7 4. Hardware Functional Description .................................................................................................7
4.1 DSP Core ........................................................................................................................................................7 4.1.1 DSP Memory ......................................................................................................................................7 4.1.2 DMA Controller ...................................................................................................................................7 4.2 On-chip DSP Peripherals ................................................................................................................................8 4.2.1 Digital Audio Input Port (DAI) ..............................................................................................................8 4.2.2 Digital Audio Output Port (DAO) .........................................................................................................8 4.2.3 Serial Control Port 1 & 2 (I2C(R) or SPITM) ............................................................................................8 4.2.4 External Memory Interface .................................................................................................................8 4.2.5 GPIO ...................................................................................................................................................8 4.2.6 PLL-based Clock Generator ...............................................................................................................8 4.3 DSP I/O Description ........................................................................................................................................9 4.3.1 Multiplexed Pins .................................................................................................................................9 4.3.2 Termination Requirements ..................................................................................................................9 4.3.3 Pads ...................................................................................................................................................9 4.4 Application Code Security ...............................................................................................................................9
5. Characteristics and Specifications .............................................................................................10
5.1 Absolute Maximum Ratings ...........................................................................................................................10 5.2 Recommended Operating Conditions ...........................................................................................................10 5.3 Digital DC Characteristics .............................................................................................................................10 5.4 Power Supply Characteristics ....................................................................................................................... 11 5.5 Thermal Data (128-Pin LQFP) ...................................................................................................................... 11 5.6 Switching Characteristics-- RESET ..............................................................................................................12 5.7 Switching Characteristics -- XTI ...................................................................................................................13 5.8 Switching Characteristics -- Internal Clock ...................................................................................................13 5.9 Switching Characteristics -- Serial Control Port - SPI Slave Mode ..............................................................14 5.10 Switching Characteristics -- Serial Control Port - SPI Master Mode ..........................................................15 5.11 Switching Characteristics -- Serial Control Port - I2C Slave Mode .............................................................16 5.12 Switching Characteristics -- Serial Control Port - I2C Master Mode ...........................................................17 5.13 Switching Characteristics -- UART .............................................................................................................18 5.14 Switching Characteristics -- Digital Audio Slave Input Port ........................................................................19 5.15 Switching Characteristics -- Digital Audio Output Port ...............................................................................20 5.16 Switching Characteristics -- SDRAM Interface ...........................................................................................22
6. Ordering Information ....................................................................................................................27 7. Environmental, Manufacturing, and Handling Information ......................................................27 8. Device Pin-Out Diagram ...............................................................................................................28
8.1 128-Pin LQFP Pin-Out Diagram.................................................................................................................... 28
9. Package Mechanical Drawings ....................................................................................................29
9.1 128-Pin LQFP Package .................................................................................................................................29
10. Revision History ..........................................................................................................................30
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CS49DV8C Data Sheet 32-bit Audio DSP Family
List of Figures
Figure 1. RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Serial Control Port - SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9. Digital Audio Port Timing Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) . . . . . . . . . . . . . . . . . . . . . . . . Figure 11. External Memory Interface - SDRAM Burst Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12. External Memory Interface - SDRAM Burst Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13. External Memory Interface - SDRAM Auto Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14. External Memory Interface - SDRAM Load Mode Register Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15. 128-Pin LQFP Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16. 128-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 14 15 16 17 18 19 20 21 23 24 25 26 28 29
List of Tables
Table 1. CS49DV8C Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Device and Firmware Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. CS49DV8C DSP Memory Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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CS49DV8C Data Sheet 32-bit Audio DSP Family
1. Documentation Strategy
The CS49DV8C data sheet describes the CS49DV8C family of multichannel audio DSPs. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS49DV8C family of processors.
Table 1. CS49DV8C Related Documentation
Document Name CS49DV8C Data Sheet Description This document Detailed system design information including Typical Connection Diagrams, boot-procedures, pin descriptions, and other system configuration information. Application note contains an Application Programming Interface (API) used to control the Dolby Volume firmware. Includes detailed configuration and usage information for the GUI development tool.
CS4953xx Hardware User's Manual
AN288PPH, "Dolby(R) Volume Module" DSP ComposerTM User's Manual
The scope of the CS49DV8C Data Sheet is primarily the hardware specifications of the CS49DV8C devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS49DV8C Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer.
2. Overview
The CS49DV8C DSP is designed to provide high-performance volume control using the Dolby Volume algorithm. The CS49DV8, supports up to 7.1 Channels of Dolby Volume processing at 48 kHz, 44.1 kHz or 32 kHz while leaving the 2nd core of the DSP completely available for even further processing functions such as Quadruple Crossover Bass Management, Tone Control, and Multiband Parametric EQ. The CS49DV8C DSP, together with Cirrus Logic's comprehensive library of audio processing algorithms, enables the development of next-generation high-definition audio solutions. Cirrus Logic also provides a broad array of digital interface products, and audio converters, to meet your audio system-level design requirements. The CS49DV8C is available in a 128-pin LQFP package. Please refer to Table 2 on page 6 for the processor speed and available firmware for the CS49DV8C product family.
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Table 2. Device and Firmware Selection Guide
Decode Processor A1 Mid-processor A1 Mid-processor B1 Post-processor1 * Tone Control * Re-EQ * PEQ (up to 11 bands) * Delay * 7.1 Bass Manager * Audio Manager * 1:2 Upsampling
300 MIPS
None
* Stereo PCM * Multi-Channel PCM (2:1 Downsampling Option) (4:1 Downsampling Option)
Dolby (Runs on either DSP A or B) See Section 3. for additional concurrency information.
(R) Volume
Dolby(R) Volume (Runs on either DSP A or B) See Section 3. for additional concurrency information.
1. Processing may be restricted and dependent on firmware selected. Contact your Cirrus Logic FAE for concurrency matrix.
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CS49DV8C Data Sheet 32-bit Audio DSP Family
2.1 Licensing
Licenses are required for Dolby Volume and for all of the third party audio processing algorithms. Please contact your local Cirrus Sales representative for more information.
3. Firmware Supported
The suite of software available for the CS49DV8C family consists of operating systems (OS) and a library of overlays. The overlays have been divided into three main groups called Decoders, Midprocessors, and Post-processors. All software components are defined as follows: * OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, auto-detection, error concealment, etc. * Dolby Volume - The CS49DV8C can run Dolby Volume on either DSP A or DSP B. On the DSP that is not running Dolby Volume, it can run the firmware currently available on the CS4953xx family for that DSP (A or B).
4. Hardware Functional Description
4.1 DSP Core
The CS49DV8C is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two memory access control (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers. Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS49DV8C functionality is controlled by application codes that are stored in on-board ROM or downloaded to the CS49DV8C from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio post-processor modules which are available from Cirrus Logic. 4.1.1 DSP Memory The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
Table 3. CS49DV8C DSP Memory Sizes
Memory Type X Y P DSP A 16k SRAM, 32k ROM 24k SRAM, 32k ROM 8k SRAM, 32k ROM DSP B 10k SRAM, 8k ROM 16k SRAM, 16k ROM 8k SRAM, 24k ROM
4.1.2 DMA Controller The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external
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CS49DV8C Data Sheet 32-bit Audio DSP Family
memory; and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI) The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM or IEC61937. Up to 32-bit word lengths are supported. Additionally support is provided for audio data input to the DSP via the DAI from an HDMI receiver. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 Digital Audio Output Port (DAO) There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192 kHz SPDIF transmitter (data with embedded clock on a single line). 4.2.3 Serial Control Port 1 & 2 (I2C(R) or SPITM) There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 25MHz in SPI mode. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control. 4.2.4 External Memory Interface The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus. 4.2.5 GPIO Many of the CS49DV8C peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. 4.2.6 PLL-based Clock Generator The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS49DV8C defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
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4.3 DSP I/O Description
4.3.1 Multiplexed Pins Many of the CS49DV8C pins are multi-functional. For details on pin functionality please refer to the CS4953xx Hardware User's Manual. 4.3.2 Termination Requirements Open-drain pins on the CS49DV8C must be pulled high for proper operation. Please refer to the CS4953xx Hardware User's Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on the CS49DV8C are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4953xx Hardware User's Manual. 4.3.3 Pads The CS49DV8C I/O operates from the 3.3 V supply and is 5 V tolerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device.
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5. Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All
data sheet typical parameters are measured under the following conditions: T = 25 C, CL = 20 pF, VDD = 1.8 V, VDDA = VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter DC power supplies: Core supply PLL supply I/O supply |VDDA - VDDIO| Symbol VDD VDDA VDDIO Iin Vfilt Vinio Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -65 Max 2.0 3.6 3.6 0.3 +/- 10 3.6 5.0 150 Unit V V V V mA V V C
Input pin current, any pin except supplies Input voltage on PLL_REF_RES Input voltage on I/O pins Storage temperature
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter DC power supplies: Core supply PLL supply I/O supply |VDDA - VDDIO| Symbol VDD VDDA VDDIO TA 0 +25 + 70 C Min 1.71 3.13 3.13 Typ 1.8 3.3 3.3 0 Max 1.89 3.46 3.46 Unit V V V V
Ambient operating temperature Commercial Grade (CVZ/CVZR)
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.) Parameter High-level input voltage Low-level input voltage, except XTI Low-level input voltage, XTI Input Hysteresis High-level output voltage (IO = -4mA), except XTI, SDRAM pins Low-level output voltage (IO = 4mA), except XTI, SDRAM pins SDRAM High-level output voltage (IO = -8mA) SDRAM Low-level output voltage (IO = 8mA) Input leakage current (all digital pins with internal pull-up resistors disabled) Symbol VIH VIL VILXTI Vhys VOH VOL VOH VOL IIN VDDIO * 0.9 VDDIO * 0.9 Min 2.0 Typ 0.4 VDDIO * 0.1 VDDIO * 0.1 5 Max 0.8 0.6 Unit V V V V V V V V A
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Parameter Input leakage current (all digital pins with internal pull-up resistors enabled, and XTI)
Symbol IIN-PU
Min -
Typ -
Max 50
Unit A
5.4 Power Supply Characteristics
(Measurements performed under operating conditions.) Parameter Power supply current: Core and I/O operating: VDD1 PLL operating: VDDA With external memory and most ports operating: VDDIO
1.Dependent on application firmware and DSP clock speed.
Min -
Typ 500 3.5 120
Max -
Unit mA mA mA
5.5 Thermal Data (128-Pin LQFP)
Parameter Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 Symbol Min Typ 48 40 .39 .33 Max C / Watt Unit C / Watt
ja jt
Notes: 1.Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top
and bottom layers. 2.Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top and bottom layers and 0.5-oz copper covering 90% of the internal power plane and ground plane layers. 3.To calculate the die temperature for a given power dissipation j = Ambient Temperature + [ (Power Dissipation in Watts) * ja ] 4.To calculate the case temperature for a given power dissipation c = j - [ (Power Dissipation in Watts) * jt ]
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.6 Switching Characteristics-- RESET
Parameter RESET minimum pulse width low All bidirectional pins high-Z after RESET low Configuration pins setup before RESET high Configuration pins hold after RESET high Symbol Trstl Trst2z Trstsu Trsthld Min 1 50 20 Max 100 Unit s ns ns ns
RESET#
HS[3:0] All Bidirectional Pins Trst2z Trstl
Trstsu Trsthld
Figure 1. RESET Timing
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5.7 Switching Characteristics -- XTI
Parameter External Crystal operating XTI period XTI high time XTI low time External Crystal Load Capacitance (parallel resonant)2 External Crystal Equivalent Series Resistance frequency1 Symbol Fxtal Tclki Tclkih Tclkil CL ESR Min 11.2896 33.3 13.3 13.3 10 Max 27 100 18 50 Unit MHz ns ns ns pF W
1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, and 27 MHz. 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer's recommendation for load capacitor selection.
XTI
t clkih Tclki
Figure 2. XTI Timing
t clkil
5.8 Switching Characteristics -- Internal Clock
Parameter Internal DCLK frequency1 CS49DV8C-CVZ CS49DV8C-CVZR Internal DCLK period1 CS49DV8C-CVZ CS49DV8C-CVZR DCLKP 6.7 1/Fxtal Symbol Fdclk Fxtal 150 ns Min Max Unit MHz
1.After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset.
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.9 Switching Characteristics -- Serial Control Port - SPI Slave Mode
.
Parameter SCP_CLK frequency1 SCP_CS falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time SCP_MOSI input SCP_CLK low to SCP_MISO output valid SCP_CLK falling to SCP_IRQ rising SCP_CS rising to SCP_IRQ falling SCP_CLK low to SCP_CS rising SCP_CS rising to SCP_MISO output high-Z SCP_CLK rising to SCP_BSY falling Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspiirqh tspiirql tspicsh tspicsdz tspicbsyl Min 24 20 20 5 5 0 24 20 3*DCLKP+20 Typical Max 25 11 20 Units MHz ns ns ns ns ns ns ns ns ns ns ns
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer.At boot the maximum speed is Fxtal/3.
tspicss
SCP_CS
tspickl 0 1 2 6 7 0 5 6 7 tspicsh
SCP_CLK
fspisck tspickh A6 tspidsu tspidh tspidov MSB tspiirqh LSB tspiirql tspicsdz A5 A0 R/W MSB LSB
SCP_MOSI
SCP_MISO
SCP_IRQ
tspibsyl
SCP_BSY
Figure 3. Serial Control Port - SPI Slave Mode Timing
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.10 Switching Characteristics -- Serial Control Port - SPI Master Mode
Parameter SCP_CLK frequency1 SCP_CS falling to SCP_CLK rising 3 SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input SCP_CLK low to SCP_MOSI output valid SCP_CLK low to SCP_CS falling SCP_CLK low to SCP_CS rising Bus free time between active SCP_CS SCP_CLK falling to SCP_MOSI output high-Z
Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspicsl tspicsh tspicsx tspidz
Min 18 18 11 5 7 -
Typical
Max
Units
Fxtal/2 (See MHz Footnote 2) 11*DCLKP + (SCP_CLK PERIOD)/2 11 11*DCLKP + (SCP_CLK PERIOD)/2 3*DCLKP 20 ns ns ns ns ns ns ns ns ns ns
-
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. See Section 5.7. 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.
tspicsx tspicss
EE_CS
tspicsl tspickl 0 1 2 6 7 0 5 6 7 tspicsh
SCP_CLK
fspisck tspickh A6 tspidsu tspidh tspidov MSB LSB tspidz A5 A0 R/W MSB LSB
SCP_MISO
SCP_MOSI
Figure 4. Serial Control Port - SPI Master Mode Timing
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.11 Switching Characteristics -- Serial Control Port - I2C Slave Mode
Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid SCP_CLK falling to SCP_IRQ rising NAK condition to SCP_IRQ low SCP_CLK rising to SCB_BSY low
1
Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov tiicirqh tiicirql tiicbsyl
Min 1.25 1.25 1.25 1.25 2.5 3 100 20 -
Typical
Max 400 -
Units kHz s s s
-
s s s ns
18 3*DCLKP + 40 3*DCLKP + 20
ns ns ns ns ns
-
3*DCLKP + 20
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer.
tiicckcmd 0 1
tiicckl 6
tiicr 7 8
tiicf 0 1 6 7 8
tiicckcmd
SCP_CLK
tiicstscl tiicckh A6 A0 tiicdov R/W ACK MSB tiicirqh tiicsu tiich fiicck LSB ACK tiicirql tiicstp tiicbft
SCP_SDA
SCP_IRQ
tiiccbsyl
SCP_BSY
Figure 5. Serial Control Port - I2C Slave Mode Timing
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.12 Switching Characteristics -- Serial Control Port - I2C Master Mode
Parameter SCP_CLK frequency1 SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov Min 1.25 1.25 1.25 1.25 2.5 3 100 20 18 Max 400 Units kHz s s s s s s ns ns ns
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application.
tiicckcmd 0 1
tiicckl 6
tiicr 7 8
tiicf 0 1 6 7 8
tiicckcmd
SCP_CLK
tiicstscl tiicckh A6 A0 tiicdov R/W ACK MSB fiicck LSB ACK tiicstp tiicbft
SCP_SDA
tiicsu
tiich
Figure 6. Serial Control Port - I2C Master Mode Timing
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.13 Switching Characteristics -- UART
Parameter UART_CLK period
1
Symbol tuclki tuckrxsu tuckrxdv tucktxdv
Min 266 40 5 5 -
Max 60 29
Unit ns % ns ns
UART_CLK duty cycle Setup time for UART_RXD Hold time for UART_RXD Delay from CLK transition to TXD transition
1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.
UART_CLK tucktxdv ttxen UART_TXD tuckrxsu UART_RXD UART_TX_EN tuckrxdv ttxhz
Figure 7. UART Timing
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.14 Switching Characteristics -- Digital Audio Slave Input Port
Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn Symbol Tdaiclkp tdaidsu tdaidh Min 40 45 10 5 Max 55 Unit ns % ns ns
DAI_SC LK t daidsu DAI_DATAn t daidh
Figure 8. Digital Audio Input (DAI) Port Timing Diagram
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.15 Switching Characteristics -- Digital Audio Output Port
Parameter DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode1
1,2
Symbol Tdaomclk Tdaosclk tdaomsck tdaomstlr tdaomlrts tdaomdv
Min 40 45 40 40 -
Max 55 60 19 8 8 10
Unit ns % ns % ns ns ns ns
DAO_SCLK duty cycle for Master or Slave mode1 Master Mode (Output A1 Mode) DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input DAO_LRCLK delay from DAO_SCLK transition, respectively3 DAO_SCLK delay from DAO_LRCLK transition, respectively DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3 Slave Mode (Output A0 Mode)4 DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3 DAO_LRCLK delay from DAO_SCLK transition, respectively3 DAO_SCLK delay from DAO_LRCLK transition, respectively3
3
tdaosdv tdaosstlr tdaoslrts
-
15 30 15
ns ns ns
1.Master mode timing specifications are characterized, not production tested. 2.Master mode is defined as the CS49DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid. 4.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
tdaomlclk DAO_MCLK tdaomsck DAO_SCLK tdaomdv DAOn_DATAn tdaomlrts DAO_LRCLK
DAO_LRCLK DAOn_DATAn DAO_SCLK DAO_MCLK
tdaomclk
tdaomsck
tdaomstlr
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK Figure 9. Digital Audio Port Timing Master Mode
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CS49DV8C Data Sheet 32-bit Audio DSP Family
tdaosclk tdaosstlr DAO_LRCLK DAO_LRCLK DAO_SCLK DAO_SCLK tdaosclk DAOn_DATAn tdaosdv tdaoslrts
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
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CS49DV8C Data Sheet 32-bit Audio DSP Family
5.16 Switching Characteristics -- SDRAM Interface
Refer to Figure 11 through Figure 14.
(SD_CLKOUT = SD_CLKIN) Parameter SD_CLKIN high time SD_CLKIN low time SD_CLKOUT rise/fall time SD_CLKOUT Frequency SD_CLKOUT duty cycle SD_CLKOUT rising edge to signal valid Signal hold from SD_CLKOUT rising edge SD_CLKOUT rising edge to SD_DQMn valid SD_DQMn hold from SD_CLKOUT rising edge SD_DATA valid setup to SD_CLKIN rising edge SD_DATA valid hold to SD_CLKIN rising edge SD_CLKOUT rising edge to ADDRn valid tsdcmdv tsdcmdh tsddqv tsddqh tsddsu tsddh tsdav 1.38 1.3 1.38 3.8 45 1.1 3.8 Symbol tsdclkh tsdclkl tsdclkrf Min 2.3 2.3 150 55 3.8 Typical Max 1 Unit ns ns ns MHz % ns ns ns ns ns ns ns
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SD_CLKOUT
tsdcmdv
SD_CS
tsdcmdh
tsdclkrf
SD_RAS
SD_CAS
SD_WE SD_DQMn
tsddqv
00
tsddqh
11
Copyright 2008 Cirrus Logic, Inc. 23
SD_An
tsdav
CAS=2 SD_Dn
tsddsu
tsddh
LSP0 MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 MSP3
SD_CLKIN
tsdclkl
tsdclkh
Figure 11. External Memory Interface - SDRAM Burst Read Cycle
CS49DV8C Data Sheet 32-bit Audio DSP Family
DS868PP2 Copyright 2008 Cirrus Logic, Inc. 24
SD_CLKOUT
tsdcmdv
SD_CS SD_RAS
tsdcmdh
SD_CAS
SD_WE
SD_Dn
LSP0
MSP0
LSP1
MSP1
LSP2
MSP2
LSP3
MSP3
tsdav
SD_An
SD_DQMn
00
11
tsddqv
tsddqh
Figure 12. External Memory Interface - SDRAM Burst Write Cycle
CS49DV8C Data Sheet 32-bit Audio DSP Family
DS868PP2 Copyright 2008 Cirrus Logic, Inc. 25
SD_CLKOUT
tsdcmdv SD_CS
tsdcmdv
tsdcmdh
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_ADDRn
SD_DATAn
Figure 13. External Memory Interface - SDRAM Auto Refresh Cycle
CS49DV8C Data Sheet 32-bit Audio DSP Family
DS868PP2 Copyright 2008 Cirrus Logic, Inc. 26
SD_CLKOUT
tsdcmdv SD_CS
tsdcmdh
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_ADDRn
OPCODE
SD_DATAn
Figure 14. External Memory Interface - SDRAM Load Mode Register Cycle
CS49DV8C Data Sheet 32-bit Audio DSP Family
CS49DV8C Data Sheet 32-bit Audio DSP Family
6. Ordering Information
The CS49DV8C family part number is described as follows:
CS49DVNNI-XYZ where NN - Product Number Variant I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free
Table 4. Ordering Information
Part No. CS49DV8C-CVZ CS49DV8C-CVZR Grade Commercial Commercial Temp. Range 0 to +70 C 0 to +70 C Container Tray 128-pin LQFP Reel Package
7. Environmental, Manufacturing, and Handling Information
Table 5. Environmental, Manufacturing, and Handling Information
Model Number CS49DV8C-CVZ CS49DV8C-CVZR Peak Reflow Temp 260 C 260 C MSL Rating* 3 3 Max Floor Life 7 Days 7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
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CS49DV8C Data Sheet 32-bit Audio DSP Family
8. Device Pin-Out Diagram
8.1 128-Pin LQFP Pin-Out Diagram
GPIO37, SCP1_BSY#, PCP_BSY# GPIO34, SCP1__MISO / SDA
GPIO33, SCP1_MOSI
GPIO35, SCP1_CLK
SD_BA1, EXT_A14
SD_BA0, EXT_A13
110 SD_CS#
RESET#
GPIO38, PCP_WR# / DS#, SCP2_CLK GPIO11, PCP_A3, AS#, SCP2_MISO / SDA GPIO10, PCP_A2 / A10, SCP2_MOSI GPOI9, SCP1_IRQ# GPIO8, PCP_IRQ#, SCP2_IRQ# GPIO7, SCP1_CS#, IOWAIT GPIO6, PCP_CS#, SCP2_CS# VDDIO7 GNDIO7
1
105 GNDIO5
120 VDDIO6
115 GND5
125 VDD6
SD_A10, EXT_A10
EXT_CS1#
SD_RAS#
SD_CAS#
EXT_OE#
EXT_A19
EXT_A18
EXT_A17
EXT_A16
EXT_A15
SD_WE#
GNDIO6
GND6
VDD5
SD_A0, EXT_A0 SD_A1, EXT_A1 100 VDDIO5 SD_A2, EXT_A2
5
GND4 SD_A3, EXT_A3 SD_A4, EXT_A4 95 VDD4 EXT_CS2# SD_A5, EXT_A5 GNDIO4 SD_A6, EXT_A6 90 SD_A7, EXT_A7 VDDIO4 SD_A8, EXT_A8 SD_A9, EXT_A9 GND3 85 SD_A11, EXT_A11
GPIO3, DDAC 10 GPIO2, UART_TXD VDD7 GPIO1, UART_RXD GPIO0, UART_CLK GND7 15 XTAL_OUT XTI XTO GNDA PLL_REF_RES 20 VDDA (3.3V) VDD8 GPIO14, DAI1_DATA3, TM3, DSD3 GPIO13, DAI1_DATA2, TM2, DSD2 GND8 25 GPIO12, DAI1_DATA1, TM1, DSD1 DAI1_DATA0, TM0, DSD0 VDDIO8 DAI1_SCLK, DSD-CLK DAI1_LRCLK, DSD4 30 GNDIO8 GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY# GPIO43, BDI_CLK, DAI2_SCLK BDI_DATA, DAI2_DATA, DSD5 GPIO26, DAO2_DATA3 / XMTB/UART_TX_EN 35 DBDA DBCK GPIO20, DAO2_DATA2, EE_CS# DAO_MCLK 40 GND1 45 GPIO23, DAO2_LRCLK GPIO17, DAO1_DATA3 / XMTA VDDIO1 50 VDD2 55 SD_D5, EXT_D5 60
128-Pin LQFP
SD_A12, EXT_A12 VDD3 SD_CLKEN SD_CLKIN 80 SD_CLKOUT SD_DQM1 SD_D8, EXT_D8 SD_D9, EXT_D9 GNDIO3 75 SD_D10, EXT_D10 SD_D11, EXT_D11 VDDIO3 SD_D12, EXT_D12 SD_D13, EXT_D13 70 SD_D14, EXT_D14 SD_D15, EXT_D15 SD_D0, EXT_D0 GNDIO2 EXT_WE# 65 SD_D1, EXT_D1
TEST
GPIO22, DAO2_SCLK
GPIO16, DAO1_DATA2, HS2
GPIO15, DAO1_DATA1, HS1
GPIO19, DAO2_DATA1, HS4
GPIO18, DAO2_DATA0, HS3
DAO1_DATA0, HS0
DAO1_LRCLK
DAO1_SCLK
GNDIO1
GND2
SD_DQM0
SD_D7, EXT_D7
SD_D6, EXT_D6
SD_D4, EXT_D4
VDDIO2
VDD1
SD_D3, EXT_D3
Figure 15. 128-Pin LQFP Pin-Out
28 Copyright 2008 Cirrus Logic, Inc. DS868PP2
SD_D2, EXT_D2
CS49DV8C Data Sheet 32-bit Audio DSP Family
9. Package Mechanical Drawings
9.1 128-Pin LQFP Package
D D1
E E1
1 e A1 L
b A
Figure 16. 128-Pin LQFP Package Drawing
Table 6. 128-Pin LQFP Package Characteristics
MILLIMETERS DIM MIN A A1 b D D1 E E1 e q L L1 ddd --0.05 0.17 NOM ----0.22 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 3.5 0.60 1.00 REF 0.08 MAX 1.60 0.15 0.27 MIN --.002" .007" NOM ----.009" .866" .787" .630" .551" .020" 3.5 .024" .039" REF .003" MAX .063" .006" .011" INCHES
0 0.45
7 0.75
0 .018"
7 .030"
TOLERANCES OF FORM AND POSITION
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CS49DV8C Data Sheet 32-bit Audio DSP Family
10. Revision History
Revision PP1 PP2 Date September 2, 2008 September 25, 2008 Initial Release. Removed references to External Parallel Flash / SRAM Interface. Changes
30
Copyright 2008 Cirrus Logic, Inc.
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