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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45D32DA721
32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
Description
The MC-45D32DA721 is a 33,554,432 words by 72 bits DDR synchronous dynamic RAM module on which 18 pieces of 128M DDR SDRAM: PD45D128442 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 33,554,432 words by 72 bits organization (ECC type) * Clock frequency
Part number /CAS latency Clock frequency (MAX.) MC-45D32DA721KF-C75 CL = 2.5 CL = 2 MC-45D32DA721KF-C80 CL = 2.5 CL = 2 MC-45D32DA721KFA-C75 CL = 2.5 CL = 2 MC-45D32DA721KFA-C80 CL = 2.5 CL = 2 133 MHz 100 MHz 125 MHz 100 MHz 133 MHz 100 MHz 125 MHz 100 MHz DDR Registered DIMM Design specification Rev. 0.9 compliant DDR Registered DIMM Design specification Rev. 0.6 compliant Module type
* Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge * Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK * Quad internal banks operation * Possible to assert random column address in every clock cycle * Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0037N10 (1st edition) (Previous No. M14825EJ2V0DS00) Date Published January 2001 CP (K) Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
* 2.5 V 0.2 V Power supply for VDD * 2.5 V 0.2 V Power supply for VDDQ * SSTL_2 compatible with all signals * 4,096 refresh cycles / 64 ms * Burst termination by Precharge command and Burst stop command * 184-pin dual in-line memory module (Pin pitch = 1.27 mm) * Registered type * Serial PD
Ordering Information
Part number Clock frequency (MAX.) 133 MHz 125 MHz 133 MHz 125 MHz Package Mounted devices
MC-45D32DA721KF-C75 MC-45D32DA721KF-C80 MC-45D32DA721KFA-C75 MC-45D32DA721KFA-C80
184-pin Dual In-line Memory Module 18 pieces of PD45D128442G5 (Rev. K) (Socket Type) Edge connector: Gold plated 43.18 mm height (10.16 mm (400) TSOP (II))
2
Preliminary Data Sheet E0037N10
Pin Configuration
184-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal.
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 NC VDDQ NC DQ20 NC VSS DQ21 A11 DM2/DQS11 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8/DQS17 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDDQ /S0 NC DM5/DQS14 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ NC NC VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS NC NC VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
A0 - A11 BA0, BA1 CK0 /CK0 CKE0 WP /S0 /RAS /CAS /WE DQS0 - DQS8
: Address Inputs : SDRAM Bank Select : Clock Input : Clock Input : Clock Enable Input : Write Protect : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : Low Data Strobe High Data Strobe
[Row: A0 - A11, Column: A0 - A9, A11] DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs (positive line of differential pair) (negative line of differential pair)
DM(0 - 8) / DQS(9 - 17) : Low Data Masks / SA0 - SA2 SDA SCL VDD VSS VDDID VDDQ VREF VDDSPD NC /RESET : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : VDD Identification Flag : Power Supply for DQ and DQS : Input Reference : Power supply for EEPROM : No Connection : Reset Input
Preliminary Data Sheet E0037N10
3
Block Diagram
/RS0 DQS0 VSS DM0/DQS9
DQ 0 DQ 1 DQ 2 DQ 3
DQS1
DQ 0 DM /S DQ 1 D0 DQ 2 DQ 3
DQS
DQ 4 DQ 5 DQ 6 DQ 7
DM1/DQS10
DQ 0 DM /S DQ 1 D9 DQ 2 DQ 3
DQS
DQ 8 DQ 9 DQ 10 DQ 11
DQS2
DQ 0 DM /S DQ 1 D1 DQ 2 DQ 3
DQS
DQ 12 DQ 13 DQ 14 DQ 15
DM2/DQS11
DQ 0 DM /S DQ 1 D10 DQ 2 DQ 3
DQS
DQ 16 DQ 17 DQ 18 DQ 19
DQS3
DQ 0 DM /S DQ 1 D2 DQ 2 DQ 3
DQS
DQ 20 DQ 21 DQ 22 DQ 23
DM3/DQS12
DQ 0 DM /S DQ 1 D11 DQ 2 DQ 3
DQS
DQ 24 DQ 25 DQ 26 DQ 27
DQS4
DQ 0 DM /S DQ 1 D3 DQ 2 DQ 3
DQS
DQ 28 DQ 29 DQ 30 DQ 31
DM4/DQS13
DQ 0 DM /S DQ 1 D12 DQ 2 DQ 3
DQS
VDDQ VDD VREF
D0 - D17 D0 - D17 D0 - D17 D0 - D17
DQ 32 DQ 33 DQ 34 DQ 35
DQS5
DQ 0 DM /S DQ 1 D4 DQ 2 DQ 3
DQS
DQ 36 DQ 37 DQ38 DQ39
DM5/DQS14
DQ 0 DM /S DQ 1 D13 DQ 2 DQ 3
DQS
VSS VDDID
SERIAL PD SCL SDA A0 A1 A2 WP
DQ 40 DQ 41 DQ 42 DQ 43
DQS6
DQ 0 DM /S DQ 1 D5 DQ 2 DQ 3
DQS
DQ 44 DQ 45 DQ 46 DQ 47
DM6/DQS15
DQ 0 DM /S DQ 1 D14 DQ 2 DQ 3
DQS
SA0 SA1 SA2
DQ 48 DQ 49 DQ 50 DQ 51
DQS7
DQ 0 DM /S DQ 1 D6 DQ 2 DQ 3
DQS
DQ 52 DQ 53 DQ 54 DQ 55
DM7/DQS16
DQ 0 DM /S DQ 1 D15 DQ 2 DQ 3
DQS
/S0 BA0, BA1 A0 - A11 /RAS Register /CAS CKE0 /WE PCK /PCK
DQS
/RS0 RBA0, RBA1 RA0 - RA11 /RRAS /RCAS RCKE0 /RWE /RESET
/S0 : D0 - D17 BA0, BA1 : D0 - D17 A0 - A11 : D0 - D17 /RAS : D0 - D17 /CAS : D0 - D17 CKE : D0 - D17 /WE : D0 - D17
DQ 56 DQ 57 DQ 58 DQ 59
DQS8
DQ 0 DM /S DQ 1 D7 DQ 2 DQ 3
DQS
DQ 60 DQ 61 DQ 62 DQ 63
DM8/DQS17
DQ 0 DM /S DQ 1 D16 DQ 2 DQ 3
DQS
CB 0 CB 1 CB 2 CB 3
DQ 0 DM /S DQ 1 D8 DQ 2 DQ 3
DQS
CB 4 CB 5 CB 6 CB 7
DQ 0 DM /S DQ 1 D17 DQ 2 DQ 3
CK0, /CK0
PLL
Note
Note Wire per Clock Loading Table/Wiring Diagrams. Remarks 1. The value of all resistors of DQs, DQSs, DM/DQSs is 22 . 2. D0 - D17: PD45D128442 (8M words x 4 bits x 4 banks)
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Preliminary Data Sheet E0037N10
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 1 ms and then, execute Power on sequence and CBR (auto) refresh before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to VSS Voltage on input pin relative to VSS Short circuit output current Power dissipation Storage temperature Symbol VDD, VDDQ VT IO PD Tstg Condition Rating -0.5 to +3.6 -0.5 to +3.6 50 21 -55 to +125 Unit V V mA W C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage Supply voltage for DQ, DQS Input reference voltage Termination voltage High level dc input voltage Low level dc input voltage Input differential voltage (CLK and /CLK) Input crossing point voltage (CLK and /CLK) Operating ambient temperature Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VID (DC) VIX TA Condition MIN. 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 0.36 0.5 x VDDQ-0.2 0 VREF TYP. 2.5 2.5 MAX. 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 VDDQ + 0.6 0.5 x VDDQ+0.2 70 Unit V V V V V V V V C
Capacitance (TA = 25 C, f = 100 MHz)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 Data input/output capacitance CI/O1 Test condition A0 - A11, BA0, BA1, /RAS, /CAS, /WE CK0, /CK0 CKE0 /S0 DM(0-8)/DQS(9-17), DQS0 - DQS8 CI/O2 DQ0 - DQ63, CB0 - CB7 TBD TBD MIN. TBD TBD TBD TBD TBD TYP. MAX. TBD TBD TBD TBD TBD pF Unit pF
Preliminary Data Sheet E0037N10
5
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current (ACT-PRE) Symbol IDD0 Test condition /CAS Grade latency -C75 MIN. MAX. TBD Unit mA Notes
tRC = tRC(MIN.), tCK = tCK (MIN.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and control inputs changing once per clock cycle tRC = tRC(MIN.), tCK = tCK (MIN.), One CL = 2 bank, Active-read-precharge, IO = 0 mA, Burst length = 2, CL = 2.5 Address and control inputs changing once per clock cycle CKE VIL(MAX.), tCK = tCK(MIN.), All banks idle, Power down mode
-C80
TBD
Operating current (ACT-READ-PRE)
IDD1
-C75 -C80 -C75 -C80
TBD TBD TBD TBD TBD TBD
mA
1
Precharge power down standby current Idle standby current
IDD2P IDD2N
mA mA
CKE VIH(MIN.), tCK = tCK(MIN.), /CS VIH(MIN.), All banks idle, Address and other control inputs changing once per clock cycle CKE VIL(MAX.), tCK = tCK(MIN.), One bank active, Power down mode /CS VIH(MIN.), CKE VIH(MIN.), tCK = tCK(MIN.), tRC = tRAS(MAX.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and other control inputs changing once per clock cycle tCK = tCK(MIN.), Continuous burst read, Burst length = 2, IO = 0mA, One bank active, Address and control inputs changing once per clock cycle tCK = tCK(MIN.), Continuous burst write, Burst length = 2, One bank active, Address and control inputs changing once per clock cycle tRFC = tRFC(MIN.) CKE 0.2 V CL = 2 -C75 -C80 CL = 2.5 -C75 -C80 CL = 2 -C75 -C80 CL = 2.5 -C75 -C80 -C75 -C80
Active power down standby current Active standby current
IDD3P IDD3N
TBD TBD
mA mA
Operating current (Burst read)
IDD4R
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
mA
2
Operating current (Burst write)
IDD4W
mA
2
CBR (auto) refresh current
IDD5
mA
Self refresh current
IDD6
mA
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. 2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output open. DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Input leakage current Output leakage current Output high current Output low current Symbol II(L) IO(L) IOH IOL Test condition VI = 0 to 3.6 V, all other pins not under test = 0 V DOUT is disabled, VO = 0 to VDDQ + 0.3 V VOUT = VDDQ - 0.43 V VOUT = 0.35 V MIN. TBD TBD TBD TBD MAX. TBD TBD Unit Notes
A A
mA mA
6
Preliminary Data Sheet E0037N10
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter Input Reference voltage (Input timing measurement reference level) Termination voltage (Output timing measurement reference level) High level ac input voltage Low level ac input voltage Input differential voltage (CK0 and /CK0) Input signal slew rate Symbol VREF VTT VIH(ac) VIL(ac) VID(ac) SLEW Value VDDQ x 0.5 VREF VREF + 0.31 VREF - 0.31 0.7 1 Unit V V V V V V/ns 2 1 Notes
Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level. 2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)VIL(ac))/ t
VTT RT = 50 Output CLOAD = 30 pF
Preliminary Data Sheet E0037N10
7
Synchronous Characteristics
Parameter Symbol -C75 (PC266B) MIN. Clock cycle time CL = 2.5 CL = 2 CLK high-level width CLK low-level width DQ output access time from CLK, /CLK DQS output access time from CLK, /CLK DQS-DQ skew (for DQS and associated DQ signals) DQS-DQ skew (for DQS and all DQ signals) Data out low-impedance time from CLK, /CLK Data out high-impedance time from CLK, /CLK Half clock period DQS read preamble DQS read postamble DQ-DQS hold, DQS to first DQ to go non-valid, per access DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width (for each input) DQS write preamble setup time DQS write preamble Write postamble Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CLK setup time DQS falling edge hold time from CLK Address and control input setup time Address and control input hold time Address and control input pulse width Internal write to read command delay tCH tCL tAC tDQSCK tDQSQ tDQSQA tLZ tHZ tHP tRPRE tRPST tQH tDS tDH tDIPW tWPRES tWPRE tWPST tDQSS tDQSH tDQSL tDSS tDSH tIS tIH tIPW tWTR tCK 7.5 10 0.45 0.45 -0.75 -0.75 -0.5 -0.5 -0.75 -0.75 tCH, tCL 0.9 0.4 tHP - 0.75 0.5 0.5 1.75 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 0.9 0.9 2.2 1 0.6 1.25 1.1 0.6 MAX. 15 15 0.55 0.55 0.75 0.75 0.5 0.5 0.75 0.75 -C80 (PC200) MIN. 8 10 0.45 0.45 -0.8 -0.8 -0.6 -0.6 -0.8 -0.8 tCH, tCL 0.9 0.4 tHP - 1 0.6 0.6 2 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 1.1 1.1 2.5 1 0.6 1.25 1.1 0.6 MAX. 15 15 0.55 0.55 0.8 0.8 0.6 0.6 0.8 0.8 tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK ns Unit Note
Remark These specifications are applied to the monolithic device.
8
Preliminary Data Sheet E0037N10
Asynchronous Characteristics
Parameter Symbol -C75(PC266B) MIN. ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period PRE to ACT command period ACT to READ/WRITE delay ACT(one) to ACT(another) command period Write recovery time Auto precharge write recovery time + precharge time Mode register set command cycle time Exit self refresh to command Refresh time (4,096 refresh cycles) tRC tRFC tRAS tRP tRCD tRRD tWR tDAL tMRD tXSNR tREF 65 75 45 20 20 15 15 35 15 75 64 120,000 MAX. -C80(PC200) MIN. 70 80 50 20 20 15 15 35 15 80 64 120,000 MAX. ns ns ns ns ns ns ns ns ns ns ms Unit
Preliminary Data Sheet E0037N10
9
Serial PD
Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface CL = 2.5 Cycle time -C75 -C80 10 CL = 2.5 Access time -C75 -C80 11 12 13 14 15 16 17 18 19 20 21 22 23 DIMM configuration type Refresh rate/type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 Cycle time -C75 -C80 24 CL = 2 Access time -C75 -C80 25-26 27 tRP(MIN.) -C75 -C80 28 tRRD(MIN.) -C75 -C80 29 tRCD(MIN.) -C75 -C80 30 tRAS(MIN.) -C75 -C80 31 Module bank density 50H 50H 3CH 3CH 50H 50H 2DH 32H 40H 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 20 ns 20 ns 15 ns 15 ns 20 ns 20 ns 45 ns 50 ns Hex 80H 08H 07H 0CH 0BH 01H 48H 00H 04H 75H 80H 75H 80H 02H 80H 04H 04H 01H 0EH 04H 0CH 01H 02H 26H 00H A0H A0H 75H 80H Bit 7 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit 6 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 5 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 Bit 4 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Bit 2 0 0 1 1 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 0 Bit 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 Bit 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0
(1/2)
Notes 128 bytes 256 bytes DDR SDRAM 12 rows 11 columns 1 bank 72 bits 0 SSTL_2 7.5 ns 8 ns 0.75 ns 0.8 ns ECC Normal x4 x4 1 clock 2, 4, 8 4 banks 2, 2.5 0 1 Reg.+PLLdifclk VDD 0.2 V 10 ns 10 ns 0.75 ns 0.8 ns
256M bytes
10
Preliminary Data Sheet E0037N10
(2/2)
Byte No. 32 Function Described Command and address signal input setup time 33 Command and address signal input hold time 34 Data signal input setup time -C75 -C80 -C75 -C80 -C75 -C80 35 Data signal input hold time -C75 -C80 36-61 62 63 SPD revision Checksum for bytes 0 - 62 -C75 -C80 64-71 72 73-90 91 93-94 95-99 Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision Code Manufacturing date Assembly serial number 00H 0 0 0 0 0 0 0 0 00H CDH 53H 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 Hex 90H B0H 90H B0H 50H 60H 50H 60H Bit 7 1 1 1 1 0 0 0 0 Bit 6 0 0 0 0 1 1 1 1 Bit 5 0 1 0 1 0 1 0 1 Bit 4 1 1 1 1 1 0 1 0 Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0 Notes 0.9 ns 1.1 ns 0.9 ns 1.1 ns 0.5 ns 0.6 ns 0.5 ns 0.6 ns
100-127 Mfg specific
Timing Chart
Refer to the PD45D128442, 45D128842, 45D128164 Data sheet (E0030N).
Preliminary Data Sheet E0037N10
11
Package Drawings
[MC-45D32DA721KF]
184-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A M1 (AREA B) Y Z N
Q R L
M
M2 (AREA A) I
H K C
A E D A1 (AREA A)
S
(OPTIONAL HOLES)
T U
ITEM A A1 C D D1
MILLIMETERS 133.35 133.350.13 64.770.15 6.35 1.80 3.8 49.530.15 1.27 (T.P.) 6.35 73.30 17.78 43.180.15 23.38 19.80 4.0 MAX. R2.0 4.000.10
detail of A part W D2
D2 E H I K L M
D1 V
X
M1 M2 N Q R S T U V W X Y Z
2.50
1.270.1 4.00 MIN. 0.200.15 1.00.05 2.500.15 3.0 MIN. 3.0 MIN. M184S-50A
12
Preliminary Data Sheet E0037N10
[MC-45D32DA721KFA]
184-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) J1 (AREA B) U K
M M I E B G C A1 (AREA A) A N
(OPTIONAL HOLES)
J
H J2 (AREA A)
P Q
D
ITEM A A1 B C C1 C2 D E G H I J J1 J2
MILLIMETERS 133.35 133.350.13 64.77 6.35 1.80 3.80 49.53 1.27 (T.P.) 6.35 9.98 17.78 43.180.13 23.38 19.80 4.0 MAX. 0.90 4.0
detail of A part S C2
L C1
R T
K L M N P Q R S T U
2.50
1.270.1 4.0 MIN. 0.20.15 1.00.05 2.500.10 3.0 MIN.
Preliminary Data Sheet E0037N10
13
[MEMO]
14
Preliminary Data Sheet E0037N10
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Data Sheet E0037N10
15
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
* The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. * Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above).
M8E 00. 4

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