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19-4428; Rev 1; 4/09
KIT ATION EVALU ABLE AVAIL
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
General Description Features
o 16-/12-Bit Resolution in a 3mm x 3mm, 16-Pin TQFN Package o Hardware-Selectable on Power-Up or Reset-toZero/Midscale DAC Output o Double-Buffered Input Registers o LDAC Asynchronously Updates DAC Output o READY Facilitates Daisy Chaining o High-Performance 10ppm/C Internal Reference o Guaranteed Monotonic Over All Operating Conditions o Wide +2.7V to +5.25V Supply Range o Rail-to-Rail Buffered Output Operation o Low Gain Error (Less Than 0.5% FS) and Offset (Less Than 10mV) o 30MHz 3-Wire SPI-/QSPI-/MICROWIRE-/ DSP-Compatible Serial Interface o CMOS-Compatible Inputs with Hysteresis o Low Power Consumption (ISHDN = 2A max)
MAX5138/MAX5139
The MAX5138/MAX5139 are a family of single-channel pin-compatible and software-compatible 16-bit and 12bit DACs. The MAX5138/MAX5139 are low-power, 16bit/12-bit, buffered voltage-output, high-linearity DACs. They use a precision internal reference or a precision external reference for rail-to-rail operation. The MAX5138/MAX5139 accept a wide +2.7V to +5.25V supply-voltage range to accommodate most low-power and low-voltage applications. These devices accept a 3-wire SPITM-/QSPITM-/MICROWIRETM-/DSP-compatible serial interface to save board space and reduce the complexity of optically isolated and transformer-isolated applications. The digital interface's double-buffered hardware and software LDAC provide simultaneous output update. The serial interface features a READY output for easy daisy-chaining of several MAX5138/MAX5139 devices and/or other compatible devices. The MAX5138/MAX5139 include a hardware input to reset the DAC outputs to zero or midscale upon power-up or reset, providing additional safety for applications that drive valves or other transducers that need to be off during power-up. The high linearity of the DACs makes these devices ideal for precision control and instrumentation applications. The MAX5138/MAX5139 are available in an ultra-small (3mm x 3mm), 16-pin TQFN package and are specified over the -40C to +105C extended industrial temperature range.
Ordering Information
PART PIN-PACKAGE RESOLUTION (BITS)
Applications
Automatic Test Equipment Automatic Tuning Communication Systems
MAX5138BGTE+ 16 TQFN-EP* 16 MAX5139GTE+ 16 TQFN-EP* 12 +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Note: All devices are specified over the -40C to +105C operating temperature range.
Pin Configuration
DVDD OUT N.C. 9 8 7 AGND DIN CS SCLK 6 *EP 1 N.C. 2 M/Z 3 LDAC 4 N.C. 5
Gain and Offset Adjustment Portable Instrumentation Power-Amplifier Control Process Control and Servo Loops Programmable Voltage and Current Sources
TOP VIEW
12 AVDD 13 REFI 14 REFO 15 AGND 16
11
10
MAX5138 MAX5139 +
Functional Diagram and Typical Operating Circuit appear at end of data sheet. SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
*EXPOSED PAD
TQFN 3mm x 3mm 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
READY
Data Acquisition
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs MAX5138/MAX5139
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND ........................................................-0.3V to +6V OUT to AGND...............................................-0.3V to the lower of (AVDD + 0.3V) and +6V REFI, REFO, M/Z to AGND ...........................-0.3V to the lower of (AVDD + 0.3V) and +6V SCLK, DIN, CS to AGND ..............................-0.3V to the lower of (DVDD + 0.3V) and +6V LDAC, READY to AGND...............................-0.3V to the lower of (DVDD + 0.3V) and +6V Continuous Power Dissipation (TA = +70C) 16-Pin TQFN (derate at 14.7mW/C above +70C) ..1176.5mW Maximum Current into Any Input or Output with the Exception of M/Z Pin .......................................50mA Maximum Current into M/Z Pin ...........................................5mA Operating Temperature Range .........................-40C to +105C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VAGND = 0, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC ACCURACY (Notes 1, 2) Resolution MAX5138 Integral Nonlinearity MAX5139 Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Drift Gain Error Gain Temperature Coefficient REFERENCE INPUT AVDD = 3V to 5.25V Reference-Input Voltage Range Reference Input Impedance INTERNAL REFERENCE Reference Voltage Reference Temperature Coefficient Reference Output Impedance Line Regulation Maximum Capacitive Load CR VREFO TA = +25C (Note 5) 2.437 2.440 10 1 100 0.1 2.443 25 V ppm/C ppm/V nF VREFI AVDD = 2.7V to 3V 2 2 113 AVDD AVDD 0.2 V k GE (Note 4) -0.5 N INL INL DNL OE MAX5138 MAX5139 VREFI = 5V, AVDD = 5.25V (Note 3) TA = +25C -1 -1.0 -10 1 4 0.2 2 +0.5 0.25 16 12 -9 2 +11 6 +1 +1.0 +10 Bits LSB LSB LSB mV V/C % of FS ppm FS/C SYMBOL CONDITIONS MIN TYP MAX UNITS
VREFI = 5V, AVDD = 5.25V Guaranteed monotonic (Note 4)
2
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Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VAGND = 0, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DAC OUTPUT VOLTAGE (Note 2) Output Voltage Range DC Output Impedance Maximum Capacitive Load (Note 5) Resistive Load Short-Circuit Current Power-Up Time CL RL ISC AVDD = 5.25V AVDD = 2.7V From power-down mode 0.7 x DVDD 0.3 x DVDD VIN = 0 or DVDD -1 0.1 +1 10 DVDD - 0.5 0.4 1.25 5 0.5 25 10kHz 1Hz to 10kHz 120 18 -40 Series resistance = 0 Series resistance = 500 2 35 20 25 +40 No load 0.02 0.1 0.2 15 AVDD - 0.02 V nF F k mA s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5138/MAX5139
DIGITAL INPUTS (SCLK, DIN, CS, LDAC) (Note 6) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance DIGITAL OUTPUTS (READY) Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Major Code Transition Analog Glitch Impulse Output Noise Integrated Output Noise SR tS Positive and negative 1/4 scale to 3/4 scale VREFI = AVDD = 5V settle to 2 LSB (Note 5) Code 0, all digital inputs from 0 to DVDD V/s s nV*s nV*s nV/Hz V VOH VOL ISOURCE = 3mA ISINK = 2mA V V VIH VIL IIN CIN V V A pF
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3
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs MAX5138/MAX5139
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VAGND = 0, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10k, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER POWER REQUIREMENTS (Note 7) Analog Supply Voltage Range Digital Supply Voltage Range Supply Current Power-Down Supply Current AVDD DVDD IAVDD IDVDD IAVPD IDVPD fSCLK tCH tCL tCSS tCSH tDS tDH tSRL tCSW tLDACPWL (Note 9) 33 33 No load, all digital inputs at 0 or DVDD No load, all digital inputs at 0 or DVDD 2.7 2.7 1 1 0.2 0.1 0 13 13 8 5 10 2 30 5.25 AVDD 1.6 10 2 2 30 V V mA A A SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Note 8) (Figure 1) Serial-Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall-to-SCLK Fall Setup Time SCLK Fall-to CS-Rise Hold Time DIN-to-SCLK Fall Setup Time DIN-to-SCLK Fall Hold Time SCLK Fall to READY Transition CS Pulse-Width High LDAC Pulse Width MHz ns ns ns ns ns ns ns ns ns
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Static accuracy tested without load. Linearity is tested within 20mV of AGND and AVDD, allowing for gain and offset error. Codes above 2047 are guaranteed to be within 9 LSB. Gain and offset tested within 100mV of AGND and AVDD. Guaranteed by design. Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VI < DVDD - 0.6V or VI > 0.5V. At VI = 2.2V with DVDD = 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input-level compatible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing. Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without AVDD. Note 8: All timing specifications are with respect to the digital input and output thresholds. Note 9: Maximum daisy-chain clock frequency is limited to 25MHz.
COMMAND EXECUTED ON 24th FALLING EDGE OF SCLK tCSW
CS
tCSS
SCLK
tCL
tCH
tCSH
tDS DIN X C7 C6 C5 D3 D2
tDH D1 D0 tSRL X
READY X = DON'T CARE.
Figure 1. Serial-Interface Timing Diagram
4 _______________________________________________________________________________________
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX5138 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5138 toc01
MAX5138/MAX5139
INTEGRAL NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
MAX5138 toc02
INTEGRAL NONLINEARITY vs. TEMPERATURE
7 5 3 INL (LSB) 1 -1 -3 -5 -7 -9
MAX5138 toc03
9 6 3 INL (LSB)
9 7 5 3 INL (LSB) 1 -1 -3 -5
9
0 -3 -6 -9 0 16,384 32,768 49,152 65,536 DIGITAL INPUT CODE (LSB)
-7 -9 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)
-40
-20
0
20
40
60
80
100
TEMPERATURE (C)
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5138 toc04
DIFFERENTIAL NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
MAX5138 toc05
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX5138 toc06
1.0 0.8 0.6 0.4 DNL (LSB)
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
1.0
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16,384 32,768 49,52 65,536 DIGITAL INPUT CODE (LSB)
2.7
3.2
3.7
4.2
4.7
5.2
-40
-20
0
20
40
60
80
100
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE
MAX5138 toc07
12-BIT DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.08 0.06 0.04 DNL (LSB) INL (LSB) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10
MAX5138 toc08
12-BIT INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00
MAX5138 toc09
10 8 6 OFFSET ERROR (mV) 4 2 0 -2 -4 -6 -8 -10 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)
0.10
1.00
0
1024
2048
3072
4096
0
1024
2048
3072
4096
DIGITAL INPUT CODE (LSB)
DIGITAL INPUT CODE (LSB)
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5
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs MAX5138/MAX5139
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
GAIN ERROR vs. ANALOG SUPPLY VOLTAGE
MAX5138 toc11 MAX5138 toc10
OFFSET ERROR vs. TEMPERATURE
0.8 0.6 0.4 OFFSET ERROR (mV) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) VAVDD = 2.7V VREF = 2.5V VAVDD = 5.25V VREF = 5V 0.5 0.4 0.3 GAIN ERROR (%FS) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.7
GAIN ERROR vs. TEMPERATURE
MAX5138 toc12
0.036 0.032 GAIN ERROR (%FS) 0.028 0.024 0.020 0.016 0.012 0.008 VAVDD = 2.7V VREF = 2.5V -40 -20 0 20 40 60 80 100 VAVDD = 5.25V VREF = 5V
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX5138 toc13
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5138 toc14
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE (POWER-DOWN MODE)
0.7 0.6 0.5 0.4 TA = +105C 0.3 TA = +25C 0.2 0.1 0 TA = -40C
MAX5138 toc15
1.00 0.98 ANALOG SUPPLY CURRENT (mA) 0.96 0.94 0.92 0.90 0.88 0.86 0.84 0.82 0.80 2.7
VDVDD = 2.7V
1.0 0.9 ANALOG SUPPLY CURRENT (mA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 IDVDD IAVDD
0.8 ANALOG SUPPLY CURRENT (A)
VOUT = VREFO
VOUT = 0
3.2
3.7
4.2
4.7
5.2
-40
-20
0
20
40
60
80
100
2.7
3.2
3.7
4.2
4.7
5.2
ANALOG SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
EXITING/ENTERING POWER-DOWN MODE
MAX5138 toc16
MAJOR CODE TRANSITION
MAX5138 toc17
SETTLING TIME UP
MAX5138 toc18
20mV/div
500mV/div
VOUT
500mV/div
4s/div
1s/div
400ns/div
6
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Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX5138/MAX5139
SETTLING TIME DOWN
MAX5138 toc19
DIGITAL FEEDTHROUGH
MAX5138 toc20
SCLK 500mV/div
5V/div
VOUT
50mV/div
400ns/div
40ns/div
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
MAX5138 toc21
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX5138 toc22
REFERENCE VOLTAGE vs. TEMPERATURE
2.4380 2.4375 VREFO (V) 2.4370 2.4365 2.4360 2.4355
MAX5138 toc23
0.50 0.45 DIGITAL SUPPLY CURRENT (A) 0.40 0.35 VAVDD = 5.25V fSCLK = 1MHz
2.4390 2.4385 2.4380 2.4375 VREFO (V) 2.4370 2.4365 2.4360 2.4355 2.4350 2.4345 TA = -40C TA = +105C TA = +25C
2.4385
0.30 0.25 0.20 0.15 0.10 0.05 0 2.7 3.2 3.7 4.2 4.7 5.2 DIGITAL SUPPLY VOLTAGE (V)
2.4350 2.7 3.2 3.7 4.2 4.7 5.2 2.4345 -40 -20 0 20 40 60 80 100
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
DIGITAL SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE
VAVDD = VDVDD = 5.25V DIGITAL SUPPLY CURRENT (A) 2000
MAX5138 toc24
FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5138 toc25
OUTPUT VOLTAGE vs. SUPPLY CURRENT
VAVDD = 5V 2.44 OUTPUT VOLTAGE (V) VAVDD = 3.3V 2.43
MAX5138 toc26
2500 UP
2.51 2.50 OUTPUT VOLTAGE (V) 2.49 EXTERNAL REF = 2.5V 2.48 2.47 2.46 2.45 INTERNAL REF
2.45
1500 DOWN
1000
2.42
500 2.44 0 0 1 2 3 4 5 6 DIGITAL INPUT VOLTAGE (V) 2.43 -40 -20 0
2.41
2.40 20 40 60 80 100 0 10 20 30 TEMPERATURE (C) OUTPUT CURRENT (mA)
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7
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs MAX5138/MAX5139
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
FULL-SCALE REFERENCE FEEDTHROUGH
MAX5138 toc27
ZERO-SCALE REFERENCE FEEDTHROUGH
MAX5138 toc28
VOUT VREF
500mV/div 500mV/div VREF 500mV/div
0 VOUT 0 VREF 20s/div
VOUT
20mV/div
20s/div
REFERENCE INPUT RESPONSE vs. FREQUENCY
MAX5138 toc29
POWER-UP GLITCH, ZERO-SCALE, EXTERNAL REFERENCE
MAX5138 toc30
POWER-UP GLITCH, ZERO-SCALE, INTERNAL REFERENCE
MAX5138 toc31
0 -5 ATTENUATION (dB) -10
2V/div
2V/div
VAVDD -15 -20 -25 -30 -35 1 10 100 1000 10,000 4s/div VOUT 1V/div
VAVDD
VOUT 4s/div
1V/div
INPUT FREQUENCY (kHz)
POWER-UP GLITCH, MIDSCALE, EXTERNAL REFERENCE
MAX5138 toc32
POWER-UP GLITCH, MIDSCALE, INTERNAL REFERENCE
MAX5138 toc33
DC NOISE SPECTRUM, FFT PLOT BUFFERED OUTPUT
MAX5138 toc34
-40dBm 2V/div RESOLUTION BANDWIDTH = 1Hz 50 LOAD
2V/div
VAVDD
VAVDD 10dB/div
1V/div VOUT 4s/div VOUT
1V/div
25kHz/div 4s/div 2.5kHz/div
8
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Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
Pin Description
PIN 1, 4, 9 2 3 5 6 7 8 10 11 12 13 14 15 16 -- NAME N.C. M/Z LDAC SCLK CS DIN AGND READY DVDD OUT AVDD REFI REFO AGND EP No Connection. Not internally connected. Power-Up Reset Select. Connect M/Z low to AGND to power up the DAC output. Connect M/Z high to power up the DAC output to midscale. Load DAC. Active-low hardware load DAC input. Serial-Clock Input Active-Low Chip-Select Input Data In Analog Ground. Internally connected to AGND. Connect AGND to AGND externally. Data Output Digital Power Supply. Bypass DVDD with a 0.1F capacitor to AGND. Buffered DAC Output Analog Power Supply. Bypass AVDD with a 0.1F capacitor to AGND. Reference Voltage Input. Bypass REFI with a 0.1F capacitor to AGND. Reference Voltage Output DAC Ground. Internally connected to AGND. Connect AGND to AGND externally. Exposed Pad. Not internally connected. Connect to a ground or leave unconnected. Not intended as an electrical connection point. FUNCTION
MAX5138/MAX5139
Detailed Description
The MAX5138/MAX5139 are a family of single-channel, pin-compatible and software-compatible, 16-bit and 12bit DACs. The parts are low-power, buffered voltageoutput, high-linearity DACs. The MAX5138/MAX5139 minimize the digital noise feedthrough from input to output by powering down the SCLK and DIN input buffers after completion of each 24-bit serial input. On powerup, the MAX5138/MAX5139 reset the DAC output to zero or midscale, depending on the state of the M/Z input, providing additional safety for applications that drive valves or other transducers that need to be off on powerup. The MAX5138/MAX5139 contain a segmented resistor string-type DAC, a serial-in parallel-out shift register, a DAC register, power-on reset (POR) circuit, and control logic. On the falling edge of the clock (SCLK) pulse, the serial input (DIN) data is shifted into the device, MSB first. During power-down, an internal 80k resistor pulls DAC outputs to AGND.
Output Amplifier (OUT)
The MAX5138/MAX5139 include an internal buffer for the DAC output. The internal buffer provides improved load regulation and transition glitch suppression for the DAC output. The output buffer slews at 1.25V/s and drives up to 2k in parallel with 200pF. The analog supply voltage (AVDD) determines the maximum output voltage range of the device as AVDD powers the output buffer.
DAC Reference
Internal Reference The MAX5138/MAX5139 feature an internal reference with a nominal +2.44V output. Connect REFO to REFI when using the internal reference. Bypass REFO to AGND with a 47pF (maximum 100pF) capacitor. Alternatively, if heavier decoupling is required, add a 1k resistor in series with a 1F capacitor in parallel with the existing 100pF capacitor. REFO can deliver up to 100A of current with no degradation in performance. Configure other reference voltages by applying a resistive potential divider with a total resistance greater than 33k from REFO to AGND.
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9
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs MAX5138/MAX5139
External Reference The external reference input features a typical input impedance of 113k and accepts an input voltage from +2V to AVDD. Connect an external voltage supply between REFI and AGND to apply an external reference. Leave REFO unconnected. Visit www.maxim-ic.com/products/references for a list of available external voltage-reference devices. AVDD as Reference Connect AVDD to REFI to use AVDD as the reference voltage. Leave REFO unconnected.
high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial-clock input (SCLK). Each serial word is 24 bits. The first 8 bits are the control word followed by 16 data bits (MSB first), as shown in Table 1. The serial input register transfers its contents to the input registers after loading 24 bits of data. To initiate a new data transfer, drive CS high and keep CS high for a minimum of 33ns before the next write sequence. The SCLK can be either high or low between CS write pulses. Figure 1 shows the timing diagram for the complete 3-wire serialinterface transmission. The MAX5138/MAX5139 digital input is double buffered. Depending on the command issued through the serial interface, the input register can be loaded without affecting the DAC register using the write command. To update the DAC register, either pulse the LDAC input low, or use the software LDAC command. Use the writethrough commands (see Table 1) to update the DAC output immediately after the data is received. Only use the writethrough command to update the DAC output immediately.
Serial Interface
The MAX5138/MAX5139 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSPs (Figures 2, 3). The interface provides three inputs, SCLK, CS, and DIN and one output, READY. Use READY to verify communication or to daisy-chain multiple devices (see the READY section). READY is capable of driving a 20pF load with a 30ns (max) delay from the falling edge of SCLK. The chip-select input (CS) frames the serial data loading at DIN. Following a chip-select input's
Table 1. Operating Mode Truth Table
24-BIT WORD CONTROL BITS MSB C7 C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X D8 X D7 X X X DATA BITS LSB D6-D0 X X X NOP LDAC CLR No operation. Set DAC = 1 to move contents of input to DAC register. Software clear. DESC FUNCTION
X DAC X X
0
0
0
0
0
0
1
1
X
X
X
X
X
X
X DAC READY_EN
X
Set DAC = 1 to power Power down DAC. Set Control READY_EN = 1 to enable READY. Linearity Optimize DAC linearity. Write Write to selected input registers (DAC output not affected).
0 0
0 0
0 0
0 1
0 X
1 X
0
1
0
0
0
0
0
0
LIN
0 D8
0 D7
0 D6
X DAC D15 D14 D13 D12 D11 D10 D9
0
0
1
1
X
X
X DAC D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
Write to selected input Write- and DAC register, through DAC output updated (writethrough). NOP No operation.
0
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
*For the MAX5139, D3-D0 are X = don't-care bits.
10
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Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
The MAX5138's DAC code is unipolar binary with VOUT = (code/65536) x VREF. See Table 1 for the serial interface commands. The MAX5139's DAC code is unipolar with V OUT = (code/4096) x VREF. See Table 1 for the serial interface commands. Connect the MAX5138/MAX5139 DVDD supply to the supply of the host DSP or microprocessor. The AVDD supply may be set to any voltage within the 2.7V to 5.25V operating range, but must be greater than or equal to the DVDD supply. D15-D0 are the data bits that are written to the internal register. 3) After clocking in the last data bit, drive CS high. CS must remain high for 33ns before the next transmission is started. Figure 1 shows a write operation for the transmission of 24 bits. If CS is driven high at any point prior to receiving 24 bits, the transmission is discarded.
MAX5138/MAX5139
READY
Connect READY to a microcontroller (C) input to monitor the serial interface for valid communications. The READY pulse appears 24 clock cycles after the negative edge of CS (Figure 4). Since the MAX5138/ MAX5139 look at the first 24 bits of the transmission following the falling edge of CS, it is possible to daisy chain devices with different command word lengths. READY goes high 16ns after CS is driven high.
Writing to the MAX5138/MAX5139
Write to the MAX5138/MAX5139 using the following sequence: 1) Drive CS low, enabling the shift register. 2) Clock 24 bits of data into DIN (C7 first and D0 last), observing the specified setup and hold times. Bits
+5V
SCLK
SK READY* MISO* SS
MAX5138 MAX5139
DIN
SO MICROWIRE PORT
READY*
SI*
MAX5138 MAX5139
DIN
MOSI SPI/QSPI PORT
SCLK CS I/O CS *THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE *MAX5138/MAX5139 BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
SCK
I/O
*THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5138/MAX5139 BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
Figure 2. Connections for MICROWIRE
Figure 3. Connections for SPI/QSPI
CS DIN SCLK 1 READY 1 READY 2 READY 3 2 3 4 20 21 22 23 24 1 2 3 4 5 21 22 23 24 1 2 3 4 5 21 22 23 24 SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA
Figure 4. READY Timing
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Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
Daisy chain multiple MAX5138/MAX5139 devices by connecting the first device conventionally, then connect its READY output to the CS of the following device. Repeat for any other devices in the chain, and drive the SCLK and DIN lines in parallel (Figure 5). When sending commands to daisy-chained MAX5138/MAX5139s, the devices are accessed serially starting with the first device in the chain. The first 24 data bits are read by the first device, the second 24 data bits are read by the second device and so on (Figure 4). Figure 6 shows the configuration when CS is not driven by the C. These devices can be daisy chained with other compatible devices, such as the MAX5510 and the MAX5511. To perform a daisy-chain write operation, drive CS low and output the data serially to DIN. The propagation of the READY signal then controls how the data is read by each device. As the data propagates through the daisy chain, each individual command in the chain is executed on the 24th falling clock edge following the falling edge of the respective CS input. To update just one device in a daisy chain, send the no-op command to the other devices in the chain. If READY is not required, write command 0x03 (power control) and set READY_EN = 0 (see Table 1) to disable the READY output.
MAX5138/MAX5139
software POR, erasing the contents of all registers. The output returns to the state determined by the M/Z input.
Power-Down Mode
The MAX5138/MAX5139 feature a software-controlled power-down mode. The internal reference and biasing circuits power down to conserve power when powered down. In power-down, the output disconnects from the buffer and is grounded with an internal 80k resistor. The DAC register holds the retained code so that the output is restored when powered up. The serial interface remains active in power-down mode.
Load DAC (LDAC) Input
The MAX5138/MAX5139 feature an active-low LDAC logic input that updates the output. Keep LDAC high during normal operation (when the device is controlled only through the serial interface). Drive LDAC low to update the DAC output with data from the input register. Figure 7 shows the LDAC timing with respect to OUT. Holding LDAC low causes the input register to become transparent and data written to the DAC register to immediately update the DAC output. A software command can also activate the LDAC operation. To activate LDAC by software, set control word 0x01 to load the DAC, and all other data bits to don't care. See Table 1 for the data format. This operation updates the DAC output if it is flagged with a 1. If the DAC output is flagged with a 0 it remains unchanged.
Clear Command
The MAX5138/MAX5139 feature a software clear command (0x02). The software clear command acts as a
C MOSI SCK SLAVE 1 DIN SCLK I/O CS READY DIN SCLK CS READY SLAVE 2 DIN SCLK CS READY SLAVE 3
Figure 5. Daisy-Chain Configuration
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______________________________________________________________________________________
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs MAX5138/MAX5139
TO OTHER CHIPS/CHAINS
CSm
C
CS1 CS SCLK DWRITE DREAD INT SLAVE 1 CS SCLK MAX5138 DIN MAX5139
READY
SLAVE 2 CS SCLK MAX5138 MAX5139 DIN
READY
SLAVE N CS SCLK MAX5138 DIN MAX5139 DOUT ERROR READY
Figure 6. Daisy Chain (CS Not Used)
tLDACPWL LDAC tS OUT 2 LSB
Figure 7. Output Timing
______________________________________________________________________________________
13
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs MAX5138/MAX5139
Applications Information
Power-On Reset (POR)
On power-up, the input register is set to zero, and the DAC output powers up to zero or midscale, depending on the configuration of M/Z. Connect M/Z to AGND to power the output to AGND. Connect M/Z to AVDD to power the output to midscale. To guarantee DAC linearity, wait until the supplies have settled. Set the LIN bit in the DAC linearity register; wait 10ms, and clear the LIN bit.
Layout Considerations
Digital and AC transient signals on AGND inputs can create noise at the outputs. Connect both AGND inputs to form the star ground for the DAC system. Refer remote DAC loads to this system ground for the best possible performance. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the MAX5138/MAX5139 AGND. Do not use wire-wrapped boards and sockets. Use shielding to improve noise immunity. Do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the MAX5138/MAX5139 package.
Unipolar Output
The MAX5138/MAX5139 unipolar output voltage range is 0 to VREFI. The output buffer drives a 2k load in parallel with 200pF.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function from a best fit straight line drawn between two codes. This best fit line for the MAX5138 is a line drawn between codes 3072 and 64,512 of the transfer function and the best fit line for the MAX5139 is a line drawn between codes 192 and 4032 of the transfer function, once offset and gain errors have been nullified.
Bipolar Output
Use the MAX5138/MAX5139 in bipolar applications with additional external components (see the Typical Operating Circuit).
Power Supplies and Bypassing Considerations
For best performance, use a separate supply for the MAX5138/MAX5139. Bypass both DVDD and AVDD with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device. Minimize lead lengths to reduce lead inductance. Connect both MAX5138/MAX5139 AGND inputs to the analog ground plane.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the DNL is greater than -1 LSB, the DAC guarantees no missing codes and is monotonic.
Table 2. MAX5138 Input Code vs. Output Voltage
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT, VOUT VREF x (65,535/65,536) VREF x (32,768/65,536) = 1/2 VREF VREF x (1/65,536) 0
Table 3. MAX5139 Input Code vs. Output Voltage
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 XXX 1000 0000 0000 XXX 0000 0000 0001 XXX 0000 0000 0000 XXX ANALOG OUTPUT, VOUT VREF x (4095/4096) VREF x (2048/4096) VREF x (1/4096) 0
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Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
Offset Error
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point where the MSB changes from low to high and all other bits change from high to low, or where the MSB changes from high to low and all other bits change from low to high. The duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse.
MAX5138/MAX5139
Gain Error
Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.
Digital-to-Analog Power-Up Glitch Impulse
The digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode.
Settling Time
The settling time is the amount of time required from the start of a transition, until the DAC output settles to the new output value within the converter's specified accuracy.
Chip Information
PROCESS: BiCMOS
Digital Feedthrough
Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled.
Functional Diagram
AVDD
DVDD
AGND
REFI
REFO INTERNAL BIAS CKT
MAX5138 MAX5139
M/Z
REFERENCE POR CONTROL LOGIC POWER-DOWN CONTROL
CS SCLK DIN SERIAL-TOPARALLEL CONVERTER
INPUT REGISTER
DAC REGISTER
12-/16-BIT DAC
OUT BUFFER
READY
LDAC
AGND
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15
Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs MAX5138/MAX5139
Typical Operating Circuit
DIGITAL POWER SUPPLY ANALOG POWER SUPPLY
100nF
100nF
100nF
DVDD M/Z LDAC CS SCLK DIN READY DAC
AVDD
OUT
MAX5138 MAX5139
REFO REFI 47pF
R1
R2
AGND
*SHOWN IN BIPOLAR CONFIGURATION
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 16 TQFN-EP PACKAGE CODE T1633-5 DOCUMENT NO. 21-0136
16
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Low-Power, Single, 16-/12-Bit, Buffered Voltage-Output DACs
Revision History
REVISION NUMBER 0 1 REVISION DATE 3/09 4/09 Initial release Removed future product reference for MAX5139 DESCRIPTION PAGES CHANGED -- 1
MAX5138/MAX5139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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