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AMIS-30542 AMIS-30542 Micro-Stepping Motor Driver
Introduction
The AMIS-30542 is a micro-stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and a SPI interface with an external microcontroller. It has an on-chip voltage regulator, reset-output and watchdog reset, able to supply peripheral devices. AMIS-30542 contains a current-translation table and takes the next micro-step depending on the clock signal on the "NXT" input pin and the status of the "DIR" (=direction) register or input pin. The chip provides a so-called "speed and load angle" output. This allows the creation of stall detection algorithms and control loops based on load-angle to adjust torque and speed. It is using a proprietary PWM algorithm for reliable current control. The AMIS-30542 is implemented in I2T100 technology, enabling both high-voltage analog circuitry and digital functionality on the same chip. The chip is fully compatible with the automotive voltage requirements. The AMIS-30542 is ideally suited for general-purpose stepper motor applications in the automotive, industrial, medical, and marine environment. With the on-chip voltage regulator it further reduces the BOM for mechatronic stepper applications.
Key Features
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NQFP-32, 7x7 CASE 560AA
MARKING DIAGRAM
* Dual H-Bridge for 2-Phase Stepper Motors * Programmable Peak-Current Up to 2.2 A Continuous (5 A Short * * * * * * * * * * * * * * *
Time) Using a 5-bit Current DAC On-Chip Current Translator SPI Interface Speed and Load Angle Output Seven Step Modes from Full Step Up to 32 Micro-Steps Fully Integrated Current-Sense PWM Current Control with Automatic Selection of Fast and Slow Decay Low EMC PWM with Selectable Voltage Slopes Active Fly-Back Diodes Full Output Protection and Diagnosis Thermal Warning and Shutdown Compatible with 5 V and 3.3 V Microcontrollers Integrated 5 V Regulator to Supply External Microcontroller Integrated Reset Function to Reset External Microcontroller Integrated Watchdog Function These Devices are Pb-Free and are RoHS Compliant*
C542-001 XXXX Y ZZ
= Specific Device Code = Date Code = Assembly Location = Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 27 of this data sheet.
Output current level may be limited by ambient temperature and heat sinking. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2009
October, 2009 - Rev. 0
1
Publication Order Number: AMIS-30542/D
AMIS-30542
BLOCK DIAGRAM
VDD CPN CPP VCP VBB
CLK
Timebase
Vreg
Chargepump
POR
EMC T R A N S L A T O R P W M I-sense
CS DI DO NXT DIR SLA POR/WD CLR ERR TST0
Band- gap Temp . Sense Logic & Registers Load Angle SPI OTP
MOTXP
MOTXN
EMC P W M I-sense
MOTYP
MOTYN
AMIS-30542
GND
Figure 1. Block Diagram AMIS-30542 Table 1. PIN LIST AND DESCRIPTION
Name GND DI CLK NXT DIR ERR SLA / CPN CPP VCP CLR CS VBB MOTYP GND MOTYN MOTXN GND MOTXP VBB / POR/WD TST0 DO VDD Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15, 16 17, 18 19, 20 21, 22 23, 24 25, 26 27 30 28 29 31 32 Ground SPI Data In SPI Clock Input Next micro-step input Direction input Error output (open drain) Speed load angle output No function (to be left open in normal operation) Negative connection of charge pump capacitor Positive connection of charge pump capacitor Charge pump filter-capacitor "Clear" = chip reset input SPI chip select input High voltage supply Input Negative end of phase Y coil output Ground, heat sink Positive end of phase Y coil output Positive end of phase X coil output Ground, heat sink Negative end of phase X coil output High voltage supply input No function (to be left open in normal operation) Power-on-reset and watchdog reset output (open drain) Test pin input (to be tied to ground in normal operation) SPI data output (open drain) Logic supply output (needs external decoupling capacitor) Digital Output Digital Input Digital Output Supply Type 4 Type 6 Type 2 High Voltage High Voltage High Voltage Digital Input Digital Input Supply Driver Output Supply Driver Output Driver Output Supply Driver Output Supply Type 3 Type 1 Type 2 Type 3 Description Type Supply Digital Input Digital Input Digital Input Digital Input Digital Output Analog Output Type 2 Type 2 Type 2 Type 2 Type 4 Type 5 Equivalent Schematic
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POR/WD TSTO MOTXP MOTXP
VDD
32
VBB
DO
31 30
29
28
27
26
25
GND DI CLK NXT DIR ERR SLA
1 2 3 4 5 6 7 8
24 23 22
GND GND MOTXN MOTXN MOTYN MOTYN GND GND
AMIS- 30542
21 20 19 18 17
9
10
11
12
13
14
15
16
MOTYP VBB
MOTYP
CLR
Figure 2. Pin Out AMIS-30542
CPP CPN
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol VBB TST TJ VESD VESD Storage temperature
Parameter Analog DC supply voltage (Note 1)
Junction Temperature under bias (Note 2) Electrostatic discharges on component level, All pins (Note 3) Electrostatic discharges on component level, HiV pins (Note 4)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. For limited time < 0.5 s. 2. Circuit functionality not guaranteed. 3. Human body model (100 pF via 1.5 kW, according to JEDEC EIA-JESD22-A114-B). 4. HiV = High Voltage Pins MOTxx, VBB, GND; (100 pF via 1.5 kW, according to JEDEC EIA-JESD22-A114-B).
VCP
CS
Min -0.3 -55 -50 -2 -8
Max +40 +160 +175 +2 +8
Unit V C C kV kV
Table 3. THERMAL RESISTANCE
Thermal Resistance Junction-to-Ambient Package NQFP-32 Junction-to-Exposed Pad 0.95 1S0P board 60 2S2P board 30 Unit K/W
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EQUIVALENT SCHEMATICS Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used.
4K
IN
Rin
OUT
TYPE 1: CLR input
TYPE 4: DO and ERRB open drain outputs
IN
4K
Rout
SLA
TYPE 2 : CLK , DI, CSB , NXT , DIR inputs
TYPE 5: SLA analog output
VDD
VBB
VDD
VBB
TYPE 3: VDD and VBB power supply inputs
.
Figure 3. In- and Output Equivalent Diagrams
PACKAGE THERMAL CHARACTERISTICS The AMIS-30542 is available in a NQFP32 package. For cooling optimizations, the NQFP has an exposed thermal pad which has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer. Figure 3 gives an example for good power distribution solutions. For precise thermal cooling calculations the major thermal resistances of the device are given. The thermal media to which the power of the devices has to be given are: * Static environmental air (via the case) * PCB board copper area (via the exposed pad) The thermal resistances are presented in Table 5: DC Parameters. The major thermal resistances of the device are the Rth from the junction to the ambient (Rthja) and the overall Rth from the junction to exposed pad (Rthjp). In Table 5 below one can find the values for the Rthja and Rthjp, simulated according to JESD-51: The Rthja for 2S2P is simulated conform JEDEC JESD-51 as follows: * A 4-layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used * Board thickness is 1.46 mm (FR4 PCB material) * The 2 signal layers: 70 mm thick copper with an area of 5500 mm2 copper and 20% conductivity * The 2 power internal planes: 36 mm thick copper with an area of 5500 mm2 copper and 90% conductivity The Rthja for 1S0P is simulated conform to JEDEC JESD-51 as follows: * A 1-layer printed circuit board with only 1 layer * Board thickness is 1.46 mm (FR4 PCB material) * The layer has a thickness of 70 mm copper with an area of 5500 mm2 copper and 20% conductivity
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Figure 4. Example of NQFP-32 PCB Ground Plane Layout in Top View (Preferred Layout at Top and Bottom)
Recommend Operation Conditions Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating
Table 4. OPERATING RANGES
Symbol VBB TJ Analog DC Supply Junction Temperature (Note 5) Parameter
5. No more than 100 cumulative hours in life time above Ttw.
EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIII
NQFP- 32
ELECTRICAL SPECIFICATION ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability.
Min +6 -40
Max +30 +172
Unit V C
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Table 5. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified) Convention: currents flowing in the circuit are defined as positive.
Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit SUPPLY AND VOLTAGE REGULATORS VBB IBB VDD IINT ILOAD IDDLIM ILOAD_PD VDDH VDDL MOTORDRIVER IMDmax,Peak IMdmax,RMS IMdabs IMdrel ISET_TC1 MOTXP MOTXN MOTYP MOTYN Max current through motor coil in normal operation Max RMS current through coil in normal operation Absolute error on coil current Error on current ratio ICOILx / ICOILy Temperature coefficient of coil current set-level, CUR[4:0] = 0...27 Temperature coefficient of coil current set-level, CUR[4:0] = 28...31 On-resistance high-side driver, CUR[4:0] = 0...31 (Note 7) On-resistance low-side driver, CUR[4:0] = 23...31 (Note 7) On-resistance low-side driver, CUR[4:0] = 16...22 (Note 7) On-resistance low-side driver, CUR[4:0] = 9...15 (Note 7) On-resistance low-side driver, CUR[4:0] = 0...8 (Note 7) Pull down current -40C v TJ v 160C TJ = -40C TJ = -40C -10 -7 -240 5525 3906 10 7 mA mA % % ppm/K VDD VBB Nominal operating supply range Total internal current consumption (Note 6) Regulated Output Voltage Internal load current (Note 6) Max Output Current (external and internal loads) Current limitation Output current in Power Down Unloaded outputs 6 V v VBB < 8 V 8 V v VBB v 30 V Pin shorted to ground 1 20 50 150 mA mA Unloaded outputs 4.75 5 6 30 8 5.25 8 V mA V mA
POWER-ON-RESET (POR) VDD Internal POR comparator threshold VDD rising Internal POR comparator threshold VDD falling 4.0 4.25 3.68 4.4 V V
ISET_TC2
-40C v TJ v 160C
-490
ppm/K
RHS RLS3 RLS2 RLS1 RLS0 IMpd DIGITAL INPUTS Ileak VIL VIH Rpd_CLR Rpd_TST DI, CLK NXT, DIR CLR, CS CLR TST0
VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C HiZ mode
0.10 0.16 0.11 0.18 0.22 0.35 0.47 0.74 0.92 1.51 10
0.16 0.31 0.16 0.31 0.31 0.63 0.63 1.25 1.25 2.50
W W W W W W W W W W mA
Input Leakage (Note 8) Logic Low Threshold Logic High Threshold Internal Pulldown Resistor Internal Pulldown Resistor
TJ = 160C 0 2.20 120 3
1 0.65 VDD 300 9
mA V V kW kW
6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Parameter guaranteed by design. 7. Characterization Data Only 8. Not valid for pins with internal Pulldown resistor
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Table 5. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified) Convention: currents flowing in the circuit are defined as positive.
Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit DIGITAL OUTPUTS VOL DO, ERR, POR/WD Logic Low level open drain IOL = 5 mA 0.5 V
THERMAL WARNING AND SHUTDOWN Ttw Ttsd CHARGE PUMP Vcp VCP Cbuffer Cpump Rthja Rthjp NQFP CPP CPN External buffer capacitor External pump capacitor Thermal Resistance Junction-to-Ambient Thermal Resistance Junction-to-Exposed Pad Simulated Conform JEDEC JESD-51, (2S2P) Output voltage 6 V< VBB < 15 V 15 V < VBB < 30 V VBB+8 180 180 2 * VBB - 1.5 VBB+11.5 220 220 30 0.95 VBB+15 470 470 V V nF nF K/W K/W Thermal Warning Thermal shutdown (Notes 9 and 10) 138 145 Ttw + 20 152 C C
PACKAGE THERMAL RESISTANCE VALUE
SPEED AND LOAD ANGLE OUTPUT Vout Voff Gsla Rout Cload SLA Output Voltage Range Output Offset SLA pin Gain of SLA Pin = VBEMF / VCOIL Output Resistance SLA pin Load Capacitance SLA pin SLAG = 0 SLAG = 1 SLAG = 0 SLAG = 1 0.2 -50 -30 0.5 0.25 0.23 1 50 kW pF VDD - 0.2 50 30 V mV mV
9. No more than 100 cumulated hours in life time above Ttw. 10. Thermal shutdown is derived from thermal warning Characterization Data Only.
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Table 6. AC PARAMETERS (The AC parameters are given for VBB and temperature in their operating ranges)
Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit INTERNAL OSCILLATOR fosc MOTOR DRIVER fPWM MOTxx fd tbrise MOTxx Turn-on voltage slope, 10% to 90% PWM frequency Double PWM frequency PWM jitter Depth (Note 11) EMC[1:0] = 00 EMC[1:0] = 01 EMC[1:0] = 10 EMC[1:0] = 11 tbfall MOTxx Turn-off voltage slope, 90% to 10% EMC[1:0] = 00 EMC[1:0] = 01 EMC[1:0] = 10 EMC[1:0] = 11 DIGITAL OUTPUTS tH2L DO ERR Output fall-time from VinH to VinL Capacitive load 400 pF and pullup resistor of 1.5 kW 50 ns Frequency depends only on internal oscillator 20.8 41.6 22.8 45.6 10 350 250 200 100 350 250 200 100 24.8 49.6 kHz kHz % fPWM V/ms V/ms V/ms V/ms V/ms V/ms V/ms V/ms Frequency of internal oscillator 3.6 4 4.4 MHz
CHARGE PUMP fCP tCPU CPN CPP MOTxx Charge pump frequency Startup time of charge pump (Note 12) Spec external components 250 5 kHz ms
CLR FUNCTION tCLR POWER-UP tPU tPOR tRF WATCHDOG tWDTO tWDPR POR/WD Watchdog time out interval Prohibited watchdog acknowledge delay 32 2 512 ms ms POR/WD Powerup time Reset duration Reset filter time VBB = 12 V, ILOAD = 50 mA, CLOAD = 220 nF See FIgure 16 See FIgure 16 100 1 110 ms ms ms CLR Hard reset duration time 100 ms
NXT FUNCTION tNXT_HI tNXT_HI tDIR_SET tDIR_HOLD NXT NXT Minimum, High Pulse Width NXT Minimum, Low Pulse Width NXT Hold Time, Following Change of DIR NXT Hold Time, Before Change of DIR See Figure 5 See Figure 5 See Figure 5 See Figure 5 2 2 0.5 0.5 ms ms ms ms
11. Characterization Data Only 12. Guaranteed by design
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tNXT_HI tNXT_LO
NXT tDIR_SET
0.5 VCC
tDIR_HOLD
DIR
VALID
Figure 5. NXT-Input Timing Diagram
Table 7. SPI TIMING PARAMETERS
Symbol tCLK tCLK_HIGH tCLK_LOW tSET_DI tHOLD_DI tCSB_HIGH tSET_CSB tSET_CLK SPI Clock Period SPI Clock High Time SPI Clock Low Time DI Set Up Time, Valid Data Before Rising Edge of CLK DI Hold Time, Hold Data After Rising Edge of CLK CS High Time CS Set Up Time, CS Low Before Rising Edge of CLK CLK Set Up Time, CLK Low Before Rising Edge of CS Parameter Min 1 100 100 50 50 2.5 100 100 Typ Max Unit ms ns ns ns ns ms ns ns
CS tSET _CSB
0. 2 VCC
tCLK
CLK
0 ,2 VCC
tCLK_HI tSET_DI tHOLD_DI
DI
0.8 VCC
VALID
Figure 6. SPI Timing
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IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII
IIIIIIIII IIIIIIIII IIIIIIIII
0 .2 VCC
III III III
tSET_CLK
0 .8 VCC 0.2 VCC
tCLK _LO
III III III
AMIS-30542
TYPICAL APPLICATION SCHEMATIC
D1 C1 C6 VDD
32
100 nF C4 C5 100 nF R2 R3 R4
100 nF C2
100 nF C3 VBB VBB
27 11
VBAT
100mF
220 nF
14
VCP CPN C7 220 nF CPP MOTXP MOTXN MOTYP MOTYN
POR/WD DIR NXT DO DI
28 5 4 31 2 3 13 12 6 7 1 17 18 23 24 29
9
AMIS-30542
10
25, 26 21, 22
mC
CLK CS CLR ERR SLA C8 R1
M
15, 16 19, 20
GND
TSTO
Figure 7. Typical Application Schematic AMIS-30542
Table 8. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component C1 C2, C3 C4 C5 C6 C7 C8 R1 R2, R3, R4 D1 13. ESR < 1 W. Function VBB Buffer Capacitor (Note 13) VBB Decoupling Block Capacitor VDD Buffer Capacitor VDD Buffer Capacitor Charge Pump Buffer Capacitor Charge Pump Pumping Capacitor Low Pass Filter SLA Low Pass Filter SLA Pullup Resistor Open Drain Output Optional Reverse Protection Diode Typ Value 100 100 100 100 220 220 1 5.6 4.7 MURD530 Tolerance -20 +80% -20 +80% $20% $20% $20% $20% $20% $1% $1% Unit mF nF nF nF nF nF nF kW kW
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FUNCTIONAL DESCRIPTION H-Bridge Drivers A full H-bridge is integrated for each of the two stator windings. Each H-bridge consists of two low-side and two high-side N-type MOSFET switches. Writing logic `0' in bit disables all drivers (high-impedance). Writing logic `1' in this bit enables both bridges and current can flow in the motor stator windings. In order to avoid large currents through the H-bridge switches, it is guaranteed that the top- and bottom-switches of the same half-bridge are never conductive simultaneously (interlock delay). A two-stage protection against shorts on motor lines is implemented. In a first stage, the current in the driver is limited. Secondly, when excessive voltage is sensed across the transistor, the transistor is switched off. In order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. The output slope is defined by the gate-drain capacitance of output transistor and the (limited) current that drives the gate. There are two trimming bits for slope control (see Table 14 SPI Control Parameter Overview EMC[1:0]). The power transistors are equipped with so-called "active diodes": when a current is forced trough the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. This ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain-bulk diode of the transistor. Depending on the desired current range and the micro-step position at hand, the RDS(on) of the low-side
Icoil Set value Actual value 0 TPWM t
transistors will be adapted such that excellent current-sense accuracy is maintained. The RDS(on) of the high-side transistors remain unchanged; see Table 5 DC Parameters for more details. PWM Current Control A PWM comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. This loop then generates a PWM signal, which turns on/off the H-bridge switches. The switching points of the PWM duty-cycle are synchronized to the on-chip PWM clock. The frequency of the PWM controller can be doubled and an artificial jitter can be added (see Table 14 SPI Control Parameter Overview PWMJ). The PWM frequency will not vary with changes in the supply voltage. Also variations in motor-speed or load-conditions of the motor have no effect. There are no external components required to adjust the PWM frequency. Automatic Forward and Slow-Fast Decay The PWM generation is in steady-state using a combination of forward and slow-decay. The absence of fast-decay in this mode, guarantees the lowest possible current-ripple "by design". For transients to lower current levels, fast-decay is automatically activated to allow high-speed response. The selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation.
Forward & Slow Decay Fast Decay & Forward
Forward & Slow Decay
Figure 8. Forward and Slow/Fast Decay PWM
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Automatic Duty Cycle Adaptation In case the supply voltage is lower than 2*Bemf, then the duty cycle of the PWM is adapted automatically to > 50% to maintain the requested average current in the coils. This
Icoil
Duty Cycle < 50%
process is completely automatic and requires no additional parameters for operation. The over-all current-ripple is divided by two if PWM frequency is doubled (see Table 14 SPI Control Parameter Overview PWMF)
Duty Cycle > 50% Actual value
Duty Cycle < 50%
Set value
t TPWM
Figure 9. Automatic Duty Cycle Adaption
Step Translator and Step Mode The step translator provides the control of the motor by means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL and input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode. One out of seven possible stepping modes can be selected through SPI-bits SM[2:0] (see Table 14 SPI Control Parameter Overview ) After power-on or hard reset, the coil-current translator is set to the default 1/32 micro-stepping at position `0'. Upon changing the step mode, the translator jumps to position 0* of the
corresponding stepping mode. When remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. Table 10 lists the output current vs. the translator position. As shown in Figure 10 the output current-pairs can be projected approximately on a circle in the (Ix, Iy) plane. There are, however, two exceptions: uncompensated half step and full step. In these step modes the currents are not regulated to a fraction of Imax but are in all intermediate steps regulated at 100%. In the (Ix, Iy) plane the current-pairs are projected on a square. Table 9 lists the output current vs. the translator position for these cases.
Table 9. SQUARE TRANSLATOR TABLE FOR FULL STEP AND UNCOMPENSATED HALF STEP
Stepmode ( SM[2:0] ) 101 MSP[6:0] 000 0000 001 0000 010 0000 011 0000 100 0000 101 0000 110 0000 111 0000 Uncompensated Half Step 0* 1 2 3 4 5 6 7 110 Full Step - 1 - 2 - 3 - 0 Coil x 0 100 100 100 0 -100 -100 -100 Coil y 100 100 0 -100 -100 -100 0 100 % of Imax
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Table 10. CIRCULAR TRANSLATOR TABLE
Stepmode (SM[2:0]) 000 MSP[6:0] 000 0000 000 0001 000 0010 000 0011 000 0100 000 0101 000 0110 000 0111 000 1000 000 1001 000 1010 000 1011 000 1100 000 1101 000 1110 000 1111 001 0000 001 0001 001 0010 001 0011 001 0100 001 0101 001 0110 001 0111 001 1000 001 1001 001 1010 001 1011 001 1100 001 1101 001 1110 001 1111 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 011 1010 011 1011 011 1100 011 1101 011 1110 011 1111 1/32 `0' 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 001 1/16 0* - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 010 1/8 0* - - - 1 - - - 2 - - - 3 - - - 4 - - - 5 - - - 6 - - - 7 - - - 8 - - - 9 - - - 10 - - - 11 - - - 12 - - - 13 - - - 14 - - - 15 - - - 011 1/4 0* - - - - - - - 1 - - - - - - - 2 - - - - - - - 3 - - - - - - - 4 - - - - - - - 5 - - - - - - - 6 - - - - - - - 7 - - - - - - - 100 1/2 0* - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - 2 - - - - - - - - - - - - - - - 3 - - - - - - - - - - - - - - - Coil x 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 Coil y 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 0 -3.5 -8.1 -12.7 -17.4 -22.1 -26.7 -31.4 -34.9 -38.3 -43 -46.5 -50 -54.6 -58.1 -61.6 -65.1 -68.6 -72.1 -75.5 -79 -82.6 -84.9 -87.2 -89.5 -91.8 -93 -94.1 -95.3 -96.5 -97.7 -98.8 % of Imax
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AMIS-30542
Table 11. CIRCULAR TRANSLATOR TABLE (CONTINUED)
Stepmode ( SM[2:0] ) 000 MSP[6:0] 100 0000 100 0001 100 0010 100 0011 100 0100 100 0101 100 0110 100 0111 100 1000 100 1001 100 1010 100 1011 100 1100 100 1101 100 1110 100 1111 101 0000 101 0001 101 0010 101 0011 101 0100 101 0101 101 0110 101 0111 101 1000 101 1001 101 1010 101 1011 101 1100 101 1101 101 1110 101 1111 110 0000 110 0001 110 0010 110 0011 110 0100 110 0101 110 0110 110 0111 110 1000 110 1001 110 1010 110 1011 110 1100 110 1101 110 1110 110 1111 111 0000 111 0001 111 0010 111 0011 111 0100 111 0101 111 0110 111 0111 111 1000 111 1001 111 1010 111 1011 111 1100 111 1101 111 1110 111 1111 1/32 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 001 1/16 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61 - 62 - 63 - 010 1/8 16 - - - 17 - - - 18 - - - 19 - - - 20 - - - 21 - - - 22 - - - 23 - - - 24 - - - 25 - - - 26 - - - 27 - - - 28 - - - 29 - - - 30 - - - 31 - - - 011 1/4 8 - - - - - - - 9 - - - - - - - 10 - - - - - - - 11 - - - - - - - 12 - - - - - - - 13 - - - - - - - 14 - - - - - - - 15 - - - - - - - 100 1/2 4 - - - - - - - - - - - - - - - 5 - - - - - - - - - - - - - - - 6 - - - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - Coil x 0 -3.5 -8.1 -12.7 -17.4 -22.1 -26.7 -31.4 -34.9 -38.3 -43 -46.5 -50 -54.6 -58.1 -61.6 -65.1 -68.6 -72.1 -75.5 -79 -82.6 -84.9 -87.2 -89.5 -91.8 -93 -94.1 -95.3 -96.5 -97.7 -98.8 -100 -98.8 -97.7 -96.5 -95.3 -94.1 -93 -91.8 -89.5 -87.2 -84.9 -82.6 -79 -75.5 -72.1 -68.6 -65.1 -61.6 -58.1 -54.6 -50 -46.5 -43 -38.3 -34.9 -31.4 -26.7 -22.1 -17.4 -12.7 -8.1 -3.5 Coil y -100 -98.8 -97.7 -96.5 -95.3 -94.1 -93 -91.8 -89.5 -87.2 -84.9 -82.6 -79 -75.5 -72.1 -68.6 -65.1 -61.6 -58.1 -54.6 -50 -46.5 -43 -38.3 -34.9 -31.4 -26.7 -22.1 -17.4 -12.7 -8.1 -3.5 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 % of Imax
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AMIS-30542
Iy
Start = 0 Step 1 Step 2 Step 3 Start = 0
Iy
Step 1 Start = 0
Iy
Step 1
Ix
Step 2
Ix
Ix
Step 3
Step 3
Step 2
1/4th micro step SM[2:0] = 011
Uncompensated Half Step SM[2:0] = 101
Full Step SM[2:0] = 110
Figure 10. Translator Table: Circular and Square
Direction The direction of rotation is selected by means of following combination of the DIR input pin and the SPI-controlled direction bit . (see Table 14 SPI Control Parameter Overview) NXT input Changes on the NXT input will move the motor current one step up/down in the translator table (even when the motor is disabled: = 0). Depending on the
NXT-polarity bit (see Table 14 SPI Control Parameter Overview), the next step is initiated either on the rising edge or the falling edge of the NXT input. Translator Position The translator position MSP[6:0] can be read in SPI Status Register 3 (See Table 15 SR3). This is a 7-bit number equivalent to the 1/32th micro-step from see Table 10 "Circular Translator Table". The translator position is updated immediately following a NXT trigger.
NXT
Update Translator Position
Update Translator Position
Figure 11. Translator Position Timing Diagram
Synchronization of Step Mode and NXT Input When step mode is re-programmed to another resolution (Figure 12), then this is put in effect immediately upon the first arriving "NXT" input. If the micro-stepping resolution is increased, the coil currents will be regulated to the nearest micro-step, according to the fixed grid of the increased resolution. If however the micro-stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro-step translator table.
If the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro-stepping is proceeds according to the translator table. If the translator position is not shared both by the old and new resolution setting, then the micro-stepping proceeds with an offset relative to the translator table (See Figure 12 right hand side).
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AMIS-30542
Change from lower to higher resolution Iy
endpos
Change from higher to lower resolution DIR Iy
endpos
DIR
NXT3 NXT4 NXT2
Iy
NXT1
DIR
NXT1 NXT2
Iy
startpos
DIR
startpos
Ix
Ix
Ix
NXT3
Ix
Halfstep
1/4th step
1/8th step
Halfstep
PC20070604.6
Figure 12. NXT-Step Mode Synchronization
Left: Change from lower to higher resolution. The left-hand side depicts the ending half-step position during which a new step mode resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the micro-step position. Right: Change from higher to lower resolution. The left-hand side depicts the ending micro-step position during which a new step mode resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the half-step position. Note: It is advised to reduce the micro-stepping resolution only at micro-step positions that overlap with desired micro-step positions of the new resolution. Programmable Peak-Current The amplitude of the current waveform in the motor coils (coil peak current = Imax) is adjusted by means of an SPI parameter "CUR[4:0]" (see Table 14 SPI Control Parameter
Peak Current
4.75 A
Overview). Whenever this parameter is changed, the coil-currents will be updated immediately at the next PWM period. Figure 13 presents the Peak-Current and Current Ratings in conjunction to the Current setting CUR[4:0].
Current Range 3 CUR[ 4:0] = 23 - 31 >
2.40 A
Current Range 2 CUR [4:0] = 16 - 22 >
1.20 A Current Range 1 CUR[4:0] = 9 - 15 > 615 mA Current Range 0 CUR[4:0] = 0 - 8 >
0
8
15
22
31
CUR[4:0]
Figure 13. Programmable Peak-Current Overview
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AMIS-30542
Speed and Load Angle Output The SLA-pin provides an output voltage that indicates the level of the Back-e.m.f. voltage of the motor. This Back-e.m.f. voltage is sampled during every so-called "coil current zero crossings". Per coil, two zero-current positions exist per electrical period, yielding in total four zero-current observation points per electrical period.
I COIL
V BEMF t
ZOOM
Previous Micro-step Coil Current Zero Crossing Current Decay Zero Current Next Micro-step
I COIL
t V COIL
VBB Voltage Transient
|V BEMF | t
Figure 14. Principle of Bemf Measurement
Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a transient behavior. As this transient is not always desired in application software, two operating modes can be selected by means of the bit (see "SLA-transparency" in Table 14 SPI Control Parameter Overview). The SLA pin shows in "transparent mode" full visibility of the voltage transient behavior. This allows a sanity-check of the speed-setting versus motor operation and characteristics and supply voltage levels. If the bit "SLAT" is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the SLA-pin. Because the transient
behavior of the coil voltage is not visible anymore, this mode generates smoother Back e.m.f. input for post-processing, e.g. by software. In order to bring the sampled Back e.m.f. to a descent output level (0 V to 5 V), the sampled coil voltage VCOIL is divided by 2 or by 4. This divider is set through an SPI bit . (see Table 14 SPI Control Parameter Overview) The following drawing illustrates the operation of the SLA-pin and the transparency-bit. "PWMsh" and "ICOIL = 0" are internal signals that define together with SLAT the sampling and hold moments of the coil voltage.
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AMIS-30542
VCOIL
div2 div4
Ssh
Sh
buf
SLA- pin
Csh
Ch
Icoil=0 PWMsh
SLAT NOT(Icoil=0)
PWMsh Icoil=0 SLAT VCOIL
t SLA-pin
last sample is retained
VBEMF
previous output is kept at SLA pin
retain last sample
t
SLAT = 1 => SLA-pin is "transparent" during VBEMF sampling @ Coil Current Zero Crossing. SLA-pin is updated "real-time".
SLAT = 0 => SLA-pin is not "transparent" during VBEMF sampling @ Coil Current Zero Crossing. SLA-pin is updated when leaving current-less state.
Figure 15. Timing Diagram of SLA-Pin
Warning, Error Detection and Diagnostics Feedback Thermal Warning and Shutdown When junction temperature rises above TTW, the thermal warning bit is set (Table 16 SPI Status registers Address SR0). If junction temperature increases above thermal shutdown level, then the circuit goes in "Thermal Shutdown" mode () and all driver transistors are disabled (high impedance) (see Table 16 SPI Status registers Address SR2). The conditions to reset flag is to be at a temperature lower than Ttw and to clear the flag by reading it using any SPI read command. Overcurrent Detection The overcurrent detection circuit monitors the load current in each activated output stage. If the load current exceeds the over-current detection threshold, then the overcurrent flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. Each driver transistor has an individual detection bit in (see Table 16 SPI Status registers Address SR1 and SR2: and ). Error condition is latched and the microcontroller needs to clean the status bits to reactivate the drivers. Note: Successive reading the SPI StatusRegisters 1 and 2 in case of a short circuit condition, may lead to damage to the drivers.
Open Coil/Current Not Reached Detection Open coil detection is based on the observation of 100% duty cycle of the PWM regulator. If in a coil 100% duty cycle is detected for longer than 200 ms then the related driver transistors are disabled (high-impedance) and an appropriate bit in the SPI status register is set ( or ). (Table 16) When the resistance of a motor coil is very large and the supply voltage is low, it can happen that the motor driver is not able to deliver the requested current to the motor. Under these conditions the PWM controller duty cycle will be 100% and after 200 ms the error pin and , will flag this situation (motor current is kept alive). This feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil-current or else the coil current should be reduced. Charge Pump Failure The charge pump is an important circuit that guarantees low RDS(on) for all drivers, especially for low supply voltages. If supply voltage is too low or external components are not properly connected to guarantee RDS(on) of the drivers, then the bit is set (Table 16). Also after POR the charge pump voltage will need some time to exceed the required threshold. During that time will be set to "1".
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AMIS-30542
Error Output This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination of: NOT(ERRB) = OR OR OR OR OR Logic Supply Regulator AMIS-30542 has an on-chip 5 V low-drop regulator with external capacitor to supply the digital part of the chip, some low-voltage analog blocks and external circuitry. The voltage level is derived from an internal bandgap reference. To calculate the available drive-current for external
VBB
circuitry, the specified Iload should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. See Table 5. DC parameters Power-On Reset (POR) Function The open drain output pin POR/WD provides an "active low" reset for external purposes. At powerup of AMIS-30542, this pin will be kept low for some time to reset for example an external microcontroller. A small analogue filter avoids resetting due to spikes or noise on the VDD supply.
t VDD VDDH VDDL t < tRF tPU tPD
POR/WD pin tPOR tRF
Figure 16. Power-on-Reset Timing Diagram
Watchdog Function The watchdog function is enabled/disabled through bit (Table 13: SPI CONTROL REGISTERS (ALL SPI control registers have Read/Write Access and default to "0" after power-on or hard reset.)). Once this bit has been set to "1" (watchdog enable), the microcontroller needs to re-write this bit to clear an internal timer before the watchdog timeout interval expires. In case the timer is activated and WDEN is acknowledged too early (before tWDPR) or not within the interval (after tWDTO), then a reset of the microcontroller will occur through POR/WD pin. In addition, a warm/cold boot bit is available (see Tables 16 and 17) for further processing when the external microcontroller is alive again. CLR pin (=Hard Reset) Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside AMIS-30542, the input CLR needs to be pulled to logic 1 during minimum time given by tCLR. (Table 6 AC Parameters). This reset function clears all internal registers without the need of a power-cycle, except in sleep mode. The operation of all
analog circuits is depending on the reset state of the digital, charge pump remains active. Logic 0 on CLR pin resumes normal operation again. The voltage regulator remains functional during and after the reset and the POR/WD pin is not activated. Watchdog function is reset completely. Sleep Mode The bit in SPI Control Register 2 (See Table 12) is provided to enter a so-called "sleep mode". This mode allows reduction of current-consumption when the motor is not in operation. The effect of sleep mode is as follows: * The drivers are put in HiZ * All analog circuits are disabled and in low-power mode * All internal registers are maintaining their logic content * NXT and DIR inputs are forbidden * SPI communication remains possible (slight current increase during SPI communication) * Oscillator and digital clocks are silent, except during SPI communication
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AMIS-30542
The voltage regulator remains active but with reduced current-output capability (ILOADSLP). The watchdog timer stops running and it's value is kept in the counter. Upon leaving sleep mode, this timer continues from the value it had before entering sleep mode.
VBB
Normal operation is resumed after writing logic `0' to bit . A startup time is needed for the charge pump to stabilize. After this time, NXT commands can be issued.
t VDD VDDH t tPOR tPU
POR/WD pin tDSPI tWDRD tPOR
Enable WD > tWDPR and < tWDTO Acknowledge WD t tWDTO = tWDPR or = tWDTO
WD timer
t
Figure 17. Watchdog Timing Diagram
NOTE: tDSPI is the time needed by the external microcontroller to shift-in the bit after a powerup.
The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See also Table 13: SPI CONTROL REGISTERS (ALL SPI control registers have Read/Write Access and default to "0" after power-on or hard reset). The timing is given in Table 12 below.
Table 12. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0]
Index WDT[3:0] 0 1 2 3 4 5 6 7 0000 0001 0010 0011 0100 0101 0110 0111 tWDTO (ms) 32 64 96 128 160 192 224 256 8 9 10 11 12 13 14 15 Index WDT[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 tWDTO (ms) 288 320 352 384 416 448 480 512
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AMIS-30542
SPI INTERFACE The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with AMIS-30542. The implemented SPI block is designed to interface directly with numerous micro-controllers from several manufacturers. AMIS-30542 acts always as a Slave and can't initiate any transmission. The operation of the device is configured and controlled by means of SPI registers which are observable for read and/or write from the Master. SPI Transfer Format and Pin Signals During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI).
# CLK cycle CS
DO signal is the output from the Slave (AMIS-30542), and DI signal is the output from the Master. A chip select line (CS) allows individual selection of a Slave SPI device in a multiple-slave system. The CS line is active low. If AMIS-30542 is not selected, DO is pulled up with the external pull up resistor. Since AMIS-30542 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The SPI clock idles low between the transferred bytes. The diagram below is both a Master and a Slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave.
4 5 6 7 8
1
2
3
CLK
DI
MSB
6
5
4
3
2
1
LSB
DO
MSB
6
5
4
3
2
1
LSB
Figure 18. Timing Diagram of a SPI Transfer
NOTE:
At the falling edge of the eight clock pulse the data-out shift register is updated with the content of the addressed internal SPI register. The internal SPI registers are updated at the first rising edge of the AMIS-30542 system clock when CS = High
Transfer Packet: Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes.
BYTE 1 Command and SPI Register Address
MSB CMD2 CMD1 LSB CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 MSB D7 D6 D5 D4 D3 D2 D1
Command
SPI Register Address
Figure 19. SPI Transfer Packet
Byte 1 contains the Command and the SPI Register Address and indicates to AMIS-30542 the chosen type of operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received from AMIS-30542 in a READ operation.
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III III III IIII IIII
BYTE 2 Data
LSB D0
AMIS-30542
Two command types can be distinguished in the communication between master and AMIS-30542: * READ from SPI Register with address ADDR[4:0]: CMD2 = "0" * WRITE to SPI Register with address ADDR[4:0]: CMD2 = "1" READ Operation If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a READ command. This READ command contains the address of the SPI register to be read out. At the falling edge of the eight clock pulse the data-out shift register is updated with the content of the corresponding internal SPI register. In the next 8-bit clock pulse train this data is shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive command or dummy data.
Registers are updated with internal status at the rising edge of the internal AMIS-30542 clock when CS = 1
CS
COMMAND
DI
DATA from previous command or NOT VALID after POR or RESET
READ DATA from ADDR 1
COMMAND or DUMMY
DATA
DO OLD DATA or NOT VALID
DATA
DATA from ADDR1
Figure 20. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master
All 4 Status Registers (see SPI Registers) contain 7 data bits and a parity check bit The most significant bit (D7) represents a parity of D[6:0]. If the number of logical ones in D[6:0] is odd, the parity bit D7 equals "1". If the number of logical ones in D[6:0] is even then the parity bit D7 equals "0". This simple mechanism protects against noise and increases the consistency of the transmitted data. If a parity check error occurs it is recommended to initiate an additional READ command to obtain the status again. Also the Control Registers can be read out following the same routine. Control Registers don't have a parity check. The CS line is active low and may remain low between successive READ commands as illustrated in Figure 22. There is however one exception. In case an error condition is latched in one of Status Registers (see SPI Registers) the ERR pin is activated. (See Section Error Output). This signal flags a problem to the external microcontroller. By reading the Status Registers information about the root cause of the problem can be determined. After this READ operation the Status Registers are cleared. Because the Status Registers and ERR pin (see SPI Registers) are only updated by the internal system clock when the CS line is high, the Master
should force CS high immediately after the READ operation. For the same reason it is recommended to keep the CS line high always when the SPI bus is idle. WRITE Operation If the Master wants to write data to a Control Register it initiates the communication by sending a WRITE command. This contains the address of the SPI register to write to. The command is followed with a data byte. This incoming data will be stored in the corresponding Control Register after CS goes from low to high! AMIS-30542 responds on every incoming byte by shifting out via DO the data stored in the last received address. It is important that the writing action (command - address and data) to the Control Register is exactly 16 bits long. If more or less bits are transmitted the complete transfer packet is ignored. A WRITE command executed for a read-only register (e.g. Status Registers) will not affect the addressed register and the device operation. Because after a power-on-reset the initial address is unknown the data shifted out via DO is not valid.
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AMIS-30542
The NEW DATA is written into the corresponding internal register at the rising edge of CS
CS
COMMAND
DI
DATA from previous command or NOT VALID after POR or RESET
DATA
NEW DATA for ADDR3
WRITE DATA to ADDR3
DATA
OLD DATA or NOT VALID
DATA
OLD DATA from ADDR3
DO
Figure 21. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3
Examples of combined READ and WRITE Operations In the following examples successive READ and WRITE operations are combined. In Figure 22 the Master first reads the status from Register at ADDR4 and at ADDR5 followed
Registers are updated with the internal status at the rising edge of the internal AMIS-30542 clock when CS = 1
by writing a control byte in Control Register at ADDR2. Note that during the write command the old data of the pointed register is returned at the moment the new data is shifted in
The NEW DATA is written into the corresponding internal register at the rising edge of CS
CS
COMMAND
DI
DATA from previous command or NOT VALID after POR or RESET
COMMAND
READ DATA from ADDR5
COMMAND
WRITE DATA to ADDR 2
DATA
NEW DATA for ADDR2
READ DATA from ADDR4
DATA
OLD DATA or NOT VALID
DATA
DATA from ADDR4
DATA
DATA from ADDR5
DATA
OLD DATA from ADDR2
DO
Figure 22. 2 Successive READ Commands Followed by a WRITE Command
After the write operation the Master could initiate a read back command in order to verify the data correctly written as illustrated in Figure 23. During reception of the READ command the old data is returned for a second time. Only after receiving the READ command the new data is
transmitted. This rule also applies when the master device wants to initiate an SPI transfer to read the Status Registers. Because the internal system clock updates the Status Registers only when CS line is high, the first read out byte might represent old status information.
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AMIS-30542
Registers are updated with the internal status at the rising edge of CS The NEW DATA is written into the corresponding internal register at the rising edge of CS
CS
COMMAND
DI
DATA from previous command or NOT VALID after POR or RESET
DATA
NEW DATA for ADDR2
COMMAND
READ DATA from ADDR2 COMMAND or DUMMY
WRITE DATA to ADDR2
DATA
DO OLD DATA or NOT VALID
DATA
OLD DATA from ADDR2
DATA
OLD DATA from ADDR2
DATA
NEW DATA from ADDR2
Figure 23. A WRITE Operation Where DATA from the Master is Written in SPI Register with Address 2 Followed by a READ Back Operation to Confirm a Correct WRITE Operation
NOTE: The internal data-out shift buffer of AMIS-30542 is updated with the content of the selected SPI register only at the last (every eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
Table 13. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to "0" after power-on or
hard reset) Structure Content Access Address WR (00h) CR0 (01h) CR1 (02h) CR2 (03h) CR2 (08h) Reset Data Data Data Data Data DIRCTRL MOTEN M[1:0] Bit 7 R/W 0 WDEN SM[2:0] NXTP SLP - SLAG - SLAT PWMF - - Bit 6 R/W 0 Bit 5 R/W 0 WDT[3:0] Bit 4 R/W 0 Bit 3 R/W 0 Bit 2 R/W 0 - CUR[4:0] PWMJ - StrC - StrE[1:0] EMC[1:0] - Bit 1 R/W 0 - Bit 0 R/W 0 -
StrB[1:0]
Where: R/W Reset:
Read and Write access Status after power-On or hard reset
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Table 14. SPI CONTROL PARAMETER OVERVIEW
Symbol DIRCTRL Description Controls the direction of rotation (in combination with logic level on input DIR) = 0 Status = 0 = 1 = 1 = 0 = 1 NXTP EMC[1:0] Selects if NXT triggers on rising or falling edge Turn On - Turn-off Slopes of motor driver (Note 14) = 0 = 1 00 01 10 11 SLAT SLAG PWMF PWMJ SM[2:0] Speed load angle transparency bit Speed load angle gain setting Enables doubling of the PWM frequency (Note 14) Enables jittery PWM Stepmode = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 000 001 010 011 100 101 110 111 SLP MOTEN M[1:0] Enables sleep mode Activates the motor driver outputs PWM Mode Control = 0 = 1 = 0 = 1 00 01 10 11 StrB[1:0] PWM Strobe B Control: DON mask comparator time (Note 16) 00 01 10 11 StrC StrE[1:0] PWM Strobe C Control: Switch time top/bottom regulation PWM Strobe E Control: Compensation bridge active time (Note 16) = 0 = 1 00 01 10 11 14. The typical values can be found in Table 5: DC Parameters and in Table 6: AC parameters 15. Depending on the wiring of the motor connections 16. The duration is depending on the selected PWM frequency Value CW motion (Note 15) CCW motion (Note 15) CCW motion (Note 15) CW motion (Note 15)
Trigger on rising edge Trigger on falling edge Very Fast Fast Slow Very Slow SLA is transparent SLA is NOT transparent Gain = 0.5 Gain = 0.25 Default Frequency Double Frequency Jitter disabled Jitter enabled 1/32 Micro - Step 1/16 Micro - Step 1/8 Micro - Step 1/4 Micro - Step Compensated Half Step Uncompensated Half Step Full Step n.a. Active mode Sleep mode Drivers disabled Drivers enabled Default control DCMin Mode 1 DCMin Mode 1' DCMin Mode 2 4 PWM clock cycles 8 PWM clock cycles 12 PWM clock cycles 19 PWM clock cycles 86% duty cycle PWM regulator 75% duty cycle PWM regulator 4 PWM clock cycles 8 PWM clock cycles 12 PWM clock cycles 19 PWM clock cycles
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AMIS-30542
CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.
Table 15. SPI CONTROL PARAMETER OVERVIEW CUR[4:0]
Current Range (Note 18) Index CUR[4:0] 0 1 2 3 0 4 5 6 7 8 9 10 11 1 12 13 14 15 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Current (mA) (Note 17) 122 230 350 370 410 455 500 550 615 680 750 840 916 1010 1110 1205 3 2 Current Range (Note 18) Index CUR[4:0] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Current (mA) (Note 17) 1390 1520 1680 1810 2000 2165 2400 2650 2880 3090 3325 3570 3825 4090 4370 4750
17. Typical current amplitude at TJ = 125 18. Reducing the current over different current ranges might trigger overcurrent detection. See dedicated application note for solutions
SPI Status Register Description
All 4 SPI status registers have Read Access and are default to "0" after power-on or hard reset.
Table 16. SPI STATUS REGISTERS
Structure Content Access Address SR0 (04h) SR1 (05h) SR2 (06h) SR3 (07h) Reset Data is not latched Data is latched Data is latched Data is not latched Bit 7 R 0 PAR PAR PAR PAR Bit 6 R 0 TW OVCXPT OVCYPT Bit 5 R 0 CPfail OVCXPB OVCYPB Bit 4 R 0 WD OVCXNT OVCYYNT Bit 3 R 0 OPENX OVCXNB OVCYNB MSP[6:0] Bit 2 R 0 OPENY - TSD Bit 1 R 0 - - - Bit 0 R 0 - - -
Where: R Reset PAR
Read only mode access Status after power-on or hard reset Parity check
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AMIS-30542
Table 17. SPI STATUS FLAGS OVERVIEW
Mnemonic CPFail Flag Charge pump failure Length (bit) 1 Related SPI Register Status Register 0 Comment `0' = no failure `1' = failure: indicates that the charge pump does not reach the required voltage level. Note 1 Translator micro step position `1' = Open coil detected `1' = Open coil detected `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor XN-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor XN-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor XP-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor XP-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor YN-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor YN-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor YP-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor YP-terminal Reset State `0'
MSP[6:0] OPENX OPENY OVCXNB
Micro-step position OPEN Coil X OPEN Coil Y OVer Current on X H-bridge; MOTXN terminal; Bottom tran. OVer Current on X H-bridge; MOTXN terminal; Top transist. OVer Current on X H-bridge; MOTXP terminal; Bottom tran. OVer Current on X H-bridge; MOTXP terminal; Top transist. OVer Current on Y H-bridge; MOTYN terminal; Bottom tran. OVer Current on Y H-bridge; MOTYN terminal; Top transist. OVer Current on Y H-bridge; MOTYP terminal; Bottom tran. OVer Current on Y H-bridge; MOTYP terminal; Top transist. Thermal shutdown Thermal warning Watchdog event
7 1 1 1
Status Register 3 Status Register 0 Status Register 0 Status Register 1
`0000000' `0' `0' `0'
OVCXNT
1
Status Register 1
`0'
OVCXPB
1
Status Register 1
`0'
OVCXPT
1
Status Register 1
`0'
OVCYNB
1
Status Register 2
`0'
OVCYNT
1
Status Register 2
`0'
OVCYPB
1
Status Register 2
`0'
OVCYPT
1
Status Register 2
`0'
TSD TW WD NOTE:
1 1 1
Status Register 2 Status Register 0 Status Register 0 `1' = watchdog reset after time-out
`0' `0' `0'
WD - This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to "1" after reset, it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be cleared only when the master writes "0" to WDEN bit.
Table 18. ORDERING INFORMATION
Part No. AMIS30542C5421RG AMIS30542C54212G Peak Current 3200 mA 3200 mA Temperature Range -40C to 125C -40C to 125C Package NQFP-32 (7 x 7 mm) (Pb-Free) NQFP-32 (7 x 7 mm) (Pb-Free) Shipping Units / Tubes Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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27
AMIS-30542
PACKAGE DIMENSIONS
NQFP-32, 7x7 CASE 560AA-01 ISSUE O
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28
AMIS-30542
PACKAGE DIMENSIONS
NQFP-32, 7x7 CASE 560AA-01 ISSUE O
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