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Features
* * * * * * * * * *
Usable for Automotive 12V/24V and Industrial Applications Maximum High-speed Data Transmissions up to 1 MBaud Fully Compatible with ISO 11898 Controlled Slew Rate Standby Mode TXD Input Compatible to 3.3V Short-circuit Protection Overtemperature Protection High Voltage Bus Lines Protection, -40V to +40V High Speed Differential Receiver Stage with a Wide Common Mode Range, -10V to +10V, for High Electromagnetic Immunity (EMI) * Fully Controlled Bus Lines, CANH and CANL to Minimize Electromagnetic Emissions (EME) * High ESD Protection at CANH, CANL HBM 8 kV, MM 300V
High-speed Can Transceiver ATA6660
1. Description
The ATA6660 is a monolithic circuit based on the Atmel(R)'s Smart Power BCD60-III technology. It is especially designed for high speed CAN-Controller (CAN-C) differential mode data transmission between CAN-Controllers and the physical differential bus lines. Figure 1-1. Block Diagram
3 VCC
1 TXD
TXD Input Stage
Overtemperature and Short Circuit Protection
Driver
7 CANH 8 RS
Constant Slope/ Standby
4 RXD
Reference Voltage 0.5*VCC
Receiver
6 CANL 5 VREF
2 GND
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2. Pin Configuration
Figure 2-1. Pinning SO8
TXD GND VCC RXD 1 2 3 4 8 7 6 5 RS CANH CANL VREF
Table 2-1.
Pin 1 2 3 4 5 6 7 8
Pin Description
Symbol TXD GND VCC RXD VREF CANL CANH RS Function Transmit data input Ground Supply voltage Receive data output Reference voltage output Low level CAN voltage input/output High level CAN voltage input/output Switch Standby Mode/Normal Mode
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3. Functional Description
The ATA6660 is a monolithic circuit based on Atmel's Smart Power BCD60-III technology. It is especially designed for high-speed differential mode data transmission in harsh environments like automotive and industrial applications. Baudrate can be adjusted up to 1 Mbaud. The ATA6660 is fully compatible to the ISO11898, the developed standard for high speed CAN-C (Controller Area Network) communication.
3.1
Voltage Protection and ESD
High voltage protection circuitry on both line pins, CANH (pin 7) and CANL (pin 6), allow bus line voltages in the range of -40V to +40V. ESD protection circuitry on line pins allow HBM = 8 kV, MM = 300V. The implemented high voltage protection on bus line output/input pins (7/6) makes the ATA6660 suitable for 12V automotive applications as well as 24V automotive applications.
3.2
Slope Control
A fixed slope is adjusted to prevent unsymmetrical transients on bus lines causing EMC problems. Controlled bus lines, both CANH and CANL signal, will reduce radio frequency interference to a minimum. In well designed bus configurations the filter design costs can be reduced dramatically.
3.3
Overcurrent Protection
In the case of a line shorts, like CANH to GND, CANL to VCC, integrated short current limitation allows a maximum current of ICANH_SC or ICANL_SC. If junction temperature rises above 165C an internal overtemperature protection circuitry shuts down both output stages, the receiver will stay activated.
3.4
Standby Mode
The ATA6660 can be switched to Standby Mode by forcing the voltage VRS > 0.87 x VCC. In Standby Mode the supply current will reduce dramatically, supply current during Standby Mode is typical 600 A (IVCC_stby). Transmitting data function will not be supported, but the opportunity will remain to receive data. A high-speed comparator is listening for activities on the bus. A dominant bus signal will force the output RXD to a low level in typical tdRXDL = 400 ns. If the RS pin is not connected, causing through a broken connection to the controller, the ATA6660 will switch to Standby Mode automatically.
3.5
High-speed Receiver
In Normal Mode a fast receiver circuitry combined with a resistor network is able to detect differential bus line voltages Vrec_th > 0.9V as dominant bit, differential bus line voltages Vrec_th < 0.5V as recessive bit. The wide receiver common mode range, -10V to +10V, combined with a symmetrical differential receiver stage offers high immunity against electromagnetic interference. A typical hysteresis of 70 mV is implemented. Dominant differential bus voltages forces RXD output (pin 4) to low level, recessive differential bus voltages to high level.
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3.6
TXD Input
The input stage pin 1 (TXD) is compatible for 3.3V output levels from new controller families. Pull-up resistance (25 k) forces the IC to Recessive Mode, if TXD-Pin is not connected. TXD low signal drives the transmitter into dominant state.
3.7
Transmitter
A integrated complex compensation technique allows stable data transmission up to 1 MBaud. Low level on TXD input forces bus line voltages CANH to 3.5V, CANL to 1.5V with a termination resistor of 60. In the case of a line short circuit, like CANH to GND, CANL to VCC, integrated short current limitation circuitry allows a maximum current of 150 mA. If junction temperature rises above typical 163C an internal overtemperature protection shuts down both output stages, the Receive Mode will stay activated.
3.8
Split Termination Concept
With a modified bus termination (see Figure 8-3 on page 10) a reduction of emission and a higher immunity of the bus system can be achieved. The one 120 resistor at the bus line end nodes is split into two resistors of equal value, i.e., two resistors of 60. The resistors for the stub nodes is recommended with two resistors of 1.3 k. (for example 8 stub nodes and 2 bus end nodes) Notice: The bus load of all the termination resistors has to stay within the range of 50 to 65. The common mode signal at the centre tap of the termination is connected to ground via a capacitor of e.g., Csplit = 10 nF to 100 nF. A separate ground lead to the ground pin of the module connector is recommended.
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage DC voltage at pins 1, 4, 5 and 8 DC voltage at pins 6 and 7 Transient voltage at pins 6 and 7 Storage temperature Operating ambient temperature ESD classification ESD classification TStg Tamb All pins Pin 6, 7 versus pin 2 HBM ESD S.5.1 MM JEDEC A115A HBM 1.5 k, 100 pF MM 0, 200 pF Symbol VCC VTXD, VREF, VRS, VRXD VCANH, VCANL 0V < VCC < 5.25V; no time limit Conditions Min. -0.3 -0.3 -40.0 -150 -55 -40 3000 200 8000 300 Max. +6 VCC +0.3 +40.0 +100 +150 +125 Unit V V V V C C V V V V
5. Thermal Resistance
Parameters Thermal resistance from junction to ambient Symbol RthJA Value 160 Unit K/W
6. Truth Table
VCC 4.75V to 5.25V 4.75V to 5.25V 4.75V to 5.25V TXD 0 1 (or floating) X RS < 0.3 x VCC < 0.3 x VCC > 0.87 x VCC CANH 3.5V 0.5 x VCC 0.5 x VCC CANL 1.5V 0.5 x VCC 0.5 x VCC Bus State Dominant Recessive Recessive RXD 0 1 1
7. RS (Pin 8) Functionality
Slope Control Mode Standby Constant slope control Voltage and Current Levels IRS < | 10 A | IRS 500 A
VRS > 0.87 x VCC
VRS < 0.3 x VCC
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8. Electrical Characteristics
VCC = 4.75V to 5.25V; Tamb = -40C to +125C; RBus = 60; unless otherwise specified. All voltages referenced to ground (pin 2); positive input current. No. 1 1.1 1.2 1.3 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 4 4.1 4.2 5 5.1 Parameters Supply Current Supply current dominant Supply current recessive VTXD = 0V VRS = 0V VTXD = 5V VRS = 0V 3 3 3 Ivcc_dom Ivcc_rec Ivcc_stby 45 10 600 60 15 980 mA mA A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Supply current standby VRS = 5V Transmitter Data Input TXD HIGH level input voltage LOW level input voltage VTXD = 5V VRS = 0V VTXD = 0V VRS = 0V
1 1 1 1
VTXDH VTXDL IIH IIL
2 -0.3 -1 -500
VCC + 0.3 +1 0 -50
V V A A
A A A A
HIGH level input current VTXD = VCC LOW level input voltage VTXD = 0V Receiver Data Output RXD High level output voltage IRXD = -100 A
4 4 4 4
VRXDH VRXDL IRXDs1 IRXDs2
0.8 x VCC 0 -3 2
VCC 0.2 x VCC -1 6
V V mA mA
A A A A
Low level output voltage IRXD = 1 mA Short current at RXD Short current at RXD VTXD = 5V VRXD = 0V VTXD = 0V VRXD = 5V VRS = 0V; -50 A < I5 < 50 A VRS = 5 V; -5 A < I5 < 5 A
Reference Output Voltage VREF Reference output voltage Normal Mode Reference output voltage Standby Mode 5 5 Vref_no Vref_stby 0.45 VCC 0.4 x VCC 0.55 VCC 0.6 VCC V V A A
DC Bus Transmitter CANH; CANL Recessive bus voltage IO(CANH)(reces) IO(CANL)(reces) CANH output voltage dominant CANL output voltage dominant VTXD = VCC; no load -40V < VCANH; VCANL < 40V; 0V < VCC < 5.25V VTXD = 0V VTXD = 0V 6, 7 VCANH; VCANL IO_reces VCANH VCANL 2.0 2.5 3.0 V A
5.2
6, 7
-5
+5
mA
A
5.3 5.4
6, 7 6, 7
2.8 0.5
3.5 1.5
4.5 2.0
V V
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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8. Electrical Characteristics (Continued)
VCC = 4.75V to 5.25V; Tamb = -40C to +125C; RBus = 60; unless otherwise specified. All voltages referenced to ground (pin 2); positive input current. No. 5.5 5.6 5.7 5.8 6 6.1 Short-circuit CANH current Short-circuit CANL current Differential receiver threshold voltage Normal Mode Differential receiver threshold voltage Standby Mode Differential input hysteresis CANH and CANL common mode input resistance Differential input resistance Matching between CANH and CANL common mode input resistance CANH, CANL input capacitance Differential input capacitance CANH, CANL input leakage input current Thermal Shut-down Shut-down junction temperature for CANH/CANL Switch on junction temperature for CANH/CANL Temperature hysteresis TJ(SD) 150 163 175 C B VCC = 0V VCANH = 3.5V VCANL = 1.5V Parameters Differential bus output voltage (VCANH - VCANL) Test Conditions VTXD = 0V; RL = 45 to 60; VCC = 4.9V VTXD = VCC; no load VCANH = -10V TXD = 0V VCANL = 18V TXD = 0V Pin 6, 7 6, 7 6, 7 6, 7 Symbol Vdiffdom Vdiffrec ICANH_SC ICANL_SC Min. 1.5 -500 -35 50 Typ. 2 Max. 3.0 +50 -100 150 Unit V mV mA mA Type* A A A A
DC Bus Receiver CANH; CANL -10V < VCANH < +10V -10V < VCANL < +10V VRS = VCC 6, 7 Vrec_th 0.5 0.7 0.9 V A
6.2
6, 7
Vrec_th_stby Vdiff(hys) Ri Rdiff
0.5
0.7
0.9
V
A
6.3
6, 7
70
mV
A
6.4
6, 7
5
15
25
k
A
6.5
6, 7
10
30
100
k
A
6.6
6, 7
Ri_m
-3
+3
%
A
6.7 6.8
6, 7 6, 7
Ci Cdiff ILI(CANH); ILI(CANL)
20 10
pF pF
D D
6.9 7 7.1
6, 7
250
A
A
7.2 7.3
TJ(SD) THys
140
154 10
165
C K
B B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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8. Electrical Characteristics (Continued)
VCC = 4.75V to 5.25V; Tamb = -40C to +125C; RBus = 60; unless otherwise specified. All voltages referenced to ground (pin 2); positive input current. No. 8 8.1 8.2 8.3 8.4 Parameters Test Conditions Pin Symbol td(TXD-BUS_ON) td(TXD-BUS_OFF) 6, 7 td_activ(TXD-RXD) td_inactiv(TXD-RXD) Min. Typ. 120 50 200 180 Max. 180 100 420 460 Unit ns ns ns ns Type* A A A A Timing Characteristics Normal Mode, VRS 0.3 x VCC (see Figure 8-1 on page 9) Delay TXD to bus active VRS = 0V Delay TXD to bus inactive Delay TXD to RXD, recessive to dominant Delay TXD to RXD, dominant to recessive Difference between Delay TXD to RXD dominant to Delay recessive Bus dominant to RXD low in Standby Mode VRS = 0V VRS = 0V VRS = 0V tdiff = td_activ(TXD-RXD) - td_inactiv(TXD-RXD)
8.5
tdiff
-280
80
ns
A
9 9.1
Timing Characteristics Standby Mode VRS 0.87 x VCC VRS = VCC 4 tdRxDL 300 450 ns A
9.2
Wake up time after Standby Mode (time TXD = 0V delay between Standby VRS from 0V to VCC to Normal Mode and to bus dominant) Standby/Normal Mode Selectable via RS (Pin 8) Input voltage for Normal VRS = VCC Mode Input current for Normal VRS = 0V Mode Input voltage for Standby Mode
6, 7
Twake_up
2
s
A
10 10.1 10.2 10.3
8 8 8
VRS IRS Vstby -700 0.87 x VCC
0.3 x VCC
V A V
A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8
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Figure 8-1. Timing Diagrams
HIGH TXD LOW Dominant CANH CANH
CANL Dominant CANL Dominant (Bus Active)
0.9V
Vdiff
0.5V
Recessive (Bus Inactive) HIGH
0.7VCC
RXD
0.3VCC
LOW t(TXD_bus_on) td(TXD_bus_off)
td_activ(TXD_RXD)
td_inactiv(TXD_RXD)
9
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Figure 8-2.
Test Circuit for Timing Characteristics
TXD GND + 5V VCC RXD
1 2 3 4
ATA6660
8 7 6 5
RS CANH CANL Vref
RL = 62 CL = 100pF
C = 47 F
C = 100 nF
C = 15 pF
Figure 8-3.
Bus Application with Split Termination Concept
Bus Line End Node CSPLIT = 10 nF
CAN Controller
TXD GND
RS CANH CANL Vref
RL = 60
RL = 60
1 2 ATA6660 3
8 7
+ 5V
VCC RXD
Bus Line Stub Node
6
C = 15 pF C = 47 F C = 100 nF
4 1
5
RL = 1.3 k
RL = 1.3 k
TXD CAN Controller + 5V GND VCC
RS CANH CANL Vref
RL = 60 RL = 60 Bus Line End Node CSPLIT = 10 nF
8 7
2 ATA6660 3
C = 15 pF
6
RXD
4
5
C = 47 F C = 100 nF
CSPLIT = 10 nF
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9. Ordering Information
Extended Type Number ATA6660-TAPY ATA6660-TAQY Package SO8 SO8 Remarks Can transceiver, Pb-free, 1k, taped and reeled Can transceiver, Pb-free, 4k, taped and reeled
10. Package Information
Package: SO 8 Dimensions in mm 4.90.1 50.2 3.70.1
0.2
0.1+0.15
1.4
0.4 1.27 3.81
3.80.1 60.2
8
5
technical drawings according to DIN specifications
1 Drawing-No.: 6.541-5031.01-4 Issue: 1; 15.08.06
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11. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, and not to this document. Revision No. 4582E-BCD-02/08 History * Put datasheet in the newest template * Section 9 "Ordering Information" on page 11 changed * Put datasheet in the newest template * Pb-free logo on page 1 deleted * Section 9 "Ordering Information" on page 11 changed * * * * Put datasheet in the newest template Pb-free logo on page 1 added Heading rows on Table "Absolute Maximum Ratings" on page 5 added Section 9 "Ordering Information" on page 11 changed
4582D-BCD-06/06
4582C-BCD-09/05
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