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SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Product List Features
SM59D04G2L25, 25MHz 16KB internal Flash MCU SM59D04G2C25, 25MHz 16KB internal Flash MCU Operating Voltage: 2.7V ~ 3.6V or 4.5V ~ 5.5V General 8052 family compatible 12 or 6 clocks per machine cycle Frequency runs up to 25MHz 16K byte on chip program Flash with In-System Programming(ISP) and EEPROM capability 768 Bytes on-chip expanded RAM with disable function 256 Bytes for standard 8052 RAM. External RAM address up to 64KB Dual 16-bit Data Pointers (DPTR0 & DPTR1) One channel serial peripheral interface (UART) Three 16 bit Timers/Counters(Timer 0 , 1, 2) Four 8-bit I/O ports for PDIP package Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package Programmable Watchdog Timer (WDT) Programmable Counter Array (PCA) for Pulse Width Modulation (PWM), capture and compare External interrupt 0, 1 with two priority level Expanded External Interrupt (EEI) interface for eight more external interrupts. ISP service program space configurable in N*512 byte (N=0 to 8) size for IAP application Direct and simple ICP programming without service program ALE output select for low EMI Clock output as the source for next MCU Power Management Unit ( IDLE and STOP mod) Code protection function Flash Memory Endurance : 100K erase and write cycles each byte at TA=25 Flash Memory Data Retention :10 years
Description
The SM59D04G2 series product is an 8-bit single chip macro-controller with 16KB Flash & 1K byte RAM embedded. It is a derivative of the 8052 micro-controller family with a fully compatible instruction sets. The 16K embedded Flash can be programmed via a commercial writer or ISP (In-System Programming) or ICP (In-Circuit Programming) function. The unused Flash can be the memory space for the EEPROM application through the ISP. After programming, the code can be protected to prevent illegal read and write. Its plentiful peripherals can make many applications easier and more efficient, such as dual DPTR, UART, WDT, Timers, PCA and EEI which are functionally compatible with most other chips. SM59D04G2 also provides power saving modes (IDLE and STOP), low EMI characteristics, etc. All of the requirements are considered to achieve the ideal MCU.
Ordering Information
yymmv SM59D04G2ihhkL yy: year, mm: month v: version identifier{ A, B,...} i: process identifier {L=2.7V~3.6V,C=4.5V~ 5.5V} hh: working clock in MHz {25} k: package type postfix {as below table} L:PB Free identifier {No text is Non-PB Free"P" is PB Free}
Postfix P J Q Package 40L PDIP 44L PLCC 44L QFP Pin / Pad Configuration Page 2 Page 3 Page 4
Contact SyncMOS : www.syncmos.com.tw 6F, No.10-2 Li- Hsin 1st Road , SBIP, Hsinchu, Taiwan 30078 TEL: 886-3-567-1820 FAX: 886-3-567-1891
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 1 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Pin Configuration
T2/P1.0 T2EX/P1.1 CCCI/P1.2 CC0/P1.3 CC1/P1.4 CC2/P1.5 CC3/P1.6 CC4/P1.7 RESET RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 2 Ver.C SM59D04G2 07/2009
SyncMOS
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
P1.1/T2EX
P1.2/CCCI
P0.0/AD0
P0.1/AD1
42
P0.2/AD2
41
6
5
4
3
2
1
44
43
40 39 38 37 36 35 34 33 32 31 30 29
CC2/P1.5 CC3/P1.6 CC4/P1.7 RESET RXD/P3.0 P4.3 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
P0.3/AD3
P1.4/CC1
P1.3/CC0
P1.0/T2
VDD
P4.2
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA P4.1 ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
17 18
16
15
14
13
12
11
10
9
8
7
19
20
21
22
23
24
25
26
27
28
A10/P2.2
A11/P2.3
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 3 Ver.C SM59D04G2 07/2009
A12/P2.4
WR/P3.6
RD/P3.7
XTAL2
XTAL1
VSS
P4.0
A8/P2.0
A9/P2.1
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P2.7/A15
25
P2.6/A14
24
33
32
31
30
29
28
27
26
AD3/P0.3 AD2/P0.2 AD1/P0.1 AD0/P0.0 VDD P4.2 T2/P1.0 T2EX/P1.1 CCCI/P1.2 CC0/P1.3 CC1/P1.4
34 35 36 37 38 39 40 41 42 43 44
23
P2.5/A13
22 21 20 19 18 17 16 15 14 13 12
PSEN
ALE
P4.1
EA
P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P4.0 VSS XTAL1 XTAL2 P3.7/RD P3.6/WR
10
RXD/P3.0
TXD/P3.1
CC2/P1.5
CC3/P1.6
CC4/P1.7
RESET
P4.3
INT0/P3.2
INT1/P3.3
T0/P3.4
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 4 Ver.C SM59D04G2 07/2009
T1/P3.5
11
1
2
3
4
5
6
7
8
9
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Block Diagram
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 5 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Pin Description
40L PDIP Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 44L QFP Pin# 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 17 28 39 6 44L PLCC Pin# 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 23 34 1 12 Symbol
P10/T2/EEI0/ICP_CLK
P11/T2EX/EEI1/ICP_TRIG
I/O i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o o o I i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o
Names
Bit 0 of port 1 & Timer 2 external input clock & EEI interrupt 0 & ICP clock input Bit 1 of port 1 & Timer 2 capture trigger & EEI interrupt 1 & ICP Trigger (active low) Bit 2 of port 1 & PCA External clock input & EEI interrupt 2 & ICP data/command IO
P12/CCCI/EEI2 /ICP_DATA P13/CC0/EEI3 P14/CC1/EEI4 P15/CC2/EEI5 P16/CC3/EEI6 P17/CC4/EEI7 RESET P30/RXD P31/TXD P32/INT0 P33/INT1 P34/T0 P35/T1 P36/WR P37/RD XTAL2 XTAL1 VSS P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 PSEN/ Clk_out ALE EA P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 VDD P40 P41 P42 P43
Bit 3 of port 1 & PCA Channel 0 & EEI interrupt 3 Bit 4 of port 1 & PCA Channel 1 & EEI interrupt 4 Bit 5 of port 1 & PCA Channel 2 & EEI interrupt 5 Bit 6 of port 1 & PCA Channel 3 & EEI interrupt 6 Bit 7 of port 1 & PCA Channel 4 & EEI interrupt 7 Hardware reset input (active high) Bit 0 of port 3 & Serial interface channel receive/transmit data
Bit 1 of port 3 & Serial interface channel transmit data or receive clock in mode 0
Bit 2 of port 3 & External interrupt 0 (low or falling-edge trigger) Bit 3 of port 3 & External interrupt 1 (low or falling-edge trigger) Bit 4 of port 3 & Timer 0 external input Bit 5 of port 3 & Timer 1 external input Bit 6 of port 3 & external memory write signal Bit 7 of port 3 & external memory read signal Crystal output or oscillator input Crystal input Ground Bit 0 of port 2 & Bit 8 of external memory address Bit 1 of port 2 & Bit 9 of external memory address Bit 2 of port 2 & Bit 10 of external memory address Bit 3 of port 2 & Bit 11 of external memory address Bit 4 of port 2 & Bit 12 of external memory address Bit 5 of port 2 & Bit 13 of external memory address Bit 6 of port 2 & Bit 14 of external memory address Bit 7 of port 2 & Bit 15 of external memory address Program storage enable (active low) & crystal/oscillator clock output as the clock source for the others Address latch enable External access with internal pull-up (active low) Bit 7 of port 0 & Bit 7 of external memory address/data Bit 6 of port 0 & Bit 6 of external memory address/data Bit 5 of port 0 & Bit 5 of external memory address/data Bit 4 of port 0 & Bit 4 of external memory address/data Bit 3 of port 0 & Bit 3 of external memory address/data Bit 2 of port 0 & Bit 2 of external memory address/data Bit 1 of port 0 & Bit 1 of external memory address/data Bit 0 of port 0 & Bit 0 of external memory address/data Power supply Bit 0 of port 4 Bit 1 of port 4 Bit 2 of port 4 Bit 3 of port 4
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 6 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Special Function Register (SFR)
Address 80h to FFh is the location of SM59D04G2 special function register (SFR). These locations must be accessed by direct addressing mode only. The following table gives the SFRs, part of them are identically located and defined as the general 8052 series: Table: SM59D04G2 SFR location 0/8 F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80
B ACC P4 PSW T2CON IP P3 IE P2 SCON P1 TCON P0
1/9
2/A
3/B
4/C
ISPFAH
5/D
KBLS ISPFAL
6/E
KBE ISPFD
7/F
KBF ISPC
T2MOD IP1
RCAP2L
RCAP2H
TL2
TH2 SCONF RCON
IE1 PCAC1 SBUF CC2DH TMOD SP
PCAC2 PCACH CC2DL TL0 DPL
CC0CON
CC1CON
CC2CON
CC3CON
CC4CON
PCACL CC3DH TL1 DPH
CC0DH CC3DL TH0 DPL1
CC0DL CC4DH TH1 DPH1
CC1DH CC4DL WDTC DPS
CC1DL WDTK PCON
FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
Here is the simple description and initial value of the above SFR. A detailed explanation is given in later sections. TableSFR description and initial value Register Location Initial value Description P0 80h FFh Port 0 SP 81h 07h Stack Pointer DPL 82h 00h Data Pointer Low byte DPH 83h 00h Data Pointer High byte DPL1 84h 00h Data Pointer 1 Low byte DPH1 85h 00h Data Pointer 1 High byte DPS 86h 00h Data Pointer select PCON 87h 00h Power control register TCON 88h 00h Timer control register TMOD 89h 00h Timer Mode TL0 8Ah 00h Timer 0 low byte TL1 8Bh 00h Timer 1 low byte
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 7 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Register TH0 TH1 WDTC WDTK P1 CC2DH CC2DL CC3DH CC3DL CC4DH CC4DL SCON SBUF PCACH PCACL CC0DH CC0DL CC1DH CC1DL P2 PCAC1 PCAC2 CC0CON CC1CON CC2CON CC3CON CC4CON IE IE1 P3 IP IP1 SCONF T2CON T2MOD RCAP2L RCAP2H TL2
Location 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h B0h B8h B9h BFh C8h C9h CAh CBh CCh
Initial value 00h 00h 00h 00h FFh 00h 00h 00h 00h 00h 00h 00h XXh 00h 00h 00h 00h 00h 00h FFh 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh 00h 00h 00h C0h 00h 00h 00h FFh
Description Timer 0 high byte Timer 1 high byte Watchdog timer control register Watchdog timer refresh key Port 1 Compare/Capture channel 2 data high byte Compare/Capture channel 2 data low byte Compare/Capture channel 3 data high byte Compare/Capture channel 3 data low byte Compare/Capture channel 4 data high byte Compare/Capture channel 4 data low byte Serial port channel (UART) control register Serial port channel (UART) data buffer PCA counter high byte PCA counter low byte Compare/Capture channel 0 data high byte Compare/Capture channel 0 data low byte Compare/Capture channel 1 data high byte Compare/Capture channel 1 data low byte Port 2 PCA control register 1 PCA control register 2 Compare/Capture channel 0 control register Compare/Capture channel 1 control register Compare/Capture channel 2 control register Compare/Capture channel 3 control register Compare/Capture channel 4 control register Interrupt Enable Interrupt Enable 1 register Port 3 Interrupt Priority Interrupt Priority 1 register System control flag Timer 2 control register Timer 2 mode Reload/Capture data low byte Reload/Capture data high byte Timer 2 low byte
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 8 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Register TH2 PSW P4 ACC B ISPFAH ISPFAL ISPFD ISPC KBLS KBE KBF
Location CDh D0h D8h E0h F0h F4h F5h F6h F7h FDh FEh FFh
Initial value FFh 00h xFh 00h 00h 00h 00h 00h 00h 00h 00h 00h
Description Timer 2 high byte Program Status Word register Port 4 Accumulator B register ISP address high byte ISP address low byte ISP data register ISP control register EEI Level Selector Register EEI input Enable Register EEI Flag register
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 9 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Function Description
1 General Features
SM59D04G2 is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the following sections. 1.1 Embedded Flash
The program can be loaded into the embedded 16KB Flash memory via its writer or ISP (In-System Programming) or ICP (In-Circuit Programming) function. The high-quality Flash is suitable for re-programming and data recording as EEPROM. 1.2 IO Pads
The IO pads are compatible to the 8052 series. P0 is open-drain in the input or output high condition, so the external pull-up resistor is required. P1 ~ P4 are designed with internal pull-up resistors. The IO pad structure is given below:
Fig. 1-1IO pad structure All the pads for P0 ~ P4 are with slew rate to reduce EMI. The other way to reduce EMI is to disable the ALE output if unused. This is selected by its SFR. In 3.3V applications, the IO pads are 5V tolerant except for XATL1 and XTAL2.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 10 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
1.3
12T/6T Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per one machine cycle. If the machine cycle is changed to 6 clocks, then this 6T mode will double the running speed of 12T's with the same oscillator source. 12T or 6T is configured in the information block. The figures given below are an example to show the difference of 12T mode and 6T mode.
Fig 1-2(a)The signal waveform of external program (EA=0) in 12T mode
Fig 1-2(b)The signal waveform of external program (EA=0) in 6T mode Since the execution speed in 6T is two times of that in 12T, in order for the easy explanation in the later sections, here we define the terminology "system clock" or "system frequency" as System clock frequency(FOSC) = crystal(FCRY) or oscillator frequency in 6T, and System clock frequency(FOSC)= crystal(FCRY) or oscillator frequency divided by 2 in 12T Take a 16MHz oscillator as an example, the system clock frequency is 16MHz in 6T. But in 12T mode, the system clock frequency is 8MHz.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 11 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
2
Instruction set
The SM59D04G2 uses the powerful 80C51 instruction set. It consists of 49 single-byte, 42 two-byte and 15 three-byte instructions. Among them, 63 instructions are executed in 1 machine-cycle, 46 instructions in 2 machine-cycles and 2 instructions in 4 machine-cycles. A summary of the instruction set is given in Table 2-1. All of the instructions are fully compatible with standard 8052-series'. Table 2.1 Instruction set
Mnemonic Arithmetic Instructions ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV A, @Ri A, #data A, Rn A, direct A, @Ri A, #data A Rn direct @Ri A Rn direct @Ri DPTR AB AB OPERATION A = A + Rn A = A + direct A = A + <@Ri> A = A + #data A = A + Rn + C A = A + direct + C A = A + @Ri + C A = A + #data + C A = A Rn C A = A direct C A = A <@Ri> C A = A#data C A=A+1 Rn = Rn + 1 direct = direct + 1 <@Ri> = <@Ri> + 1 A=A 1 Rn = Rn 1 direct = direct 1 <@Ri> = <@Ri> 1 DPTR = DPTR 1 B:A = A x B A = INT (A/B) B = MOD (A/B) Decimal adjust ACC A .AND. Rn A .AND. direct A .AND. <@Ri> A .AND. #data direct .AND. A direct .AND. #data A .OR. Rn A .OR. direct A .OR. <@Ri> A .OR. #data direct .OR. A direct .OR. #data A .XOR. Rn A .XOR. direct A .XOR. <@Ri> A .XOR. #data direct .XOR. A direct .XOR. #data A=0 A = /A Rotate ACC Left 1 bit Rotate Left through Carry Rotate ACC Right 1 bit Rotate Right through Carry Swap Nibbles in A BYTE 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 CYCLE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
DA A Logical Instructions ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 12 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Data Transfers Instructions MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A,Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Boolean Instructions CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel Jump Instructions ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct,rel CJNZ A, #data,rel CJNZ Rn, #data,rel CJNZ @Ri, #data,rel DJNZ Rn, rel DJNZ direct, rel NOP
A = Rn A = direct A = <@Ri> A = #data Rn = A Rn = direct Rn = #data direct = A direct = Rn direct = direct direct = <@Ri> direct = #data <@Ri> = A <@Ri> = direct <@Ri> = #data DPTR = #data16 A = code memory[A+DPTR] A = code memory[A+PC] A = external memory[Ri] (8-bits address) A = external memory[DPTR] (16-bits address) external memory[Ri] = A (8-bits address) external memory[DPTR] = A (16-bits address) INC SP: MOV "@'SP', < direct > MOV < direct >, "@SP": DEC SP ACC and < Rn > exchange data ACC and < direct > exchange data ACC and < Ri > exchange data ACC and @Ri exchange low nibbles C=0 bit = 0 C=1 bit = 1 C = /C bit = /bit C = C .AND. bit C = C .AND. /bit C = C .OR. bit C = C .OR. /bit C = bit bit = C Jump if C= 1 Jump if C= 0 Jump if bit = 1 Jump if bit = 0 Jump if C = 1 Call Subroutine only at 2k bytes Address Call Subroutine in max 64K bytes Address Return from subroutine Return from interrupt Jump only at 2k bytes Address Jump to max 64K bytes Address Jump on at 256 bytes Jump to A+ DPTR Jump if A = 0 Jump if A 0 Jump if A < direct > Jump if A < #data > Jump if Rn < #data > Jump if @Ri < #data > Decrement and jump if Rn not zero Decrement and jump if direct not zero No Operation
1 2 1 2 1 2 2 2 2 3 2 2 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1
1 1 1 1 1 2 1 1 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 13 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
3
Memory Structure
The SM59D04G2 manipulates operands in three memory spaces. They are (1) 256 bytes standard RAM, (2) 768 bytes auxiliary RAMand (3) 16K bytes embedded Flash as program memory. 3.1 Program Memory
As described in Section 1, the SM59D04G2 has 16K bytes on-chip Flash memory which is used as general program memory, the address range for the 16K bytes is 0000h to 3FFFh. If the program code is less than 16K bytes, the remaining part can be used as EEPROM to store data. The procedure of this EEPROM application function is described in the section on ISP.
The feature of FLASH memory is shown as following: READ: byte-wise WRITE: byte-wise within 30us (previously erased by a chip erase).
ERASE:
Full Erase (16K bytes) within 200 ms. Erased bytes contain FFH Endurance : 100K erase and write cycles each byte at TA=25 Retention : 10 years
If we do ISP or IAP, there are up to 4K bytes of specific ISP service program. The address range is 3000h to 3FFFh. The ISP service program size can be partitioned as N blocks of 512 bytes (N=0 to 8). When N=0, there will be no ISP service program space available, the total 16K bytes memory are used as program memory. When N=1, the Flash from 3E00h to 3FFFh is reserved for ISP service program. When N=2, the Flash from 3C00h to 3FFFh is reserved for ISP service program... Value N is set in the information block. Fig 3.1 shows the ISP Flash reservation with different values of N.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 14 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
3FFF 3E00 ISP service program space, up to 4KB 3C00 3A00 3800 3600 3400 3200 3000 16KB program memory space
N=8 N=7 N=6 N=0 N=1
SM56D04G2
0000
Fig 3-1Flash segmentation for ISP The SM59D04G2 provides code protect function on the writer. The user can select protect or unprotect by writer. If protection is selected, users can't read the program from the writer. When the user runs in the external program mode (EA = 0) and protect bit is set and the MOVC instruction will be disable by hardware. The only way to change the protection bit back is to erase the entire Flash. 3.2 Data Memory
The SM59D04G2 has 256 + 768 bytes on-chip RAM, the 256 bytes are the same as general 8052 internal memory structure while the expanded 768 bytes on-chip RAM can be accessed by external memory addressing method( by instruction MOVX).
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 15 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Fig. 3-2 : RAM architecture 3.2.1 Data Memory - Lower 128 byte ($00h to $7Fh)
Data Memory 00h to FFh is the same as defined in 8052. The address 00h to 7Fh can be accessed by both direct and indirect addressing modes. Address 00h to 1Fh is register area. Address 20h to 2Fh is memory bit area, and address 30h to 7Fh is for general memory area. 3.2.2 3.2.2 Data Memory - Higher 128 byte ($80h to $FFh)
The address 80h to FFh can only be accessed by indirect addressing mode. It is data area. 3.2.3 3.2.3 Data Memory - Expanded 768 bytes ($0000h to $02FFh)
Address 0000h to 02FFh is the on-chip expanded RAM area, totally 768 bytes. This area can be accessed by external direct addressing mode with instruction MOVX. If the address of instruction MOVX @DPTR is larger than 02FFh, then the SM59D04G2 will generate the external memory control signal automatically. The bit 1 (OME) of SFR BFh (SCONF) can enable or disable this expanded 768 byte RAM. The default setting of OME bit is 0 (disable).
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 16 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
4
CPU Engine
The SM59D04G2 CPU engine allows fetching instructions from the program memory, and accessing data with RAM or SFR. Here the SFR in the CPU engine is explained.
Mnemonic Description
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
ACC B PSW SP DPL DPH DPL1 DPH1 DPS SCONF
Accumulator B register Program status word Stack Pointer Data pointer low 0 Data pointer high 0 Data pointer low 1 Data pointer high 1 Data pointer select System control flag
E0h F0h D0h 81h 82h 83h 84h 85h 86h BFh
ACC.7 B.7 CY
8051 Core ACC.6 ACC.5 B.6 B.5 AC F0
ACC.4 B.4
ACC.3 B.3
ACC.2 B.2 OV
ACC.1 B.1 F1
ACC.0 B.0 P
00h 00h 00h 07h 00h 00h 00h 00h
RS[1:0] SP[7:0] DPL[7:0] DPH[7:0] DPL1[7:0] DPH1[7:0]
-
-
-
-
-
ISPE
OME
DPS.0 ALEI 00h
4.1
Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to hold the operand. Mnemonic: ACC
7 ACC.7 6 ACC.6 5 ACC.5 4 ACC.4 3 ACC.3 2 ACC.2 1 ACC.1
Address: E0h
0 ACC.0 Reset 00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator. 4.2 B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to hold temporary data. Mnemonic: B
7 B.7 6 B.6 5 B.5 4 B.4 3 B.3 2 B.2 1 B.1
Address: F0h
0 B.0 Reset 00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator. 4.3 Program Status Word Mnemonic: PSW
7 CY 6 AC 5 F0 4 RS[1:0] 3 2 OV 1 F1
Address: D0h
0 P Reset 00h
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 17 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
CY: Carry flag. AC: Auxiliary Carry flag for BCD operations. F0: General purpose Flag 0 available for user. RS[1:0]: Register bank select, used to select working register bank. RS[1:0] Bank Location Selected 00 Bank 0 00h - 07h 01 Bank 1 08h - 0Fh 10 Bank 2 10h - 17h 11 Bank 3 18h - 1Fh OV: Overflow flag. F1: General purpose Flag 1 available for user. P: Parity flag, affected by hardware to indicate odd/even number of "one" bits in the Accumulator, i.e. even parity. 4.4 Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 08h. Mnemonic: SP
7 6 5 4 SP[7:0] 3 2 1
Address: 81h
0 Reset 07h
SP[7:0]: The Stack Pointer stores the Scratchpad RAM address where the stack begins. In other words, it always points to the top of the stack. 4.5 Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as 2 byte register (MOV DPTR, #data16) or as two registers (ea. MOV DPL, #data8). It is generally used to access external code or data space (ea. MOVC A, @A+DPTR or MOV A, @DPTR respectively). Mnemonic: DPL
7 6 5 4 3 DPL[7:0] 2 1
Address: 82h
0 Reset 00h
DPL[7:0]: Data pointer Low 0 Mnemonic: DPH
7 6 5 4 3 DPH[7:0] 2 1
Address: 83h
0 Reset 00h
DPH[7:0]: Data pointer High 0
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 18 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
4.6
Data Pointer 1
The dual data pointer accelerates the moving of block data. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the SM59D04G2, the standard data pointer is called DPTRthe second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located in the LSB of DPS register (DPS.0). The user switches between pointers by toggling the LSB of DPS register. All DPTR-related instructions use the currently selected DPTR for any activity. Mnemonic: DPL1
7 6 5 4 3 DPL1[7:0] 2 1
Address: 84h
0 Reset 00h
DPL1[7:0]: Data pointer Low 1 Mnemonic: DPH1
7 6 5 4 3 DPH1[7:0] 2 1
Address: 85h
0 Reset 00h
DPH1[7:0]: Data pointer High 1 Mnemonic: DPS
7 6 5 4 3 2 1 -
Address: 86h
0 DPS.0 Reset 00h
DPS.0: Data Pointer select register. DPS.0 = 1 is selected DPTR1.
4.7
System control flag Mnemonic: SCONF
7 6 5 4 3 2 ISPE 1 OME
Address: BFh
0 ALEI Reset 00h
ISPE: ISP function enable bit. ISPE = 1 is enable ISP function. ISPE = 0 is disable ISP function. OME: 768 bytes on-chip RAM enable bit. OME = 1 is enable 768 bytes on-chip RAM. OME = 0 is disable 768 bytes on-chip RAM. ALEI: ALE output disable. ALEI = 1 is disable ALE output. ALEI = 0 is Enable ALE output.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 19 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
5
Port 0 - Port 4
Port 0 ~ Port 4 are the general purpose IO of this controller. Port 4[3:0] is available with 44-pin PLCC or QFP package only, not for 40-pin package. Most of the ports are multiplexed with the other outputs, e.g., Port 3[0] is also used as RXD in the UART application. Port0 is open-drain in the input and output high condition, so external pull-up resistors are required. As for the other ports, the pull-up resistors are built internally. For general purpose applications, every pin can be assigned to either high or low independently because their SFRs are bit addressable as given below Mnemonic: P0
7 P0.7 6 P0.6 5 P0.5 4 P0.4 3 P0.3 2 P0.2 1 P0.1
Address: 80h
0 P0.0 Reset FFh
P0.7~ 0: Port0[7] ~ Port0[0] Mnemonic: P1
7 P1.7 6 P1.6 5 P1.5 4 P1.4 3 P1.3 2 P1.2 1 P1.1
Address: 90h
0 P1.0 Reset FFh
P1.7~ 0: Port1[7] ~ Port1[0] Mnemonic: P20
7 P2.7 6 P2.6 5 P2.5 4 P2.4 3 P2.3 2 P2.2 1 P2.1
Address: A0h
0 P2.0 Reset FFh
P2.7~ 0: Port2[7] ~ Port2[0] Mnemonic: P3
7 P3.7 6 P3.6 5 P3.5 4 P3.4 3 P3.3 2 P3.2 1 P3.1
Address: B0h
0 P3.0 Reset FFh
P3.7~ 0: Port3[7] ~ Port3[0] Mnemonic: P4
7 x 6 x 5 x 4 x 3 P4.3 2 P4.2 1 P4.1
Address: D8h
0 P4.0 Reset xFh
P4.3~ 0: Port4[3] ~ Port4[0]
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 20 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
6
Timer 0 and Timer 1
These timer and counter functions are presented in the same module. The "timer" or "counter" function is selected by the control bits C/ T in SFR TMOD. Timer 0 and Timer 1 have four operation modes, which are selected by bit-pairs (M1, M0) in SFR TMOD. Mode 0, 1, and 2 are the same for both timer and counters. Mode 3 is different. The four operating modes are described below 6.1 Mode 0
In this mode, the timer register is configured as a 13-bit register. Take Timer 1 as the example, as the counter rolls over from all 1s to all 0s, it sets the Timer 1 interrupt flag TF1. The counter input is enabled by the timer when TR1 = 1 and either GATE = 0 or INT 1 = 1, here setting GATE = 1 allows the timer to be controlled by external input INT 1 , to facilitate pulse width measurements. TR1 is a control bit in the SFR TCON and GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers. Mode 0 operation is the same for Timer 0 and Timer 1. So substituting TR0, TF0 and INT 0 for the corresponding Timer 1 signals in the last paragraph, we can know the operation of Mode 0 for Timer 0. But there are two different GATE bits, one is for Timer 1(TMOD.7) and the other one is for Timer 0 (TMOD.3).
OSC /12
C/ T = 0 TL1 (5 bits) C/ T = 1 T1 pin Control TH1 (8 bits) TF1 Interrupt
TR1
GATE
INT 1 pin
Fig. 6-1 Mode 0 operation for Timer 1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 21 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
6.2
Mode 1
Mode 1 is the same as Mode 0, except that the timer register runs with all 16 bits.
T
T
INT1
Fig. 6-2 Mode 1 operation for Timer 1
6.3
Mode 2
For Timer 1, Mode 2 configures the timer register as an 8-bit counter (TL1) with automatic reload. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload operation leaves TH1 unchanged. Timer 0 Mode 2 operation is also the same.
T
T
INT1
Fig. 6-3 Mode 2 operation for Timer 1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 22 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
6.4
Mode 3
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 takes TL0 and TH0 as two separate counters. TL0 uses the Timer 0 control bits: C/T , GATE, TR0, INT 0 , and TF0. TH0 is locked into a timer function to count machine cycles and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the "Timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.
OSC /12
C/ T = 0 TL0 (8 bits) C/ T = 1 T0 pin Control TF0 Interrupt
TR0
GATE INT 0 pin
TH0 (8 bits) Control TR1
TF1
Interrupt
Fig. 6-4 Mode 3 operation for Timer 0
6.5
SFR description
Description Timer 0 , low byte Timer 0 , high byte Timer 1 , low byte Timer 1 , high byte Timer Mode Control Timer/Counter Control
Direct
Mnemonic
Bit 7
TL0 TH0 TL1 TH1 TMOD TCON
8Ah 8Ch 8Bh 8Dh 89h 88h GATE TF1
Bit 6 Bit 5 Bit 4 Bit 3 Timer 0 and 1 TL0[7:0] TH0[7:0] TL1[7:0] TH1[7:0] C/ T TR1 M1 TF0 M0 TR0 GATE IE1
Bit 2
Bit 1
Bit 0
RESET
00h 00h 00h 00h C/ T IT1 M1 IE0 M0 IT0 00h 00h
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 23 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
6.5.1
Timer/Counter Mode Control register (TMOD) Mnemonic: TMOD
7 GATE 5 M1 C/ T Timer 1 6 4 M0 3 GATE 2 C/ T Timer 0 1 M1
Address: 89h
0 M0 Reset 00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1, respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on T0 or T1 input pin C/ T : Selects Timer or Counter operation. When set to 1, a Counter operation is performed, when cleared to 0, the corresponding register will function as a Timer. M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1. M1 M0 Mode Function 0 0 Mode0 13-bit Counter/Timer, with 5 lower bits in TL0 or TL1 register and 8 bits in TH0 or TH1 register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are hold at zero. 0 1 Mode1 16-bit Counter/Timer. 1 0 Mode2 8 -bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TLx overflows, a value from THx is copied to TLx. 1 1 Mode3 If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent 8 bit Timers / Counters.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 24 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
6.5.2
Timer/Counter Control register (TCON) Mnemonic: TCON
7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0
Address: 88h
0 IT0 Reset 00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when interrupt is processed. TR1: Timer 1 Run control bit. If cleared, Timer 1 stops. TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be cleared by software and is automatically cleared when interrupt is processed. TR0: Timer 0 Run control bit. If cleared, Timer 0 stops. IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1 is observed. Cleared when interrupt is processed. IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to cause interrupt. IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0 is observed. Cleared when interrupt is processed. IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to cause interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 25 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
7
Timer 2
Timer 2 is a 16-bit timer/counter which can operate either as a timer or an event counter. This is selectable by bit C/ T 2 in the SFR T2CON. It has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON as shown below. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the timer function, the TL2 register is incremented every machine cycle, thus one can think of it as counting machine cycles. Since a machine cycle consists of a 12-clock period in 12T, the count rate is 1/12 of the oscillator clock frequency. In 6T, it is 1/6. In the counter function, the register is incremented in response to every 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes 2 machine cycles (24 clock periods in 12T) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency in 12T mode or 1/12 in 6T mode. To ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. Table 7-1 : Timer 2 Operating Modes TR2 MODE CP/ RL2 0 1 16-bit Auto-reload 1 1 16-bit Capture X 1 Baud rate Generator X 0 Off
RCLK+TCLK 0 0 1 X
7.1 Capture mode In the capture mode, there are two options selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 26 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Figure 7-1 Timer 2 in capture mode
7.2
Auto-reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by a bit named DCEN (Down Counter Enable) located in the SFR T2MOD. Upon reset, the DCEN bit is set to 0 so that Timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 7-2 shows Timer 2 automatically counting up when DCEN = 0. In this mode there are two options selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to FFFFh and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in RCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 7-3. In this mode the T2EX pin controls the direction of count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at FFFFh and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. Now the timer underflows when TH2 and TL2 are equal to the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows. This bit can be used as a 17th bit of resolution if desired. In this operating mode, EXF2 does not flag an interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 27 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Figure 7-2Timer 2 in auto reload mode (DCEN=0)
Figure 7-3 Timer 2 in auto reload mode (DCEN=1) 7.3 Programmable clock out
A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides begin a regular I/O pin, has two alternate functions. It can be programmed (1) to input the external clock for Timer/Counter 2 or (2) to output a 50% duty cycle clock. An example is that the clock output ranges from 61Hz to 4MHz at a 16MHz oscillator frequency if in 12T mode. To configure the Timer/Counter 2 as a clock generator, bit C/ T 2 (T2CON.1) must be cleared and bit T2OE(T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation:
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 28 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Clock-Out Frequency =
Oscillator Frequency 4 x (65536 - RCAP 2 H , RCAP 2 L)
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies can not be determined independently from one another since they both use RCAP2H and RCAP2L.
Figure 7-4 Timer 2 in clock-out mode 7.4 SFR description
Description Timer 2 , low byte Timer 2 , high byte Reload and capture data low byte Reload and capture data high byte Timer 2 mode Timer 2 control register
Direct
Mnemonic
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RES ET
Timer 0 and 1 TL2 TH2 RCAP2L RCAP2H T2MOD T2CON CCh CDh CAh CBh C9h C8h TF2 EXF2 RCLK TL2[7:0] TH2[7:0] RCAP2L[7:0] RCAP2H[7:0] TCLK EXEN2
00h 00h 00h 00h TR2 T2OE DCEN CP/ x0h 00h
C/ T2
RL2
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 29 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Mnemonic: T2CON
7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/ T2
Address: C8h
0
CP/ RL2
Reset 00h
TF2: Timer 2 overflow flag is set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. EXF2: Timer 2 external flag is set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). RCLK: Receive clock enable. When set, causes the serial port to use Timer 2 overflow pluses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock. TCLK: Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for it's transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2: Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2: Start/Stop control for Timer 2. TR2 = 1 starts the timer. C/ T2 : Timer or counter select for Timer 2. C/ T2 = 0 for timer function. C/ T2 = 1 for external event counter (falling edge triggered). CP/ RL2 : Capture/Reload select. CP/ RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/ RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Mnemonic: T2MOD
7 6 5 4 3 2 1 T2OE
Address: C9h
0 DCEN Reset x0h
T2OE: Timer 2 Output Enable bit. DCEN: When set, this bit allows Timer 2 to be configured as an up/down counter.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 30 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
8
Watchdog timer
The watchdog timer is an 8-bit counter that is incremented once every WDTCLK clock cycle. After an external reset, the watchdog timer is disabled and all registers are set to zero. When SM59D04G2 is reset, it will read internal setting for the bit WDTEN.When the WDTEN is selected ,the watchdog function will enable. The WDTM[2:0] is control WDTCLK. User can select WDTEN on the writer. Table 8-1 Watchdog Timer Overflow Period
WDTM[2:0] Overflow Period 000 1.58ms 001 3.15ms 010 6.30ms 011 12.60ms 100 25.12ms 101 110 111
50.41ms 100.82ms 201.65ms
The watchdog timer will reset the system after 256 WDTCLK is reached. Once the watchdog is started it cannot be stopped. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM59D04G2 been reset, either hardware reset or WDT reset To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning. The SFR WDTK[7:0] must be set first. The first value set to it is 1Eh, then the next value is E1h.
Mnemonic WDTC WDTK Description Watchdog timer control register Watchdog timer refresh key
Direct
Bit 7 WDTE
Bit 6 Bit 5 Bit 4 Watchdog Timer CLEAR
Bit 3 -
Bit 2
WDTM2
Bit 1
WDTM1
Bit 0
WDTM0
RESET
8Eh 8Fh
-
00H 00H
WDTK[7:0]
Mnemonic: WDTC
7 WDTE 6 5
CLEAR
Address: 8Eh
4 3 2
WDTM2
1
WDTM1
0
WDTM0
Reset 00H
WDTM[2:0]: WDTE:
CLEAR
Watchdog timer over flow period setting. Watchdog timer Enable. WDTE=0Disable WDT function either the WDTEN was setting on the Writer WDTE=1Enable WDT function when the WDTEN was setting on the Writer This bit will be cleared to 0 automatically when MCU been reset, either hardware reset or WDT reset Setting this bit the Watchdog timer counter clear and re-start to count from the Beginning
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 31 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Mnemonic: WDTK
7 6 5 4 3 2 1
Address: 8Fh
0
WDTK[7:0]
Reset 00h
WDTK: Watchdog timer refresh key. A programmer must set it to 1Eh first, then E1h next. After these, the above SFR WDTC can be set.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 32 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
9
ISP (In-System Programming)
The SM59D04G2 can perform ISP or In-Application Programming (IAP) function by putting the ISP service code into the assigned ISP code area as shown in Table 9-1. One page of Flash memory is 512bytes. Table 9-1 ISP code area SM59D04G2 Lock-bit number ISP code area 1 512 bytes (from $3E00h to $3FFF) 2 1K bytes (from $3C00h to $3FFF) 3 1.5K bytes (from $3A00h to $3FFF) 4 2K bytes (from $3800h to $3FFF) 5 2.5K bytes (from $3600h to $3FFF) 6 3K bytes (from $3400h to $3FFF) 7 3.5K bytes (from $3200h to $3FFF) 8 4K bytes (from $3000h to $3FFF) There are three ways to enter the ISP code area. They are (1) Blank first dataIf the first Flash data is blank (data in address 0000h is FFh), the controller will read it after power on and after identifying it as blank, the program counter will go to the ISP code area. (2) Execute the "LJMP" instruction in the program as IAP function. (3) By hardware setting: After power on reset, if the hardware finds both Port2[6] and Port2[7] are tied low, or Port4[3] is low, then the program counter will go to the ISP code area. This is shown in Fig. 9-1.
Fig 9-1ISP entering by hardware setting
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 33 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
9.1
SFR description
Description ISP control register ISP Flash address high byte ISP Flash address low byte ISP Flash data
Direct
Mnemonic
Bit 7
START
Bit 6 -
Bit 5 ISP -
Bit 4
-
Bit 3 -
Bit 2 -
Bit 1 ISPF1
Bit 0 ISPF0
RESET
ISPC ISPFAH ISPFAL ISPFD
F7h F4h F5h F6h
00h 00h 00h 00h
ISPFA[15:8] ISPFA[7:0] ISPFD[7:0]
Mnemonic: ISPFAH
7 6 5 4 3 ISPFA[15:8] 2 1
Address: F4h
0 Reset 00h
Mnemonic: ISPFAL
7 6 5 4 3 ISPFA[7:0] 2 1
Address: F5h
0 Reset 00h
ISPFA[15:0]: The ISPFAH and ISPFAL provide the 16-bit Flash memory address for the ISP function. The Flash memory address should not include the ISP service program space address. If the Flash memory address indicated by ISPFAH and ISPFAL registers overlaps with the ISP service program space, the Flash write and page erase function will have no effect. Mnemonic: ISPFD
7 6 5 4 3 ISPFD[7:0] 2 1
Address: F6h
0 Reset 00h
ISPFD[7:0]: The ISPFD provide the 8-bits data for ISP function. Mnemonic: ISPC
7
START
Address: F7h
5 4 3 2 1 0 ISPF[1:0] Reset 00h
6 -
ISPF[1:0]: ISP function select. ISPF[1:0] ISP function 00 Byte program 01 Chip Protect 10 Page erase( 512 Bytes) 11 Chip erase START: ISP START bit. START = 1 : Start ISP function which indicated by ISPF[1:0]. START = 0 : no operation. The START bit is read-only by default, software must write three specific values 55h, AAh and 55h sequentially to the ISPFD register to enable the START bit write attribute. That is:
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 34 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Ex: Open ISP function: MOV ISPFD,#055h MOV ISPFD,#0AAh MOV ISPFD,#055h Any attempt to set START bit will not be allowed without procedure above. After the START bit set to 1, the SM59D04G2 hardware circuit will latch the address and data bus and hold the program counter until the START bit resets to 0 when the ISP function finished. The user does not need to check the START bit status by software method. To perform byte program or page erase ISP function, the user needs to first specify the Flash address. When performing the page erase function, the SM59D04G2 will erase the entire page indicated by the Flash address in the ISPFAH register located within the page. To perform chip erase ISP function, the SM59D04G2 will erase all the Flash program memory and data Flash memory except the ISP program space. Also, the SM59D04G2 will unprotect the Flash memory automatically if it has been protected by setting the information block bit LOCK=0. If LOCK is 0, all the Flash memory will be read all zeros. The following example is to show how the ISP service program does byte program - to program data of #22h to the address of the $1005h MOV ISPFD, #055h MOV ISPFD, #0AAh MOV ISPFD, #055h MOV SCONF, #04h MOV ISPFAH, #10h MOV ISPFAL, #05h MOV ISPFD, #22h MOV ISPFC, #80h
; Open ISP function ; enable ISP function ; Set Flash address high byte ; Set Flash address low byte ; Set Flash data to be programmed ; Start to program data of 22h to the Flash address of the $1005h ; After byte program finished, START bit of ISPC will reset to 0 automatically ; and program counter then point to the next instruction.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 35 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
10 Serial interface (UART) The UART serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. (However, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port's receive and transmit registers are both accessed through SFR SBUF. Actually, SBUF is composed of two separate registers, a transmit buffer and a receive buffer. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port control and status register are in the SFR SCON. This register contains the mode selection bits (SM0 and SM1), the SM2 bit for the multiprocessor modes (please see Subsection 10.1), the Receive Enable (REN); the 9th data bit for transmit and receive (TB8 and RB8); and the serial port interrupt bits (TI and RI). The serial port can operate in the following 4 modes: Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received with LSB first. The baud rate is fixed at 1/6 the system frequency as defined in Section 1. Mode 1: 10 bits are transmitted (through TXD) or received (through RXD) with a start bit (=0), then the 8 data bits with LSB first, finally a stop bit (=1). On the receiving side, the stop bit goes into RB8 in SFR SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (through TXD) or received (through RXD) with a start bit (=0), then the 8 data bits with LSB first, then a programmable 9th data bit, finally a stop bit (=1). On the transmitting side, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1, or, for example, the parity bit (P in the PSW) could be moved into TB8. On the receiving side , the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/16 of the system frequency. Mode 3: 11 bits are transmitted (through TXD) or received (through RXD) with a start bit (=0), then the 8 data bits with LSB first, then a programmable 9th data bit, finally a stop bit (=1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. 10.1 Multiprocessor Communications Mode 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. This feature is used in multiprocessor systems as follows.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 36 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slave that weren't being addressed leave their SM2s set and go on their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 10.2 Baud rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate =
System Frequency 6
The baud rate in mode 2 depends on the value of bit SMOD in SFR PCON. If SMOD = 0 (which is the value on reset), the baud rate is 1/32 the system frequency. If SMOD = 1, the baud rate is 1/16 the system frequency. Mode 2
2 SMOD x (System Frequency) Baud Rate = 32
10.3 Using Timer 1 to Generate Baud Rates. When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Modes 1 and 3
2 SMOD x (Timer 1 overflow rate) Baud Rate = 32
The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either "timer" or "counter" operation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case, the baud rate is given by the formula Modes 1 and 3
2 SMOD System Frequency x Baud Rate = 32 6 x [256 - TH 1]
One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 37 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
10.4 Using Timer 2 to Generate Baud Rates. In the SM59D04G2, Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note then the baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. Now, the baud rates in Modes1 and 3 are determined by Timer 2's overflow rate as follows: Modes 1, 3 Baud Rate =
Timer 2 overflow rate 16
The timer can be configured for either "timer" or "counter" operation. In the most typical applications, it is configured for "timer" operation (C/T2 = 0). "Timer" operation is a little different for Timer 2 when it's being used as a baud rate generator. Normally, as a timer, it would increment every machine cycle (thus at 12 oscillator cycles in 12T, or 6 cycles in 6T). As a baud rate generator however, it increments in every system frequency. In that case, the baud rate is given by the formula Modes 1, 3 Baud Rate =
System Frequency 16 x [65536 - (RCAP2H, RCAP2L)]
Where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 10-1. This Figure is valid only if RCLK + TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Therefore, a Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Please also note that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt, if desired. We should keep mind that when Timer 2 is running (TR2 = 1) in "timer" function in the baud rate generator mode, one should not try to read or write TH2 or TL2. Under these conditions the timer is being incremented every state time, and the results of a read or write may not be accurate. The RCAP registers may be read, but shouldn't be written to, because a write might overlap a reload and cause write and/or reload errors. In this case, turn the timer off (clear TR2) before accessing the Timer 2 or RCAP registers.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 38 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Figure 10-1 Timer 2 in Baud Rate Generator Mode
10.5 SFR description
Mnemonic
Description Power Control Serial port 0 control register Serila port 0 data buffer
Direct
Bit 7 SMOD SM0
PCON SCON SBUF
87h 98h 99h
Bit 6 Bit 5 Serial port SM1 SM2
Bit 4 REN
Bit 3 GF1 TB8
Bit 2 GF0 RB8
Bit 1 PD TI
Bit 0 IDLE RI
RESET
00h 00h XXh
SBUF[7:0]
Mnemonic: PCON
7 SMOD 6
-
Address: 87h
4 3 GF1 2 GF0 1 PD 0 IDLE Reset 00h
5 -
SMOD: This bit set to "1" to make the UART 0 baud-rate double. Mnemonic: SCON
7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI
Address: 98h
0 RI Reset 00h
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 39 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
SM0,SM1 SM0, SM1 specify the serial port mode as follows (Fosc is the system frequency) : SM0 SM1 Mode Description Baud Rate 0 0 0 Shift register Fosc /6 0 1 1 8-bit UART variable 1 0 2 9-bit UART Fosc /16 or Fosc/32 1 1 3 9-bit UART variable SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 TB8 is the 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In Modes 2 and 3, it is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. TI TI is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. It must be cleared by software. RI RI is the receive interrupt flag.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 40 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
11 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. The PCA consists of a dedicated counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any one of the following signals: - Fosc - Fosc/4 - Fosc/12 - External clock input (CCCI pin, i.e., Port1[2]) where Fosc is the system Frequency defined in Section 1. Each compare/capture module can be programmed in any one of the following modes: - Positive edge capture mode - Negative edge capture mode - Both positive and negative edge capture mode - Timer mode - High Speed Output mode - 8-bit PWM mode - 16-bit PWM mode When the compare/capture modules are programmed in the capture mode, timer mode, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules share one interrupt vector. 11.1 PCA clock select The clock input can be selected from the following four modes: 11.1.1 CCCLK = 00, selected system clock. The PCA counter increments once per system clock. Take a 16MHz oscillator as the example, the counter increments every 62.5ns in 6T mode, or 125ns in 12T mode. 11.1.2 CCCLK = 01, selected system clock/4 The PCA counter increments once every 4 system clocks. Take a 16MHz oscillator as the example, the counter increments every 250ns in 6T mode, or 500ns in 12T mode. 11.1.3 CCCLK = 10, selected system clock/12. The PCA counter increments once every 12 system clocks. Take a 16MHz oscillator as the example, the counter increments every 750ns in 6T mode, or 1.5us in 12T mode. 11.1.4 CCCLK = 11, selected external clock input. The PCA counter increments when a 1-to-0 transition is detected on the CCCI pin (= P1[2]). Fcry . Example, 16MHz oscillator, CCCI must Condition: Whatever 12T or 6T setting, CCCI pin 8 not more than 2MHz.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 41 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Fig. 11-1: PCA clock selection Table 11-1 PCA clock sample period example
Machine cycle 6T 6T 6T 12T 12T 12T 6T/12T Fcry (MHz) 16 16 16 16 16 16 16 CCCLK[1:0] 00 01 10 00 01 10 11 PCA counter increment 1 system clocks 2 system clocks 12 system clocks 1 system clocks 2 system clocks 12 system clocks External clock input (CCCI pin) Div 1 4 12 2 8 24 Sample period(us) 0.0625 0.25 0.75 0.125 0.5 1.5 External clock input (CCCI pin)
Note: Besides PCA counter increment from External clock input, Sample period(us) = 1 / (Fcry / Div)
11.2 PCA Compare/Capture mode 11.2.1 Positive edge capture mode:
The external input pins CC0 through CC4 are sampled for a 0-to 1 transition. When a positive edge transition is detected, hardware loads the 16-bit value of the PCA counter (CCCH, CCCL) into the module's capture registers (CCnDH, CCnDL). The resulting value in the capture registers reflects the PCA timer value at the time a transition was detected on the CCn pin.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 42 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Fig 11-2: PCA capture mode with positive edge 11.2.2 Negative edge capture mode:
The external input pins CC0 through CC4 are sampled for a 1-to 0 transition. When a negative edge transition is detected, hardware loads the 16-bit value of the PCA counter (CCCH, CCCL) into the module's capture registers (CCnDH, CCnDL). The resulting value in the capture registers reflects the PCA timer value at the time a transition was detected on the CCn pin.
Fig 11-3: PCA capture mode with negative edge
11.2.3
Both positive and negative edge capture mode:
The external input pins CC0 through CC4 are sampled for a 0-to-1 or 1-to-0 transition. When a positive edge or negative edge transition is detected, hardware loads the 16-bit value of the PCA counter (CCCH, CCCL) into the module's capture registers (CCnDH, CCnDL). The resulting value in the capture registers reflects the PCA timer value at the time a transition was detected on the CCn pin.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 43 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Fig 11-4: PCA capture mode with both negative and positive edge 11.2.4 Timer mode:
In the Timer mode. When the PCA counter rolls over, the CCnIF bit will be which can then generate an interrupt if CCnIE is enabled
Fig 11-5: PCA Timer mode 11.2.5 High speed output:
The high speed output mode toggles a CCn pin when a match occurs between the PCA counter and a pre-loaded value (CCnD[15:0]) in a module's compare registers. When the PCA counter matches the CCnD register, the TOGn toggles and is output on the CCn pin. Here is an example: If the TOGn register is set to one by software, the hardware will clear the TOGn register and output low on the CCn pin when the PCA counter matches the CCnD register. If software doesn't set the bit before the next match, the hardware will set the TOGn register and output high automatically.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 44 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
CCnD[15:0]
CCnI F
Interrupt
CCnI E
PCA 16 bit counter
16 bit comparator
TOGn register
CCn pin
CCnMOD = 101
Update
Fig 11-6: PCA high speed output 11.2.6 8-bit PWM: Any or all of the five PCA modules can be programmed to be a Pulse Width Modulator (PWM). The PWM output can be used to convert digital data to an analog signal by simple external circuitry. The frequency of the PWM depends on the clock source for the PCA counter. The pulse width depends on the CCnDL[7:0] register and CCnDH[15:8] is not used. When all the bits in CCnDL[7:0] are zero, the CCn pin will be kept low always. The PWM frequency is selected by SFR CCCLK as : When CCCLK = 00, PWM output frequency = Fosc/256. When CCCLK = 01, PWM output frequency = (Fosc/4)/256. When CCCLK = 10, PWM output frequency = (Fosc/12)/256. When CCCLK = 11, PWM output frequency = (CCCI pin frequency )/256. If users want to use the PWM mode, the software must set the CCR register and always keep it high. If software clears the CCR register, the PWM will be disabled and keep the CCn pin to low. 11.2.7 16-bit PWM:
It is almost the same as 8-bit PWM. Any or all of the five PCA modules can be programmed to be a 16-bit PWM. The frequency of the PWM depends on the clock source for the PCA counter. The pulse width depends on the CCnD[15:0] register. When all the bits in CCnD[15:0] are zero, the CCn pin will be kept low always. The PWM frequency is selected by SFR CCCLK as : When CCCLK = 00, PWM output frequency = Fosc/65536. When CCCLK = 01, PWM output frequency = (Fosc/4)/65536. When CCCLK = 10, PWM output frequency = (Fosc/12)/65536. When CCCLK = 11, PWM output frequency = (CCCI pin frequency )/65536. Still, if users want to use this PWM mode, the software must set the CCR register and always keep it high. If software clears the CCR register, the PWM will be disabled and keep the CCn pin to low.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 45 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
11.3 PCA SFR description
Mnemonic
Description PCA control register 1 PCA control register 2 PCA counter high byte PCA counter low byte CC0 control register CC0 data high byte CC0 data low byte CC1 control register CC1 data high byte CC1 data low byte CC2 control register CC2 data high byte CC2 data low byte CC3 control register CC3 data high byte CC3 data low byte CC4 control register CC4 data high byte CC4 data low byte
Direct
Bit 7 CCR
Bit 6 CIDL
Bit 5 PCA -
Bit 4 CC4IE CC4IF
Bit 3 CC3IE CC3IF
Bit 2 CC2IE CC2IF
Bit 1 CC1IE CC1IF
Bit 0 CC0IE CC0IF
RESET
PCAC1 PCAC2 PCAH PCAL CC0CON CC0DH CC0DL CC1CON CC1DH CC1DL CC2CON CC2DH CC2DL CC3CON CC3DH CC3DL CC4CON CC4DH CC4DL
A1h A2h 9Ah 9Bh A3h 9Ch 9Dh A4h 9Eh 9Fh A5h 91h 92h A6h 93h 94h A7h 95h 96h
00h 00h 00h 00h
CCCLK[1:0]
PCA[15:8] PCA[7:0] TOG0 CC0MOD[2:0]
00h 00h 00h
CC0D[15:8] CC0D[7:0] TOG1 CC1MOD[2:0]
00h 00h 00h
CC1D[15:8] CC1D[7:0] TOG2 CC2MOD[2:0]
00h 00h 00h
CC2D[15:8] CC2D[7:0] TOG3 CC3MOD[2:0]
00h 00h 00h
CC3D[15:8] CC3D[7:0] TOG4 CC4MOD[2:0]
00h 00h 00h
CC4D[15:8] CC4D[7:0]
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 46 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
11.3.1
PCA Control register 1 Mnemonic: PCAC1 7 6 CCR CIDL R/W R/W 5 4 CC4IE R/W 3 CC3IE R/W 2 CC2IE R/W 1 CC1IE R/W Address: A1h 0 Reset CC0IE 00h R/W
CCR: PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. CIDL: Counter Idle control: CIDL = 0 programs the PCA counter to continue functioning during idle mode. CIDL = 1 programs it to be gated off during idle. CCnIE: CC0 ~ CC4 interrupt enable. CCnIE = 1, enable interrupt. CCnIE = 0, disable interrupt. 11.3.2 PCA Control register 2 Mnemonic: PCAC2 7 6 CCCLK[1:0] R/W 5 4 CC4IF R/W 3 CC3IF R/W 2 CC2IF R/W 1 CC1IF R/W Address: A2h 0 Reset CC0IF 00h R/W
CCCLK[1:0] Compare/Capture clock source select CC0CLK[1:0] 00 01 10 11 Clock source Fosc Fosc/4 Fosc/12 External clock input (CCCI pin)
CCnIF CC0 ~ CC4 interrupt flag. Must be cleared by software. 11.3.3 PCA Counter register Mnemonic: PCAH 7 6 5 4 3 PCA[15:8] R/W 4 3 PCA[7:0] R/W 2 1 Address: 9Ah 0 Reset 00h Address: 9Bh 0 Reset 00h
Mnemonic: PCAL 7 6
5
2
1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 47 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
11.3.4
Compare/Capture channel 0 control register Mnemonic: CC0CON 7 6 5 4 TOG0 R/W 3 2 Address: A3h 1 0 Reset CC0MOD[2:0] 00h R/W
CC0MOD[2:0] Compare/Capture channel 0 modes select. CC0MOD[2:0] 000 001 010 011 100 101 110 111 TOG0: CC0 toggle register. Function Disable PCA channel 0 Positive edge capture mode Negative edge capture mode Both positive and negative edge capture mode Timer mode High Speed Output mode 8-bit PWM 16-bit PWM
11.3.5
CC0 Data register Mnemonic: CC0DH 7 6 5 4 3 CC0D[15:8] R/W 4 3 CC0D[7:0] R/W 2 1 Address: 9Ch 0 Reset 00h Address: 9Dh 0 Reset 00h
Mnemonic: CC0DL 7 6
5
2
1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 48 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
11.3.6
Compare/Capture channel 1 control register Mnemonic: CC1CON 7 6 5 Address: A4h 2 1 0 Reset CC1MOD[2:0] 00h R/W
4 TOG1 R/W
3 -
CC1MOD[2:0] Compare/Capture channel 1 modes select. CC1MOD[2:0] 000 001 010 011 100 101 110 111 TOG1: CC1 toggle register. Function Disable PCA channel 1 Positive edge capture mode Negative edge capture mode Both positive and negative edge capture mode Timer mode High Speed Output mode 8-bit PWM 16-bit PWM
11.3.7
CC1 Data register Mnemonic: CC1DH 7 6 5 4 3 CC1D[15:8] R/W 4 3 CC1D[7:0] R/W 2 1 Address: 9Eh 0 Reset 00h Address: 9Fh 0 Reset 00h
Mnemonic: CC1DL 7 6
5
2
1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 49 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
11.3.8
Compare/Capture channel 2 control register Mnemonic: CC2CON 7 6 5 4 TOG2 R/W 3 2 Address: A5h 1 0 Reset CC2MOD[2:0] 00h R/W
CC2MOD[2:0] Compare/Capture channel 2 modes select. CC2MOD[2:0] 000 001 010 011 100 101 110 111 TOG2: CC2 toggle register. Function Disable PCA channel 2 Positive edge capture mode Negative edge capture mode Both positive and negative edge capture mode Timer mode High Speed Output mode 8-bit PWM 16-bit PWM
11.3.9
CC2 Data register Mnemonic: CC2DH 7 6 5 4 3 CC2D[15:8] R/W 4 3 CC2D[7:0] R/W 2 1 Address: 91h 0 Reset 00h Address: 92h 0 Reset 00h
Mnemonic: CC2DL 7 6
5
2
1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 50 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
11.3.10 Compare/Capture channel 3 control register Mnemonic: CC3CON 7 6 5 4 TOG3 R/W 3 Address: A6h Res 2 1 0 et CC3MOD[2:0] 00h R/W
CC3MOD[2:0] Compare/Capture channel 3 modes select. CC3MOD[2:0] 000 001 010 011 100 101 110 111 TOG3: CC3 toggle register. Function Disable PCA channel 3 Positive edge capture mode Negative edge capture mode Both positive and negative edge capture mode Timer mode High Speed Output mode 8-bit PWM 16-bit PWM
11.3.11 CC3 Data register Mnemonic: CC3DH 7 6 5 4 3 CC3D[15:8] R/W 4 3 CC3D[7:0] R/W 2 1 Address: 93h 0 Reset 00h Address: 94h 0 Reset 00h
Mnemonic: CC3DL 7 6
5
2
1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 51 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
11.3.12 Compare/Capture channel 4 control register Mnemonic: CC4CON 7 6 5 4 TOG4 R/W 3 2 Address: A7h 1 0 Reset CC4MOD[2:0] 00h R/W
CC4MOD[2:0] Compare/Capture channel 4 modes select. CC4MOD[2:0] 000 001 010 011 100 101 110 111 TOG4: CC4 toggle register. Function Disable PCA channel 4 Positive edge capture mode Negative edge capture mode Both positive and negative edge capture mode Timer mode High Speed Output mode 8-bit PWM 16-bit PWM
11.3.13 CC4 Data register Mnemonic: CC4DH 7 6 5 4 3 CC4D[15:8] R/W 4 3 CC4D[7:0] R/W 2 1 Address: 95h 0 Reset 00h Address: 96h 0 Reset 00h
Mnemonic: CC4DL 7 6
5
2
1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 52 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
12 Expanded External Interrupt (EEI) interface SM59D04G2 implements an EEI interface allowing the connection of an 8xn matrix keyboard. It is based on 8 inputs with programmable interrupt capability for either high or low levels. These inputs are available as an alternate function of P1 and allow to exit from idle and power-down modes given in Section 14. The EEI interfaces with the CPU core through 3 SFR: KBLS, the EEI Level Selection register, KBE, the EEI Enable register, and KBF, the EEI Flag register. The EEI inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. Figure 12-1 shows that each EEI input has the capability to detect a programmable level according to KBLS.x bit value. Level detection is then reported in interrupt flags KBF.X that can be masked by software using KBE.x bits. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard interrupt as in Fig. 12-2. This structure allows keyboard arrangements from 1xn to 8xn matrix, and allows usage of P1 inputs for other purpose. P1 inputs allow exiting from the idle and power-down modes
Figure 12.1 EEI interface Block Diagram
EEI Interface Interrupt Request
Figure 12.2 EEI input Circuitry
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 53 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
12.1 EEI SFR description
Mnemonic
Description EEI level Selector register EEI Input Enable register EEI Flag register
Direct
Bit 7 KBLS7 KBE7 KBF7
Bit 6 Bit 5 Bit 4 Keyboard interface KBLS6 KBE6 KBF6 KBLS5 KBE5 KBF5 KBLS4 KBE4 KBF4
Bit 3 KBLS3 KBE3 KBF3
Bit 2 KBLS2 KBE2 KBF2
Bit 1 KBLS1 KBE1 KBF1
Bit 0 KBLS0 KBE0 KBF0
RESET
KBLS KBE KBF
FDh FEh FFh
00h 00h 00h
12.1.1
EEI level selector register Mnemonic: KBLS 7 6 KBLS7 KBLS6 R/W R/W 5 KBLS5 R/W 4 KBLS4 R/W 3 KBLS3 R/W 2 KBLS2 R/W 1 KBLS1 R/W Address: FDh 0 Reset KBLS0 00h R/W
KBLS7: EEI line 7 level selection bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. KBLS6: EEI line 6 level selection bit Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6. KBLS5: EEI line 5 level selection bit Cleared to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5. KBLS4: EEI line 4 level selection bit Cleared to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4. KBLS3: EEI line 3 level selection bit Cleared to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3. KBLS2: EEI line 2 level selection bit Cleared to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2. KBLS1: EEI line 1 level selection bit Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. KBLS0: EEI line 0 level selection bit Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 54 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
12.1.2
EEI input enable register Mnemonic: KBE 7 6 KBE7 KBE6 R/W R/W 5 KBE5 R/W 4 KBE4 R/W 3 KBE3 R/W 2 KBE2 R/W 1 KBE1 R/W Address: FEh 0 Reset KBE0 00h R/W
KBE7: EEI line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.7 bit in KBE register to generate an EEI interrupt request. KBE6: EEI line 6 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.6 bit in KBE register to generate an interrupt request. KBE5: EEI line 5 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.5 bit in KBE register to generate an interrupt request. KBE4: EEI line 4 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.4 bit in KBE register to generate an interrupt request. KBE3: EEI line 3 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.3 bit in KBE register to generate an interrupt request. KBE2: EEI line 2 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.2 bit in KBE register to generate an interrupt request. KBE1: EEI line 1 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.1 bit in KBE register to generate an interrupt request. KBE0: EEI line 0 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.0 bit in KBE register to generate an interrupt request.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 55 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
12.1.3
EEI flag register Mnemonic: KBF 7 6 5 KBF7 KBF6 KBF5 R R R
4 KBF4 R
3 KBF3 R
2 KBF2 R
1 KBF1 R
Address: FFh 0 Reset KBF0 00h R
KBF7: EEI line 7 flag Set by hardware when the port line 7 detects a programmed level. It generates a EEI interrupt request if the KBE.7 bit in KBE register is set. This register is read only access; the flag is automatically cleared by reading the register. KBF6: EEI line 6 flag Set by hardware when the port line 6 detects a programmed level. It generates a EEI interrupt request if the KBE.6 bit in KBE register is set. This register is read only access; the flag is automatically cleared by reading the register. KBF5: EEI line 5 flag Set by hardware when the port line 5 detects a programmed level. It generates a EEI interrupt request if the KBE.5 bit in KBE register is set. This register is read only access; the flag is automatically cleared by reading the register. KBF4: EEI line 4 flag Set by hardware when the port line 4 detects a programmed level. It generates a EEI interrupt request if the KBE.4 bit in KBE register is set. This register is read only access; the flag is automatically cleared by reading the register. KBF3: EEI line 3 flag Set by hardware when the port line 3 detects a programmed level. It generates a EEI interrupt request if the KBE.3 bit in KBE register is set. This register is read only access; the flag is automatically cleared by reading the register. KBF2: EEI line 2 flag Set by hardware when the port line 2 detects a programmed level. It generates a EEI interrupt request if the KBE.2 bit in KBE register is set. This register is read only access; the flag is automatically cleared by reading the register. KBF1: EEI line 1 flag Set by hardware when the port line 1 detects a programmed level. It generates a EEI interrupt request if the KBE.1 bit in KBE register is set. This register is read only access; the flag is automatically cleared by reading the register. KBF0: EEI line 0 flag Set by hardware when the port line 0 detects a programmed level. It generates a EEI interrupt request if the KBE.0 bit in KBE register is set. This register is read only access; the flag is automatically cleared by reading the register.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 56 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
13 Interrupts SM59D04G2 has a total of 8 interrupt vectors, they include two external interrupts, three timer interrupts, one serial port interrupts, EEI interrupts, and a PCA interrupt. Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the IE or IE1 register. This register also contains a global disable bit, which must be cleared to disable all interrupt at once. Interrupt Source External interrupt 0 Timer 0 External interrupt 1 Timer 1 Serial Port Timer 2 EEI PCA interrupt 13.1 SFR description
Mnemonic IE IE1 IP IP1 Description Interrupt Enable register Interrupt Enable 1 register Interrupt Priority register Interrupt Priority 1 register
Direct
Interrupt Vector 0003h 000Bh 0013h 001Bh 0023h 002Bh 0033h 003Bh
Polling sequence
Polling sequence
Bit 7 EA -
Bit 6 Bit 5 EEI interface ET2 PT2 -
Bit 4 ES PS -
Bit 3 ET1 PT1 -
Bit 2 EX1 PX1 -
Bit 1 ET0 EPCA PT0 PPCA
Bit 0 EX0 KBD PX0 PKBD
RESET
A8h A9h B8h B9h
00h 00h 00h 00h
Mnemonic: IE 7 6 EA -
5 ET2
4 ES
3 ET1
2 EX1
1 ET0
Address: A8h 0 Reset EX0 00h
EA: Disable all interrupt. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ET2: Timer 2 interrupt enable bit. ES: Serial port 0 interrupt enable bit. ET1: Timer 1 interrupt enable bit. EX1: External interrupt 1 enable bit. ET0: Timer 0 interrupt enable bit. EX0: External interrupt 0 enable bit.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 57 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Mnemonic: IE1 7 6 -
5 -
4 -
3 -
2 -
1 EPCA
Address: A9h 0 Reset KBD 00h
EPCA: PCA interrupt enable bit. KBD: EEI interrupt enable bit. Cleared to disable EEI interrupt. Set to enable EEI interrupt. Mnemonic: IP 7 6 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 Address: B8h 0 Reset PX0 00h
PT2: Timer 2 interrupt priority bit. PT2 = 1 is high priority. PS: Serial port 0 interrupt priority bit. PS = 1 is high priority. PT1: Timer 1 interrupt priority bit. PT1 = 1 is high priority. PX1: External interrupt 1 priority bit. PX1 = 1 is high priority. PT0: Timer 0 interrupt priority bit. PT0 = 1 is high priority. PX0: External interrupt 0 priority bit. PX0 = 1 is high priority. Mnemonic: IP1 7 6 5 4 3 2 1 PPCA Address: B9h 0 Reset PKBD 00h
PPCA: PCA interrupt priority bit. PPCA = 1 is high priority. PKBD: EEI interrupt priority bit. PKBD = 1 is high priority.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 58 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
14 Power Management 14.1 Idle Mode The user can enter the idle mode by setting the IDLE bit in the PCON register. In the idle mode, the internal clock to the CPU part is stopped but the clock still remains for the peripherals and the interrupt logic continues. The CPU part will exit idle mode when either an interrupt or a reset occurs. 14.2 Power down mode When the PD bit in the PCON register is set, the CPU enters the power-down mode as idle mode does. But the peripherals are also stopped. To exit from power down mode is done by a hardware reset or external interrupts. 14.3 SFR description
Mnemonic PCON Description Power Control
Direct
Bit 7 SMOD
87h
Bit 6 Bit 5 Bit 4 Power Management -
Bit 3 GF1
Bit 2 GF0
Bit 1 PD
Bit 0 IDLE
RESET
00h
Mnemonic: PCON
7 SMOD 6
-
Address: 87h
4 3 GF1 2 GF0 1 PD 0 IDLE Reset 00h
5
GF1: General-purpose flag bit. GF0: General-purpose flag bit. PD: When set to "1", the MCU will into Power-down mode. IDLE: When set to "1", the MCU will into IDLE mode.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 59 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Operating Conditions
Symbol TA VCC5 Fosc 25 Description Operating temperature Supply voltage Oscillator Frequency Min. -40 4.5 2 Typ. 25 5.0 25 Max. 85 5.5 25 Unit.
Remarks Ambient temperature under bias
V MHz
DC Characteristics
(TA = -40 degree C to 85 degree C, Vcc = 5V) Symbol
VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC
Parameter
Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Power Supply Current
Valid
port 0,1,2,3,4,#EA RES, XTAL1 port 0,1,2,3,4,#EA RES, XTAL1 port 0, ALE, #PSEN port 1,2,3,4 port 0 port 1,2,3,4,ALE,#PSEN port 1,2,3,4 port 1,2,3,4 port 0, #EA RES Vdd
Min. -0.5 0 2.0 70%Vcc
Max. 0.8 0.8 Vcc+0.5 Vcc+0.5 0.45 0.45
Unit V V V V V V V V V V
Test Conditions
IOL=3.2mA IOL=1.6mA IOH=-800uA IOH=-80uA IOH=-60uA IOH=-10uA Vin=0.45V Vin=2.0V 0.45V2.4 90%Vcc 2.4 90%Vcc -75 -650 10 50 300 10 20 6.5 50
uA uA uA Kohm pF mA mA uA
Freq=1MHz, Ta=25 Active mode, 16MHz Idle mode, 16MHz Power down mode
Note1:Under steady state (non-transient) conditions, IOL must be externally
Icc Active Mode Test Circuit Icc
VDD
NC Clock Signal
XTAL2 XTAL1 VSS
SM59D04G2
P0 EA RST
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 60 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
AC Characteristics
(16/25 MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Output=80pF)
Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX T, TCLCL Parameter ALE pulse width Address Valid to ALE low Address Hold after ALE low ALE low to Valid Instruction In ALE low to #PSEN low #PSEN pulse width #PSEN low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN low to Address Float #RD pulse width #WR pulse width #RD low to Valid Data In Data Hold after #RD Data Float after #RD ALE low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD low Address Valid to #WR or #RD low Data Valid to #WR High Data Valid to #WR transition Data hold after #WR #RD low to Address Float #WR or #RD high to ALE high clock fall time clock low time clock rise time clock high time clock period 63 1/fosc Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT 53 72 T -10 178 230 403 38 73 0 145 590 542 197 3xT-10 4xT-20 7xT-35 T - 25 T + 10 5 T + 10 365 365 302 0 2xT+20 8xT - 10 9xT - 20 3xT+10 0 87 292 10 6xT - 10 6xT - 10 5xT - 10 53 173 177 0 T + 25 5xT -20 10 fosc=16MHz Min. Typ. Max 115 43 53 240 T - 10 3xT - 15 3xT-10 Min. 2xT - 10 T - 20 T - 10 4xT-10 Variable fosc Typ. Max nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Unit Remarks
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 61 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Application Reference
Valid for SM59D04G2
XTAL2
Crystal
X'tal C1 C2 X'tal C1 C2
2MHz 47 pF 47 pF 16MHz 30 pF 30 pF
6MHz 35 pF 35 pF 25MHz 25 pF 25 pF
10MHz 30 pF 30 pF
12MHz 30 pF 30 pF C2
SM59D04G2
XTAL1
C1
VSS
NOTE: Oscillation circuit may differ with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. User should check with the crystal or ceramic resonator manufacture for appropriate value of external components.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 62 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Data Memory Read Cycle Timing
Program Memory Read Cycle Timing
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 63 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Data Memory Write Cycle Timing
I/O Ports Timing
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 64 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Timing Critical, Requirement of External Clock
(Vss=0.0V is assumed)
Tm.I External Program Memory Read Cycle
Tm.II External Data Memory Read Cycle
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 65 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
Tm.III External Data Memory Write Cycle
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 66 Ver.C SM59D04G2 07/2009
SM59D04G2
8-Bits Micro-controller
16KB+ ISP Flash & 1KB RAM embedded
MCU writer list
Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Contact info Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw Programmer Model Number Lab Tool - 48XP/UXP Lab Tool - 848/848XP
Hi-Lo 4F.,No.18,Lane 79,Rueiguang Rd.,Neihu,Taipei,Taiwan R.O.C. Web site: http://www.hilosystems.com.tw
Tel: 02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw
All - 100 series
Xeltek Electronic Co., Ltd Bldg 6-31 Meizhiguo garden, #2 Jiangjun Ave., Jiangning, Nanjing, China 211100 Web site: http://www.xeltek-cn.com Guangzhou Zhiyuan Electronic Co.,Ltd Floor 2,No.7 building,Huangzhou Industrial Estate,Chebei Road,Tianhe district,Guangzhou,China 510660 Web site: http://www.embedtools.com/ TianJin Weilei technology ltd Rm 357,Venturetech Center,12 Keyan West Road Nankai District,Tianjin,P.R.C, 300192 Web site: http://www.weilei.com.cn/
Tel: + 86-25-52765201, E-mail: f_l@xeltek.com.cn zxl@xeltek.com.cn
Superpro 280U Superpro 580U Superpro 3000U Superpro 9000U
TEL: +86-20-28872449 E-mail: mcu@programtec.com
SmartPRO 5000U/X8
TEL: + 86-22-87891218#801 E-mail: weilong@weilei.com.cn cm@weilei.com.cn
VP-890;VP-980;VP-880;VP-680 VP-480;VP-380;VP-280;VP-190
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 67 Ver.C SM59D04G2 07/2009

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