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ST
ST8009
96 Output LCD Common/ Segment Driver IC
Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. specification. Some parameters are subject to change. This is not a final
1. DESCRIPTION
The ST8009 is a 96-output segment/common driver IC suitable for driving small/medium scale dot matrix LCD panels, and is used in PDA or electronic dictionary. The ST8009 is good as a segment driver, a common driver or a common/segment driver, and it can create low power consumption, high-resolution LCD. The ST8009 have eight modes can selected to set common and segment numbers by selecting register. The ST8009 also have analog DC/DC converter to use.
Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratio of 2X/3X/4X/5X/6X) Regulator circuit Follower circuit Package: 124-pin COB.
(Segment mode) Shift clock frequency - 20 MHz (MAX.): VDD = +5.0 0.5 V - 15 MHz (MAX.): VDD = +3.0 to + 4.5 V - 12 MHz (MAX.): VDD = +2.5 to + 3.0 V Adopts a data bus system 4-bit parallel / serial input modes are selectable by programmable. Automatic transfer function of an enable signal Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 16324864 8096 bits of input data Line latch circuits are reset when XDISPOFF active
2. FEATURES
Number of LCD drive outputs: 96 Supply voltage for LCD drive (VOUT): Max +16V Supply voltage for logic system (VDD): +2.5 ~ +5.5V Low power consumption and low output impedance Display duty selectable by internal select register DU2,DU1,DU0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Abundant command functions DUTY --1/16 1/32 1/48 1/64 1/80 1/96 1/96
(Common mode) Shift clock frequency: 4 MHz (MAX.) Built-in X-bit shift register Available in a single mode CS0 CSX CSX Single mode CS0 Single mode
LCD bias set, electronic volume, VSS voltage regulation internal resistor ratio and booster frequency. All Functions have initial value, user can set by programmed.
PS:X=153147637995 The above 4 shift directions are register selectable Shift register circuits are reset when XDISPOFF active
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3. PAD ARRANGEMENT
Chip size: 5070.0(um) x1790.0 (um) Pad size80 (um) x80 (um) Pad pin pitch: 100 (um) ~ 140 (um) Origin : chip center (0,0) Chip Thickness19 mil
Substrate Connect to VSS.
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4. PAD CONFIGURATION
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function CS[86] CS[87] CS[88] CS[89] CS[90] CS[91] CS[92] CS[93] CS[94] CS[95]
VOUT
X 2450 2310 2180 2060 1950 1850 1750 1650 1550 1450 1350 1250 1150 1050 950 850 750 650 550 450 350 250 150 50 -50 -150 -250 -350 -450 -550 -650 -750
Y 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810
Pad No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Function SCLK FR LP2 LP1
VSS VDD
X -850 -950 -1050 -1150 -1250 -1350 -1450 -1550 -1650 -1750 -1850 -1950 -2060 -2180 -2310 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2450 -2310
Y 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 810 680 560 450 350 250 150 50 -50 -150 -250 -350 -450 -560 -680 -810 -810
CS[0] CS[1] CS[2] CS[3] CS[4] CS[5] CS[6] CS[7] CS[8] CS[9] CS[10] CS[11] CS[12] CS[13] CS[14] CS[15] CS[16] CS[17] CS[18] CS[19] CS[20] CS[21] CS[22] CS[23] CS[24] CS[25]
CAP3P CAP1N CAP1P CAP2P CAP2N CAP4P CAP5P V0 V1 V2 V3 V4 ED[3] ED[2] ED[1] ED[0] EIO1 EIO2 XCK
XDISPOFF
SID
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Pad No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97
Function CS[26] CS[27] CS[28] CS[29] CS[30] CS[31] CS[32] CS[33] CS[34] CS[35] CS[36] CS[37] CS[38] CS[39] CS[40] CS[41] CS[42] CS[43] CS[44] CS[45] CS[46] CS[47] CS[48] CS[49] CS[50] CS[51] CS[52] CS[53] CS[54] CS[55] CS[56] CS[57] CS[58]
X -2180 -2060 -1950 -1850 -1750 -1650 -1550 -1450 -1350 -1250 -1150 -1050 -950 -850 -750 -650 -550 -450 -350 -250 -150 -50 50 150 250 350 450 550 650 750 850 950 1050
Y -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810
Pad No. 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124
Function Function CS[59] CS[60] CS[61] CS[62] CS[63] CS[64] CS[65] CS[66] CS[67] CS[68] CS[69] CS[70] CS[71] CS[72] CS[73] CS[74] CS[75] CS[76] CS[77] CS[78] CS[79] CS[80] CS[81] CS[82] CS[83] CS[84] CS[85]
X 1150 1250 1350 1450 1550 1650 1750 1850 1950 2060 2180 2310 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450 2450
Y -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -810 -680 -560 -450 -350 -250 -150 -50 50 150 250 350 450 560 680
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5. PIN DESCRIPTION
SYMBOL CS0~CS95 V0~V4 VDD EIO2, EIO1 DI0~DI3 XCK XDISPOFF LP1 LP2 FR VSS CAP1I/O O P P I/O I I I I I I P O DESCRIPTION LCD drive output Power supply for LCD drive Power supply for logic system (+2.5 to +5.5 V) Input/output for chip selection at segment mode and FLM input output function at com/seg mix mode or common mode Display data input at segment mode Clock input for taking display data at segment mode Control input for output of ground level Latch pulse input for display data at segment mode Shift clock input for shift register at common mode AC-converting signal input for LCD drive waveform Ground (0 V) DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. The command data. See Figure1 The serial clock input. See Figure1 1 1 1 No of Num 96 5 1 2 4 1 1 1 1 1 1 1
CAP1+
O
1
CAP2-
O
1
CAP2+
O
1
CAP3+
O
1
CAP4+
O
1
CAP5+
O
VOUT SID SCLK
O I I
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6. BLOCK DIAGRAM
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7. INPUT/OUTPUT CIRCUITS
V DD
I
T o In te rn a l C irc u it A p p lic a b le P in s D I3 ~ D I0 , X D IS P O F F , L P 1 ,L P 2 , F R S C L K ,S ID V s s (0 V )
Input Circuit (1)
V
DD
I/O
To Internal Circuit Control Signal
Vss (0V)
Vss (0V)
VDD
Output Signal
Application Pins EIO Control Signal Vss (0V)
1
, EIO
2
Input/Output Circuit
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8. PIN FUNCTIONAL DESCRIPTION
8.1 Pin Functions
(Segment mode) SYMBOL VDD VSS FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. When the internal power supply circuit turns on The internal power supply circuit will produce the LCD bias voltage set( V0 ~ V4 ), and those V0 , V1 V2 , V3 V4 voltages are setting by the "LCD Bias Set" register. When the internal power supply circuit turns off Supply the bias voltages set by a resistor divider externally , and had better use follower circuit to hold those voltages. Ensure that voltages are set such that V0 V1 V2 V3 V4 VSS Input pins for display data In 4-bit parallel input mode, connect data to the 4 pins, DI3-DI0. DI3~DI0 In serial input mode, connect data to the DI0 pin, and DI3-DI1 must be connected to VSS . Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. LP1 XCK Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. Clock input for taking display data at segment mode The switch for turn on or turn off the LCD display The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (CS0-CS95) are set to level VSS. XDISPOFF When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of XDISPOFF. When the XDISPOFF function is canceled, the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is shown in AC characteristics, it cannot output the reading data correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. FR Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
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ST8009 Input/output pins for chip selection. When L/R register is set `0' , EIO1 is set for output, and EIO2 is set for input(connect to VSS). When L/R register is set `1', EIO1 is set for input(connect to VSS), and EIO2 is set for output. EIO1, EIO2 During output, set to "H" while LP * XCK is "H" and after 96 bits of data have been read, set to "L" for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 96 bits of data have been read. LCD drive output pins CS0~CS95 Corresponding directly to each bit of the data latch, one level (V0, V2 ,V3, VSS) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. CAP1CAP1+ CAP2CAP2+ CAP3+ CAP4+ VOUT SID SCLK DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. The serial command data. See Figure1 The serial clock input. See Figure1
(Common mode) SYMBOL VDD VSS FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. When the internal power supply circuit turns on The internal power supply circuit will produce the LCD bias voltage set( V0 ~ V4 ), and those V0, V1 V2, V3 V4 voltages are setting by the "LCD Bias Set" register. When the internal power supply circuit turns off Supply the bias voltages set by a resistor divider externally , and had better use follower circuit to hold those voltages. Ensure that voltages are set such that V0 V1 V2 V3 V4 VSS DI3-DI0 Not used. Connect DI3-DI0 to VSS, not floating. Shift clock pulse input pin for bi-directional shift register LP2 * Data is shifted at the falling edge of the clock pulse. When use gray scale mode, then must use the pin. When use monochrome mode, then the pin should be shorted to LP1. XCK Not used Not let it floating , connect to VSS 9/43 2006/11/1
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ST8009 The switch for turn on or turn off the LCD display The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (CS0-CS95) are set to level VSS. XDISPOFF When set to "L", the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V1 or V4), and the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. FR Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. LCD drive output pins CS0 ~CS95 Corresponding directly to each bit of the shift register, one level (V0 V1, V4, or VSS) is selected and output. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Shift data Input/output pins for shift register EIO1 is output pin when L/R is at VSS level "L", EIO1 is input pin when L/R is at VDD level "H" When L/R register ='1', EIO1 is used as input pin, it will be connect to FLM. When L/R register ='0', EIO1 is used as output pin, it won't be connect to FLM. EIO1, EIO2 EIO2 is input pin when L/R is at VSS level "L", EIO1 is output pin when L/R is at VDD level "H" When L/R register ='1', EIO2 is used as output pin, it won't be connect to FLM, When L/R register ='0', EIO2 is used as input pin, it will be connect to FLM Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. CAP1CAP1+ CAP2CAP2+ CAP3+ CAP4+ VOUT SID SCLK DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. The serial command data. See Figure1 The serial clock input. See Figure1
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(common /segment mix mode)
SYMBOL VDD VSS FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. When the internal power supply circuit turns on : The internal power supply circuit will produce the LCD bias voltage set( V0 ~ V4 ), and those V0 , V1 V2 , V3 V4 voltages are setting by the "LCD Bias Set" register. When the internal power supply circuit turns off : Supply the bias voltages set by a resistor divider externally , and had better use follower circuit to hold those voltages. Ensure that voltages are set such that V0 V1 V2 V3 V4 VSS Input pins for display data In 4-bit parallel input mode, input data into the 4 pins, DI3~DI0. DI3~DI0 In serial input mode, connect data to the DI0 pin, and DI3-DI1 must be connected to VSS . Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. XCK Clock input pin for taking display data Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. Shift clock pulse input pin for bi-directional shift register LP2 Data is shifted at the falling edge of the clock pulse. When use gray scale mode, then must use the pin. When use monochrome mode, then the pin should be shorted to LP1. The switch for turn on or turn off the LCD display The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (CS0-CS95) are set to level VSS. XDISPOFF When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of XDISPOFF. When the XDISPOFF function is canceled, the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is shown in AC characteristics, it cannot output the reading data correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the FR LCD drive circuit. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal, and it inputs a frame inversion signal normally. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. V1.1 11/43 2006/11/1
LP1
ST8009 Input/output pins for chip selection When L/R register is `0', EIO1 is set output, and EIO2 is set for input. EIO1 : segment chip enable output, as default segment is enabled internally and be non-selected after 16,32,48,64 or 80 bits of data have been read. Depend on select mode. ElO2 :common shift data input, no sift data output When L/R register is `1', EIO1 is set for input, and EIO2 is set for output. EIO1, EIO2 EIO1 :common shift data, no shift data output ElO2 : segment chip enable output, as default segment is enabled internally and be non-selected after 16,32,48,64 or 80 bits of data have been read. Depend on select mode. During output, set to "H" while LP * XCK is "H" and after 96 bits of data have been read, set to "L" for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 96 bits of data have been read. LCD drive output pins CS0 ~CS95 Corresponding directly to each bit of the data latch, one level (V0, V2, V3, VSS) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. CAP1CAP1+ CAP2CAP2+ CAP3+ CAP4+ VOUT XCS SID SCLK DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. This is the command mode select pin. When XCS="L" then write command to the LCD, when not used the command mode then must fixed to VDD . See Figure1 The command data. See Figure1 The serial clock input. See Figure1
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8.2 Functional Operations 8.2.1 TRUTH TABLE
(Segment Mode) FR L L H H X (Common Mode) FR L L H H X NOTES: L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage that is assigned by specification for each power pin. LATCH DATA L H L H X /DISPOFF H H H H L LCD DRIVE OUTPUT VOLTAGE LEVEL (CS0-CS95) V4 V0 V1 VSS VSS LATCH DATA L H L H X /DISPOFF H H H H L LCD DRIVE OUTPUT VOLTAGE LEVEL (CS0-CS95) V3 VSS V2 V0 VSS
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8.2.2 RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS (Segment Mode) (A) 4-bit Parallel Input Mode
DATA NUMBER OF CLOCKS
L/R
EIO1
EIO2
INPUT 24 CLOCK 23 CLOCK 22 CLOCK ... 3 CLOCK 2 CLOCK 1 CLOCK DI0 CS0 CS1 CS2 CS3 CS95 CS94 CS93 CS92 CS4 CS5 CS6 CS7 CS91 CS90 CS89 CS88 CS8 CS9 CS10 CS11 CS87 CS86 CS85 CS84 ... ... ... ... ... ... ... ... CS84 CS85 CS86 CS87 CS11 CS10 CS9 CS8 CS88 CS89 CS90 CS91 CS7 CS6 CS5 CS4 CS92 CS93 CS94 CS95 CS3 CS2 CS1 CS0
L
Output Input
DI1 DI2 DI3 DI0
H
Input
Output
DI1 DI2 DI3
(B) Serial Input Mode
DATA NUMBER OF CLOCKS 3 CLOCK CS93 X X X CS2 X X X 2 CLOCK CS94 X X X CS1 X X X 1 CLOCK CS95 X X X CS0 X X X
L/R
EIO1
EIO2
INPUT 120 CLOCK 119 CLOCK 118 CLOCK ... DI0 CS0 X X X CS95 X X X CS1 X X X CS94 X X X CS2 X X X CS93 X X X ... X X X ... X X X
L
Output Input
Dl1 DI2 DI3 DI0
H
Input Output
Dl1 DI2 DI3
(Common Mode)
L/R L H
DATA TRANSFER DIRECTION CS95 CS0 CS0 CS95
EIO1 Output Input
EIO2 Input Output
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ST8009 MIX MODE(SEGMENT/ COMMON MODE) When (DU2,DU1,DU0)=(0,1,0) SELECT THE 32 COM / 64 SEGMENT MODE
THEN SEGMENT SIDE OF MIX MODE
(A) 4-bit Parallel Input Mode
DATA NUMBER OF CLOCKS
L/R
EIO1
EIO2
INPUT 16 CLOCK 15 CLOCK 14 CLOCK ... 3 CLOCK 2 CLOCK 1 CLOCK DI0 CS0 CS1 CS2 CS3 CS95 CS94 CS93 CS92 CS4 CS5 CS6 CS7 CS91 CS90 CS89 CS88 CS8 CS9 CS10 CS11 CS87 CS86 CS85 CS84 ... ... ... ... ... ... ... ... CS52 CS53 CS54 CS55 CS43 CS42 CS41 CS40 CS56 CS57 CS58 CS59 CS39 CS38 CS37 CS36 CS60 CS61 CS62 CS63 CS35 CS34 CS33 CS32
L
Seg_end Com_FLM Output Input
Dl1 DI2 DI3 DI0
H
Com_FLM Seg_end Input Output
Dl1 DI2 DI3
(B) Serial Input Mode
DATA NUMBER OF CLOCKS 3 CLOCK 2 CLOCK 1 CLOCK CS61 X X X CS34 X X X CS62 X X X CS33 X X X CS63 X X X CS32 X X X
L/R
EIO1
EIO2
INPUT 64 CLOCK 63 CLOCK 62CLOCK ... DI0 CS0 X X X CS95 X X X CS1 X X X CS94 X X X CS2 X X X CS93 X X X ... X X X ... X X X
L
Seg_end Output
Com_FLM Input
Dl1 DI2 DI3 DI0
H
Com_FLM Input
Seg_end Output
Dl1 DI2 DI3
COMMON SIDE OF MIX MODE L/R L H NOTES: L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. DATA TRANSFER DIRECTION CS95 CS62 CS0 CS31 EIO1 Seg_end output Input EIO2 Input Seg_end output
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8.2.3 Connection examples of plural segment drivers in 4-bits interface( 288 segment )
(a) When the L/R register set "L" level
Top data Y95 EIO2 Y0 EIO1 Y95 EIO2 Y0 EIO1 Y95 EIO2
Last data Y0 EIO1
DI0~DI3
DI0~DI3
DI0~DI3
XCK
XCK
XCK
FR
FR
FR
LP
LP
LP
Vss XCK LP FR DATA 4 PS:Y CS
(b) When the L/R register set "H" level
Top data Y0 EIO1 Y95 EIO2 Y0 EIO1 Y95 EIO2 Y0 EIO1
Last data Y95 EIO2
DI0~DI3
DI0~DI3
DI0~DI3
XCK
XCK
XCK
FR
FR
FR
LP
LP
LP
Vss XCK LP FR DATA 4 PS:Y CS
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8.2.4 Timing chart of 4-device cascade connection of segment drivers
FR
LP
XCK
TOP DATA DI3 - DI0 n* 1 2 n* 1 2 n* 1 2 n* 1 2 n* 1
LAST DATA 2
device A
device B
device C
device D
EI (device A)
EO (device A)
EO (device B)
EO (device C)
*n = 24 in 4-bit parallel input mode *n = 96 in serial input mode
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8.2.5 Connection examples for signal common drivers ( 96 common)
(c) When the L/R register set "L" level
The first Y95 EIO2 Y0 EIO1
DI0~DI3
XCK
FR
LP
FLM Vss LP FR Vss 4 PS:Y CS
(d) When the L/R register set "H" level
The first Y0 EIO1 Y95 EIO2
DI0~DI3
XCK
FR
LP
FLM Vss LP FR Vss 4 PS:Y CS
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8.2.6 Connection examples for plural common/segment (mix mode) drivers The mix mode is 1/16, 1/32, 1/48, 1/64, 1/80, 1/96 duty mode
(e) When the L/R register set "L" level
Data flow COM Y95 EIO2 SEG Yx+1 Yx Y0 EIO1 Y95 EIO2 SEG Y0 EIO1
DI0~DI3
DI0~DI3
XCK
XCK
FR
FR
LP
LP
FLM XCK LP FR DATA 4 PS:Y CS
(f)
When the L/R register set "H" level
Data flow COM Y0 EIO1 Yx SEG Yx+1 Y95 EIO2 Y0 EIO1 SEG Y95 EIO2
DI0~DI3
DI0~DI3
XCK
XCK
FR
FR
LP
LP
FLM XCK LP FR DATA 4 PS:Y CS
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9. PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so a high current that may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating may permanently damage it. The details are as follows, When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on XDISPOFF function. After that, cancel the XDISPOFF function after the LCD drive power supply has become stable.
Furthermore, when disconnecting the power, set the LCD drive output pins to level VSS on XDISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here
disconnect the logic system power after disconnecting the LCD drive power
VDD VDD VSS
VDD XDISPOFF VSS V0 V0 VSS
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10. HARDWARE CIRCUIT DESCRIPTION
The LCD Data Bus Interface
There are two kinds of interfaces for LCD data bus. One is 4-bit parallel data interface and the other is the serial interface. These two kinds of interfaces are selected by setting the P/S bit in the "Interface Control Selection" register, and see detail in the Table 1. D1~D3 on data bus must be fixed to ground when "1" for P/S bit is selected. START AND STOP CONDITIONS Both SID and SCLK must be kept at high when the bus
The Command Registers Setting Interface
The command registers for ST8009 is setting by serial interface, SCLK and SID. The timing of serial interface is shown in Fig.1 and Fig.2 Both SCLK and SID must be connected to pull-up resistors.
Table 1
P/S 1 0 Data Bus Mode Parallel Interface(D0~D3) Serial Interface (D0)
is not busy, and if SCLK is high at the falling edge of SID, ST8009 will enter the "Start Condition" for beginning to receive command. Otherwise, if SCLK is high at the rising edge of SID, ST8009 will enter the "Stop Condition" for finishing command transfer. The start and stop conditions are illustrated in Fig.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
SID
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Fig .1 Write command timing diagram
SDI SCLK
data line stable; data valid change of data allowed
Fig .2 Bit transfer
SDI SCLK S
START con dition
Fig .3 Definition of START and STOP conditions
P
STOP con dition
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The Power Supply Circuits
The power supply circuits generate the LCD bias for LCD drive. The power supply circuits are consisted of booster circuit, voltage regulator circuit, and voltage follower circuit. They only enabled when ST8009 is in common mode or common/segment mode. The power supply circuits can turn on or turn off the booster circuit, voltage regulator circuit, and voltage follower circuit independently by setting the "Power Control Set" register. Table 2 shows the detail for "Power Control Set" register.
Table2 Bit
D2 D2 D2 D1 D1 D1 D0 D0 D0
Function
Booster circuit control bit Voltage regulator circuit control bit (V/R circuit) Voltage follower circuit control bit (V/F circuit)
Status "1"
ON ON ON
"0"
OFF OFF OFF
The Step-up Voltage Circuits
By applying the step-up voltage circuit for ST8009, it is possible to produce a voltage which is 2, 3, 4, 5, or 6 times of VDD level. Here must notice that the 6X step-up application only support for VDD less than +2.7V, or the ST8009 may be damaged permanently by VOUT over +16V. By the same reason, the 5X step-up application only can be used when VDD inside +3.3V, and the 4X step-up application circuit only can be used when VDD inside +4V. If the voltage of VOUT which is generated by ST8009 internal booster circuit is almost over absolute maximum voltage( +16V ) , we suggest using the external voltage regulator to stabilize the VDD power, or the VOUT may be over the absolute maximum voltage( +16V ) when the VDD power is not stable.
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ST8009
* The VDD voltage range must be set properly so that the voltage on VOUT does not exceed the absolute maximum rated value.
The Voltage Regulator Circuit
There is a high-accuracy digital to analog circuit with 64-level electronic volume function and variable resistor inside ST8009. Systems can be constructed without high-accuracy voltage regulator circuit, if the voltage on VOUT terminal is much less than absolute maximum voltage.(VREG thermal gradients approximate -0.15%/C). Through using the V0 voltage regulator internal resistors and the electronic volume function, the liquid crystal power supply voltage V0 can be controlled by command register alone (without adding any external resistors), and making it possible to adjust the liquid crystal display brightness. The V0 voltage can be calculated using following equation over the range where | V0 | < | VOUT| VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25C is as shown in Table 4.
ST8009
ST8009
ST8009
Fig 4.2
V 0 = 1 + = 1 +
Rb * V EV Ra Rb * 1 - * V REG Ra 200
V0 Internal Rb
Q V EV = 1 - * V REG 200
Internal Ra
VEV (Construct voltage supply + electronic volume) Fig .5 VSS
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Part no. ST8009
Equipment Type
Internal Power Supply
Thermal Gradient
-0.15 %/C
VREG
2.1V
Table4
is set to one of the 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 5 shows the value for depending on the electronic volume register settings. Rb/Ra is the V0 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V0 voltage regulator internal resistor ratio set command. The Rb/Ra ratio assumes the values shown in Table 6 depending on the 3-bit data settings in the VDD voltage regulator internal resistor ratio register.
D5
0 0 0
D4
0 0 0
Table5 D3 D2
0 0 0 0 0 0
D1
0 0 1
D0
0 1 0
63 62 61 : : : : 1 1 1 1 0 1 2 1 1 1 1 1 0 1 1 1 1 1 1 1 0 V0 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value)
Table6
Register D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 ST8009 (1) -0.15 %/C 5.0 5.22 5.48 5.76 6.07 6.42 6.81 7.25
V0 16 15 14 13 12 11 10 9 8 7 6
1
Ta=25 and booster off, regulator, follower on, VOUT=15.6V, VDD=3.3V
0 1 2 3 4 5 6 7
V0 Voltage Regulator Internal Resistor Ratio set D2, D1, and D0
4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Electronic Volume Register Set
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ST8009
The LCD Voltage Generator Circuit
The V0 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3 and V4 to the liquid crystal drive circuit.
VDD Externa l power supply VDD VOUT CAP3+ CAP1CAP1+ CAP4+ CAP5+
2. When only the voltage regulator circuit and V/F circuit are used
Reference Circuit Examples
1. When the step-up circuit, voltage regulating circuit and V/F circuit are used. (Example with 4x setup-up)
C2 C2 VDD C1 VDD VOUT CAP3+ CAP1CAP1+ CAP2CAP2+ ST8009 CAP4+ CAP5+ VOUT VSS C2 C2 C2
CAP2CAP2+ ST8009
V0 V1 V2 V3 V4 VSS
C1 C1
C1
3. When only the V/F circuit is used
C2 C2 C2 C2 C2 VSS
V0 V1 V2 V3 V4 VSS
VDD VDD VOUT CAP3+ CAP1CAP1+ CAP2CAP2+ CAP4+ CAP5+
ST8009
External power supply
V0
C2 C2 C2 C2 C2 VSS
V0 V1 V2 V3 V4 VSS
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ST8009 4. When the built-in power is not use * 1. Because the VR terminal input impedance is high, use short leads and shielded lines. * 2. C1 and C2 are determined by the size of the LCD
VDD VDD VOUT CAP3+ CAP1CAP1+ CAP2CAP2+ CAP4+ CAP5+
being driven. Select a value that can stabilize the liquid crystal drive voltage in the Table 7.
Item c1 c2
ST8009
Set value
1.0 to 4.7 0.1 to 4.7
units
uF uF
V0 V1 External power sullpy V2 V3 V4 VSS VSS
Table7
Following steps are the examples about how to determine the value for these capacitors: * Turn the voltage regulator circuit and voltage follower circuit on and supply a voltage to VOUT externally.
5. When the built-in power circuit is used to drive a liquid crystal panel with heavy load, it is recommended to connect an external resistor to stabilize potentials of V1, V2, V3 and V4 which are output from the built-in voltage follower.
V0
* Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes), and select a value for C2 that can stabilize the liquid crystal drive voltages (V1 to V4). Note that all C2 capacitors must have the same capacitance value. * Next, turn on all the power supply circuits to determine C1
R4
R4
C2
V1
ST8009
V2 V3 V4
R4
R4
VSS
VSS
R4 : 100K ~ 1M, it is recommended to set an optimum resistance value for R4 according to the quality of liquid crystal display and the drive waveform
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11. INSTRUCTION TABLE
Instruction
Interface control selection Software Reset Instruction Code D7 0 D6 0 D5 0 D4 0 D3 0 D2 M D1 LR D0 PS
Description
Interface selection and set
0
0
0
1
0
0
0
RST
Software reset, when set the register then the ST8009 will be reset The register can select the LCD duty numbers The register can select the LCD bias Set the power mode. The register
LCD Duty selection LCD Bias Set
0 0
0 0
1 1
0 1
0 0
DU2 B2
DU1 B1
DU0 B0
Power Controller Set
0
1
0
1
0
B
R
F
contain three power circuits can select (booster, regulator, follow)
Booster Frequency Set V0 Voltage Regulator Internal Resistor Ratio Set Electronic Volume Register Set
1
0
0
0
0
F2
F1
F0
Set the booster frequency
Select internal resistor ratio (Ra/Rb) 1 0 0 1 0 Rab2 Rab1 Rab0 mode
1
1
E5
E4
E3
E2
E1
E0
Set the V0 output voltage electronic volume register
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12. INSTRUCTION DESCRIPTION
The ST8009 identify the data bus signals by a combination between SID and SCLK signals.
Start bit
Interface Control D7 0 D6 0 D5 0 D4 0 D3 0 D2 M D1 LR D0 PS
Software reset
Stop bit
The register can control frame direction, common, segment, common/segment direction and serial or parallel (4-bits) input data Interface. M: Frame direction control bit When M=" Height", the internal frame direction and external frame direction are the same (normally). When M=" Low", the internal frame direction and external frame direction are adverse. LR: CS output direction control bit LR="H" LR="L" CS0 CS95 CS95 CS0 LCD Duty Selection D7 PS: Data Interface mode select control bit When PS="Low", the data input interface is serial When PS=" Height", the data input interface is parallel (4-bits) "LCD Duty Selection" register can set the duty for LCD display. Detail in the following column: DU2 Software Reset D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 RST 0 0 0 0 When RST="1" , do software reset action. Software reset need "Start bit" at the beginning to start the action, and also need "Stop bit" at the end to release the initializing state. It is different to other commands so can't set continuously with other commands. Note: Other commands can be set continuously with only one start bit at beginning and stop bit at end: 1 1 1 1 DU1 0 0 1 1 0 0 1 1 DU0 0 1 0 1 0 1 0 1 COM Num. 0 16 32 48 64 80 96 96 SEG Num. 96 80 64 48 32 16 0 0 0 D6 0 D5 1 D4 0 D3 0 D2 DU2 D1 DU1 D0 DU0
Start bit
Other commands
Stop bit
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ST8009 LCD Bias Set D7 0 D6 0 D5 1 D4 1 D3 0 D2 B2 D1 B1 D0 B0 Booster Frequency Set D7 1 D6 0 D5 0 D4 0 D3 0 D2 F2 D1 F1 D0 F0
This register can select the voltage bias ratio which is required for the liquid crystal display. There are eight bias modes can be selected in ST8009. B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Bias select 1/4 1/5 1/6 1/7 1/8 1/9 1/10 1/11
This register can select one of the booster frequency in the following column: F2 0 0 0 0 1 1 1 1 F1 0 0 1 1 0 0 1 1 F0 0 1 0 1 0 1 0 1 Booster Frequency 1K 2K 3K 4K 5K 6K 7K 8K
V0 Voltage Regulator Internal Resistor Ratio Set Power Controller Set D7 0 D6 1 D5 0 D4 1 D3 0 D2 B D1 R D0 F D7 This register can enable or disable the power supply circuit in ST8009. See details in "The Power Supply Circuit". B 0 1 ----R --0 1 --F ---0 1 Status Booster circuit : off Booster circuit : on Regulator circuit : off Regulator circuit : on Follower circuit : off Follower circuit : on Rab2 0 0 0 0 1 1 1 1 Rab1 0 0 1 1 0 0 1 1 Rab0 0 1 0 1 0 1 0 1 Large Ra/Rb Ratio Small 1 D6 0 D5 0 D4 1 D3 0 D2 Rab2 D1 Rab1 D0 Rab0 This register can set the V0 voltage regulator internal resistor ratio.
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ST8009 Electronic Volume Register Set D7 1 D6 1 D5 E5 D4 E4 D3 E3 D2 E2 D1 E1 D0 E0 Initializing by internal Reset circuit An internal reset circuit initializes the ST8009 after software reset has set. Following are the initial value of command registers after software reset: This register can control the V0 in 64 steps of voltage level to adjust the brightness of the liquid crystal display. This register had better set under 0xE0. Because when the value of this register set over 0xE0, the V0 will be inaccuracy. The inaccurate value of V0 will exceed in 0.1V when this register set over 0xE0. By this limit, if we need a higher voltage for V0, we had better set the bigger value for "V0 Voltage Regulator Internal Resistor Ratio" register, and then adjust the value of "Electronic Volume" register to produce the proper voltage for V0 terminal. E5 0 0 0 E4 0 0 0 E3 0 0 0 E2 0 0 0 E1 0 0 1 E0 0 1 0 Ra/Rb Ratio Small 1. Interface control selection FR: 0 LR: 0 PS: 1 2. LCD Duty selection The segment mode (96 segments) is selected by default. 3. LCD Bias Set 1/4 bias is selected by default. 4. Power Controller Set All the power circuits (booster, regulator and follower) will be turned off by default. 5. Booster Frequency Set Volume is 1 0 0 by default 6. V0 Voltage Regulator Internal Resistor Ratio Set Volume is 1 0 0 by default 7. Electronic Volume Register Set Volume is 1 0 0 0 0 0 by default 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 Large
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ST8009
Initial Flow
Software reset
Power on Flow
Display off
Interface control selection
Power controller Set BFR turn on
LCD Duty Set
EV set
LCD Bias Set
Wait 10ms
Power controller Set
Display on
EV Set
Power off Flow
Display on
Power controller Set B F R turn off
W ait 10ms
Display off
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13. ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage (1) SYMBOL VDD V1 Supply voltage (2) V2 V3 V4 Input voltage Storage temperature NOTES: 1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to VSS (0 V). VI TSTG APPLICABLE PINS VDD V1 V2 V3 V4 D14-DI0, XCK, FR, EIO1, EIO2, XDISPOFF RATING 2.5~5.5 VDD +10~ VDD +0.3 VDD +10~ VDD +0.3 -0.3~ VSS +10 -0.3~ VSS +10 -0.3 to VDD +0.3 -45 to +125 V V V C 1,2 UNIT V V NOTE
14. RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage (1) Supply voltage (2) Operating temperature NOTES: 1. The applicable voltage on any pin with respect to VSS (0 V). 2. Ensure that voltages are set such that V0 V1 V2 V3 V4 VSS. SYMBOL VDD V0 TOPR APPLICABLE PINS VDD V0 MIN. +2.5 +5.0 -20 TYP. MAX. +5.5 +16.0 +85 UNIT NOTE V V C 1, 2
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15. ELECTRICAL CHARACTERISTICS
15.1 DC Characteristics (Segment Mode) PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current (VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 to +85C) SYMBOL VIL VIH VOL VOH ILIL ILIH Output resistance Standby current Supply current (1) (Non-selection) Supply current (2) (Selection) Supply current (3) RON ISTB IDD1 IOL = +0.4 mA IOH = -0.4 mA VI = VSS VI = VDD |VON| =0.5V V0 = 16V DI7-DI0, XCK, LP, FR, EIO1, EIO2,XDISPOFF CS0-CS95 VSS VDD 1.0 CONDITIONS APPLICABLE PINS DI7-DI0, XCK, FR, EIO1, EIO2,XDISPOFF EIO1, EIO2 VDD-0.4 -10 +10 1.5 5.0 2.0 0.8VDD +0.4 MIN. TYP. MAX. UNIT NOTE 0.2VDD V V V V A A k A mA 1 2
IDD2 I0
VDD V0
7.0 0.9
mA mA
3 4
NOTES: 1. VDD = +5.0 V, V0 = +16.0 V, VI = VSS. 2. VDD = +5.0 V, V0 = +16.0 V, fXCK = 8 MHz, no-load, El = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +5.0 V, V0 = +16.0 V, fXCK = 8MHz, fLP = 19.2 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (4-bit parallel input mode).
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(Common Mode)
(VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = +5.0 to +16.0 V, TOPR = -20 to +85 C)
PARAMETER
Input "Low" voltage Input "High" voltage
SYMBOL
VIL VIH
CONDITIONS
APPLICABL E PINS
DI4-DI0, XCK, FR, EIO1, EIO2, XDISPOFF
MIN. TYP. MAX. UNIT NOTE
0.2VDD 0.8VDD +0.4 VDD-0.4 V V
Output "Low" voltage Output "High" voltage
VOL VOH
IOL = +0.4 mA IOH = -0.4 mA
EIO1, EIO2 DI4-DI0, XCK, FR, P/S,
V V
Input leakage current
ILIL
VI = VSS
EIO1, EIO2, XDISPOFF
-10.0
A
ILIH Input pull-down current Output resistance Standby current Supply current (1) Supply current (2) RON ISPD IDD I0 IPD
VI = VDD VI = VDD |VON|=0.5V V0 = 16V
DI4-DI0,FR,XDISPOFF XCK, EIO1, EIO2
+10.0 100
A A
CS0-CS95 VSS VDD V0
1.0
1.5 5.0 80 130
k A A A 1 2 2
NOTES: 1. VDD = +5.0 V, V0 = +16.0 V, VI = VSS 2. VDD = +5.0 V, V0 = +16.0 V, fLP =19.2 kHz, fFR = 80 Hz, 1/96 duty operation, no-load.
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15.2 AC Characteristics
(Segment Mode 1) PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Latch pulse fall to shift clock rise time Enable setup time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) (VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 5.0 to +16.0 V, TOPR = -20 10+85 C) SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tLSW tS tR tF tSD tWDL tD tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 78 1.2 1.2 CONDITIONS tR,tF 11ns MIN 125 51 51 30 40 51 0 51 51 51 50 36 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s 2 2 NOTE 1
NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
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ST8009 (Segment Mode 2) (VSS = 0 V, VDD = +5.00.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 to +85 C) SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tLSW tS tR tF tSD tWDL tD tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 41 1.2 1.2 CONDITIONS tR,tF 10ns MIN. 66 23 23 15 23 30 0 50 30 30 50 15 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s 2 2 NOTE 1
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Latch pulse fall to shift clock rise time Enable setup time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3)
NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
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ST8009 (Segment Mode 3) (VSS = 0 V, VDD = +3.0 to +4.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 10+85 C) SYMBOL tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tLSW tS tR tF tSD tWDL tD tPD1, tPD2 tPD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 57 1.2 1.2 CONDITIONS tR,tF 10ns MIN. 82 28 28 20 23 30 0 51 30 30 50 15 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s 2 2 NOTE 1
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Latch pulse fall to shift clock rise time Enable setup time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3)
NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Common Mode)
(VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 10+85 C)
PARAMETER
Shift clock period Shift clock "H" pulse width
SYMBOL
tWLP tWLPH
CONDITIONS
tR, tF 20ns VDD =5 0.5V VDD =2.5~4.5V
MIN
250 15 30 30 50
TYP
MAX
UNIT
ns ns
Data setup time Data hold time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3)
tSU tH tR tF tSD tWDL tDL tPD1,tPD2 tPD3 CL=10pF CL=10pF CL=10pF
ns ns 50 50 ns ns ns us 200 1.2 1.2 ns us us
100 1.2
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15.3 Timing Chart of Segment Mode
tWLPH
LP
tLD tLS tSL tLH tWCKH tWCKL
XCK
tR tWCK tF tDS tDH
DI4 - DI0
LAST DATA
TOP DATA
tWDL
tSD
DISPOFF
FR tPD1 LP tPD2 DISPOFF tPD3 Y1 - Y120
Timing Characteristics (3)
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ST8009 (Common Mode) (VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = +5.0 to +16.0 V, TOPR = -20 to +85 C) SYMBOL tWLP tWLPH tSU tH tR tF tSD tWDL tDL tPD1, t PD2 t PD3 CL = 15 pF CL = 15 pF CL = 15 pF 100 1.2 200 1.2 1.2 CONDITIONS tR,tF 20ns VDD = +5.0 0.5V VDD = +2.5+ 4.5V Data setup time Data hold time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) MIN. 250 15 30 30 50 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns s ns s s
PARAMETER Shift clock period Shift clock "H" pulse width
15.4 Timing Chart of Common Mode
tWLP
LP
tR
tWLPH tSU
tF tH
EIO2
tDL
EIO1
tWDL
DISPOFF
tSD
FR tPD1 LP tPD2 DISPOFF tPD3 Y1 - Y120
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15.5 Application Timing Block:
Example 160X80
Frame and Lp falling edge (or rising edge) must >10ns
15.6 Parallel vs. Serial Interface Diagram:
S
S
S
S
S
S
S
S
S15
S15
S15
S16
1
2
3
4
5
6
7
8
15
15
15
16
LP
D3
1
5
9
1
14
14
15
15
1
5
9
D2
2
6
1
1
14
15
15
15
2
6
1
D1
3
7
1
1
14
15
15
15
3
7
1
D0
4
8
1
1
14
15
15
16
4
8
1
D0
1
2
3
4
5
6
7
8
15
15
15
16
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16. Application Circuit
(a) When only use one ST8009 in mix mode (64X32)
(b) When use one ST8009 and two ST8011 (240X96)
240X96 DOT LCD PANEL
CS0 ~ CS95
SEG0 ~ SEG119 D0 ~ D3 XCK
SEG0 ~ SEG119
VDD LP
Vss SID SCLK FR FLM XDISPOFF
VDD LP1 XDISPOFF LP2 EIO1 XCK 4 DI0 ~ DI3 EIO2 Vss SID SCLK FR
4
VDD XDISPOFF LP EIO1 XCK EIO2 DI0 ~ DI3 Vss FR
4
VDD XDISPOFF LP EIO1 XCK EIO2 DI0 ~ DI3 Vss FR
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ST8009
(c) When use one ST8009 and two ST8008 (160X96)
(d) When use one ST8009 and one ST8008 (112X64)
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ST8009 ST8009 Serial Specification Revision History ST8009 Serial Specification Revision History Version 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.0 1.1 Date 2003/12/25 2004/1/28 2004/3/11 2004/4/5 2004/5/20 2004/09/08 2005/02/14 2005/04/19 2005/05/12 2006/11/01 Description Preliminary version Modify registers Modify registers Add application timing block disgram Add initial flow Define timing of segment Mode. P41~P44 Revise graph of ST8008,ST8011(SID, SCLK) Modify stand-by current to 5uA (max) New version update Fixing the XCS error in the fig.1
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix.
V1.1
43/43
2006/11/1

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