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| VIV0105THJ PRELIMINARY DATASHEET S C NRTL US VTM DC to DC Voltage Transformation TM FEATURES * 40 Vdc - 5 Vdc 20 A Voltage Transformation Module - Operating from standard 48 V or 24 V PRMs * High efficiency (>94%) reduces system power consumption * High density (133 A/in3) * "Half Chip" V*I Chip package enables surface mount, low impedance interconnect to system board * Contains built-in protection features: Overvoltage lockout Overcurrent Short circuit Over temperature protection * Provides enable/disable control, internal temperature monitoring, current monitoring * ZVS/ZCS resonant Sine Amplitude Converter topology * Less than 50C temperature rise at full load in typical applications TYPICAL APPLICATION DESCRIPTION The V*I Chip Voltage Transformation Module is a high efficiency (>94%) Sine Amplitude Converter (SAC)TM operating from a 26 to 48 Vdc primary bus to deliver an isolated 5 V secondary. The Sine Amplitude Converter offers a low AC impedance beyond the bandwidth of most downstream regulators, which means that capacitance normally at the load can be located at the input to the Sine Amplitude Converter. Since the K factor of the VIV0105THJ is 1/8, that capacitance value can be reduced by a factor of 64x, resulting in savings of board area, materials and total system cost. The VIV0105THJ is provided in a V*I Chip package compatible with standard pick-and-place and surface mount assembly processes. The V*I Chip package provides flexible thermal management through its low junction-to-case and junction-toboard thermal resistance. With high conversion efficiency the VIV0105THJ increases overall system efficiency and lowers operating costs compared to conventional approaches. The VIV0105THJ enables the utilization of Factorized Power Architecture providing efficiency and size benefits by lowering conversion and distribution losses and promoting high density point of load conversion. * High End Computing Systems * Automated Test Equipment * Telecom Base Stations * High Density Power Supplies * Communication Systems TYPICAL APPLICATION PR PC TM IL VC SG OS CD VIN = 26 - 48 V VOUT = 3.25 - 6.00 V (NO LOAD) IOUT = 20 A(NOM) K = 1/8 PRM +Out +In IM TM VC PC -In +Out +In VIN -In -Out VTM -Out L O A D V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 1 of 16 VIV0105THJ PRELIMINARY DATASHEET ABSOLUTE MAXIMUM RATINGS +IN to -IN . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 Vdc - +53 Vdc PC to -IN . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc - +20 Vdc TM to -IN . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc - +7.0 Vdc +IN/-IN to +OUT/-OUT . . . . . . . . . . . . . . . . . . . 2250 V (Hi Pot) +IN/-IN to +OUT/-OUT . . . . . . . . . . . . . . . . . . . . 60 V (working) +OUT to -OUT . . . . . . . . . . . . . . . . . . . . . . -1.0 Vdc - +10 Vdc Temperature during reflow . . . . . . . . . . . . . . . . . 225C (MSL5) PACKAGE ORDERING INFORMATION 4 A 3 2 1 CONTROL PIN SPECIFICATIONS See section 5.0 for further application details and guidelines. PC (V*I Chip VTM Primary Control) The PC pin can enable and disable the VTM. When held below 2.0 V the VTM will be disabled. When allowed to float with an impedance to -IN of greater than 60 k the module will start. The PC pin is capable of being driven high either by an external logic signal or internal pull up to 5 V (operating). TM (V*I Chip VTM Temperature Monitor) The TM pin monitors the internal temperature of the VTM within an accuracy of 5 C. It has a room temperature setpoint of ~3.0 V and an approximate gain of 10 mV/C. It can source up to 100 A and may also be used as a "Power Good" flag to verify that the VTM is operating. IM (V*I Chip Current Monitor) The IM pin provides a DC analog voltage proportional to the output current of the VTM. This voltage varies between 0.3 and 2.1 V and represents VTM output current within 25% of the actual value under all operating line temperature conditions between 50% and 100% load. VC (VTM Control) In typical applications the VC pin of the VTM is tied to the VC pin of the PRMTM Regulator. In these applications the PRM provides a temporary VC voltage during startup synchronizing the output rise of the two devices. In addition, the VC port provides feedback to the PRM on to its output resistance through an internal resistor. For applications which do not use a PRM, a voltage between 12 V and 17 V must be applied to VC in order to enable the VTM. +In +Out B C D J K E F G H -Out L M IM TM VC PC -In Bottom View Signal Name +In -In IM TM VC PC +Out -Out Designation A1-B1, A2-B2 L1-M1, L2-M2 E1 F2 G1 H2 A3-D3, A4-D4 J3-M3, J4-M4 PART NUMBER VIV0105THJ VIV0105MHJ DESCRIPTION -40C - 125C TJ, J lead -55C - 125C TJ, J lead V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 2 of 16 VIV0105THJ PRELIMINARY DATASHEET 1.0 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40C < TJ < 125C (T-Grade); All other specifications are at TJ = 25C unless otherwise noted ATTRIBUTE Voltage range dV/dt No load power dissipation Inrush Current Peak DC Input Current K Factor SYMBOL VIN dVIN/dt PNL IINR-P IIN-DC K IOUT-AVG IOUT-PK POUT-AVG VOUT AMB HOT 20% ROUT-AMB ROUT-HOT ROUT-COLD COUT FSW FSW-RP VOUT-PP COUT = 0 f, IOUT = 20 A VIN = 42.4 V, 20 MHz BW, Section 8.0 1/8 20 30 132 6.12 93.7 92 14 17.3 12.3 18 22.5 16 1000 1.6 3.2 1.75 3.5 135 1.9 3.8 350 CONDITIONS / NOTES No external VC applied VIN = 42.4 V VIN = 26 V to 48 V VC enable, VIN = 42.4 V COUT = 1,000 F, IOUT = 20 A MIN 26 1.85 4.8 TYP MAX 48 1 2.6 3.6 12 2.7 UNIT Vdc V/s W W A A V/V A A W V % % % m m m F MHz MHz mV () VOUT VIN Output Current(average) Output Current(Peak) Output Power (average) Output Voltage Efficiency (Ambient) Efficiency (Hot) Efficiency (Over load range) Output Resistance (Ambient) Output Resistance (Hot) Output Resistance (Cold) Load Capacitance Switching Frequency Ripple Frequency Output Voltage Ripple PC PC Voltage (Operating) PC Voltage (Enable) PC Voltage (Disable) PC Source Current (Startup) PC Source Current (Operating) PC Resistance (Internal) PC Resistance (External) PC Capacitance (Internal) PC Disable Time PC Fault Response Time TM TM Voltage (Ambient) TM Gain TM Source Current TM Resistance (Internal) TM Capacitance (External) TPEAK <10 ms, IOUT_AVG 20 A IOUT_AVG 20 A Section 3.0 VIN = 42.4 V, TJ =25C, IOUT = 20 A VIN = 26 V to 48 V, TJ = 25C IOUT = 20 A VIN = 42.4 V, TJ = 100 C, IOUT = 20 A 4 A < IOUT < 20 A TJ = 25C TJ = 125C TJ = -40C VTM Standalone Operation. VIN pre-applied, VC enable 2.73 92.2 88.5 90.5 85 10 12.1 8.6 VPC VPC-EN VPC-DIS IPC-EN IPC-OP RPC-INT RPC-EXT CPC-INT TPC-DIS TFR-PC 4.7 2 50 Internal pull down resistor Connected to -IN. Unit will not start if below minimum value Section 5.0 From fault to PC = 2.0 V 50 60 5 2.5 100 150 5.3 3 2.0 300 2 400 V V V A mA k k 588 4 100 pF s s VTM-AMB ATM ITM RTM-INT CTM-EXT TJ = 27C 2.95 3 10 40 3.05 100 50 50 Internal pull down resistor 25 V mV/C A k pF V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 3 of 16 VIV0105THJ PRELIMINARY DATASHEET 1.0 ELECTRICAL CHARACTERISTICS (CONT.) Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40C < TJ < 125C (T-Grade); All other specifications are at TJ = 25C unless otherwise noted ATTRIBUTE TM (CONT.) TM Voltage Ripple TM Fault Response Time IM IM Voltage (No Load) IM Voltage (50%) IM Voltage (Full Load) IM Gain IM Resistance (External) VC External VC Voltage VC Slew Rate VC Current Draw (steady-state) VC Inrush Current Internal VC Capacitance Output Turn-On Delay (VC) VC to PC Delay VC Application Time VC Internal Resistor PROTECTION Positive Going OVLO UV Turn-Off Output Overcurrent Trip Short Circuit Protection Trip Current Thermal Shutdown Setpoint Output Overcurrent Response Time Constant Short Circuit Protection Response Time Overvoltage Lockout Response Time Constant GENERAL SPECIFICATION Isolation Voltage (Hi-Pot) Working Voltage (IN - OUT) Isolation Capacitance Isolation Resistance MTBF Agency Approvals / Standards VVC-EXT dVC/dt IVC IINR-VC CVC-INT TON TVC-PC TVC-AP RVC-INT Required for startup, and operation below 26 V. See Section 5.0 Required for proper startup VC = 14 V, Vin = 0 VC = 17 V, dVC/dt = 0.25 V/s VC = 0 V VIN pre-applied, PC floating, VC enable, CPC = 0 F, COUT = 1,000 F VC = 10.5 V to PC high, VIN = 0 V, dVC/dt = 0.25 V/s Maximum application time of VC 12 0.0025 85 2.2 500 10 4.64 25 20 17 0.25 150 750 V V/s mA mA F s s ms k VTM-PP TFR-TM CTM = 0 F, VIN = 42.4 V, IOUT = 20 A, 20 MHz BW From fault to TM = 1.5 V 120 10 200 mV s SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT VIM-NL VIM-50% VIM-FL AIM RIM-EXT TJ = 25C, VIN = 42.4 V, IOUT = 0 TJ = 25C, VIN = 42.4 V, IOUT = 10 A TJ = 25C, VIN = 42.4 V, IOUT = 20 A TJ = 25C, VIN = 42.4 V, IOUT > 10 A 2.5 0.5 1.0 1.58 60 V V V mV/A M VIN_OVLO+ VIN_UVTO IOCP ISCP TJ-OTP TOCP TSCP TOVLO 48.6 No external VC applied, IOUT = 20 A 20.2 30 125 Effective internal RC filter From detecton to cessation of switching Effective internal RC filter 50.8 22 42 45 130 4.5 1 2.7 53 26 60 60 135 V V A A C ms s s VHIPOT VIN-OUT CIN-OUT RIN-OUT 2,250 Unpowered Unit MIL HDBK 217F, 25C, Ground Benign cTUVus CE Mark ROHS 6 of 6 1350 10 1750 4.5 60 2150 VDC V pF M MHrs V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 4 of 16 VIV0105THJ No Load Power Dissipation vs. Line No Load Power Dissipation (W) 3.5 3 2.5 2 1.5 1 26 28 30 32 34 36 38 40 42 44 46 48 PRELIMINARY DATASHEET Full Load Efficiency vs. Case Temperature 95 Full Load Efficiency (%) 94 93 92 91 90 89 88 87 -40 -20 0 20 40 60 80 100 Input Voltage (V) TCASE: -40C 25C 100C VIN : Case Temperature (C) 26 V 40 V 48 V Figure 1 - No load power dissipation vs. VIN; TCASE Figure 2 - Full load efficiency vs. temperature; VIN Efficiency & Power Dissipation -40C Case 96 94 92 90 88 86 84 82 80 78 76 74 72 70 Efficiency & Power Dissipation 25C Case 13 12 11 10 9 8 7 6 5 4 3 2 1 96 94 92 90 88 86 84 82 80 78 76 74 72 70 0 2 Power Dissipation (W) PD PD 0 2 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20 Output Current (A) VIN: 26 V 40 V 48 V 26 V 40 V 48 V VIN: 26 V Output Current (A) 40 V 48 V 26 V 40 V 48 V Figure 3a - Efficiency and power dissipation at -40C (case); VIN Figure 3b - Efficiency and power dissipation at 25C (case); VIN Efficiency & Power Dissipation 100C Case 96 94 92 90 88 86 84 82 80 78 76 74 72 70 0 2 ROUT vs. Case Temperature 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18 Power Dissipation (W) 17 16 Efficiency (%) Rout (m) 15 14 13 12 11 10 -40 -20 0 20 40 60 80 100 PD 4 6 8 10 12 14 16 18 20 Output Current (A) VIN: 26 V 40 V 48 V 26 V 40 V 48 V Case Temperature (C) I OUT : 2A 20 A Figure 3c - Efficiency and power dissipation at 100C (case); VIN Figure 4 - ROUT vs. temperature vs. IOUT V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 5 of 16 Power Dissipation (W) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Efficiency (%) Efficiency (%) VIV0105THJ PRELIMINARY DATASHEET Ripple vs. Load 275 250 Ripple (mV pk-pk) 225 200 175 150 125 100 0 2 4 6 8 10 12 14 16 18 20 Load Current (A) Vpk-pk (mV) Figure 5 - Full load ripple, 100 F CIN; No external COUT Figure 6 - Vripple vs. IOUT ; 42 VIN, no external output capacitance 2.25 2.00 1.75 1.50 IM Voltage vs. Load 40 VIN 2 1.75 1.5 1.25 IM Voltage vs. Load 25C Case IM (V) 1.25 1.00 0.75 0.50 0.25 0.00 0 2 4 6 8 10 12 14 16 18 20 IM (V) 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 16 18 20 Load Current (A) TCASE: -40C 25C 100C VIN : Load Current (A) 26 V 40 V 48 V Figure 7 - IM voltage vs. load; 40 VIN Figure 8 - IM voltage vs. load; 25C Case Full Load IM Voltage vs. TCASE & Line 2.25 2.00 1.75 1.50 1.25 1.00 -40 -20 0 20 40 60 80 100 IM (V) Case Temperature (C) VIN : 26 V 40 V 48 V Figure 9 - Full load IM voltage vs. TCASE & line Figure 10 - Start up from application of VC; VIN pre-applied COUT = 1,000 F V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 6 of 16 VIV0105THJ PRELIMINARY DATASHEET Figure 11 - Start up from application of VIN; VC pre-applied COUT = 1,000 F Figure 12 - 0 - 20 A transient response; CIN = 100 F, no external COUT Figure 13 - 20 A - 0 A transient response; CIN = 100 F, no external COUT Figure 14 - PC disable waveform; RLOAD = 0.25 , COUT = 1,000 F V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 7 of 16 VIV0105THJ PRELIMINARY DATASHEET 2.0 PACKAGE/MECHANICAL SPECIFICATIONS All specifications are at TJ =25C unless otherwise noted. See associated figures for general trend data. ATTRIBUTE Length Width Height Volume Footprint Current Density Weight Lead Finish Operating Temperature (Junction) Storage Temperature Thermal Impedance Thermal Capacity Peak Compressive Force Applied to Case (Z-axis) Moisture Sensitivity Level ESD Rating Peak Temperature During Reflow Peak Time Above 183C Peak Heating Rate During Reflow Peak Cooling Rate Post Reflow [a] [b] SYMBOL L W H Vol F CD W CONDITIONS / NOTES MIN 21.7 / 0.85 16.4 / 0.64 6.48 / 0.255 TYP 22.0 / 0.87 16.5 / 0.65 6.73 / 0.265 2.44 / 0.150 3.6 / 0.56 133 0.28/8 MAX 22.3 / 0.88 16.6 / 0.66 6.98 / 0.275 UNIT mm/in mm/in mm/in cm3/in3 cm2/in2 A/in3 oz/g m m m C C C C C/W Ws/C lbs VDC VDC C s C/s C/s No Heatsink No Heatsink No Heatsink Nickel Palladium Gold VIV0105THJ (T-Grade) VIV0105MHJ (M-Grade) VIV0105THJ (T-Grade) VIV0105MHJ (M-Grade) Junction to Case Supported by J-leads only 0.51 0.02 0.003 -40 -55 -40 -65 TJ TST OJC 2.03 0.15 0.05 125 125 125 125 2.7 5 2.5 3.0 ESDHBM ESDMM MSL Level 5 Human Body Model[a] Machine Model[b] 5 1500 400 225 150 3 6 1.5 1.5 JEDEC JESD 22-A114C.01 JEDED JESD 22-A115-A V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 8 of 16 VIV0105THJ 2.1 MECHANICAL DRAWING PRELIMINARY DATASHEET mm (inch) 2.2 RECOMMENDED LAND PATTERN 2.3 RECOMMENDED LAND PATTERN FOR PUSH PIN HEATSINK Notes: 1. Maintain 3.50 (0.138) Dia. keep-out zone free of copper, all PCB layers. 2. (A) minimum recommended pitch is 24.00 (0.945) this provides 7.50 (0.295) component edge-to-edge spacing, and 0.50 (0.020) clearance between Vicor heat sinks. (B) Minimum recommended pith is 25.50 (1.004). This provides 9.00 (0.354) component edge-to-edge spacing, and 2.00 (0.079) clearence between Vicor heat sinks. 3. V*I Chip land pattern shown for reference only, actual land pattern may differ. Dimensions from edges of land pattern to push-pin holes will be the same for all half size V*I Chips. 4. RoHS complient per CST-0001 latest revision. 5. Unless otherwise specified: Dimensions are mm (inches) tolerances are: x.x (x.xx) = 0.13 (0.01) x.xx (x.xxx) = 0.13 (0.005) 6. Plated through holes for grounding clips (33855) shown for reference, Heatsink orientation and device pitch will dictate final grounding solution. (0.080) (2) Pl. plated thru hole See note 6 21.00 (0.827) ( 10.50 ) (0.413) 22.52 (0.887) 21.00 (0.827) ( 10.50 ) (0.413) Dashed lines indicates half VIC position o 2.950.07 (0.1160.003) non-plated thru hole See note 1 7.63 ( 3.50 ) (0.300) (0.138) Dashed lines indicates half VIC position o 2.950.07 0.76 (0.030) (0.1160.003) non-plated thru hole See note 1 3.50 ) 7.63 ( (0.138) (0.300) 0.44 (0.017) 6.12 (0.241) ( 22.26 ) 7.00 (0.876) (0.276) ( 22.26 ) 7.00 (0.876) (0.276) o 2.03 2.76 (0.109) ( 15.48 ) (0.609) 24.00 (0.945) See Note 2A 2.76 (0.109) ( 15.48 ) (0.609) 25.50 (1.004) See note 2B (NO GROUNDING CLIPS) (WITH GROUNDING CLIPS) V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 9 of 16 VIV0105THJ PRELIMINARY DATASHEET 3.0 POWER, VOLTAGE, EFFICIENCY RELATIONSHIPS Because of the high frequency, fully resonant SAC topology, power dissipation and overall conversion efficiency of VTM converters can be estimated as shown below. Key relationships to be considered are the following: 1. Transfer Function a. No load condition VOUT = VIN * K Eq. 1 Figure 15 - Power transfer diagram P R OUT P NL INPUT POWER OUTPUT POWER Where K (transformer turns ratio) is constant for each part number b. Loaded condition VOUT = VIN * K - IOUT * ROUT Eq. 2 2. Dissipated Power The two main terms of power losses in the VTM module are: - No load power dissipation (PNL) defined as the power used to power up the module with an enabled power train at no load. - Resistive loss (ROUT) refers to the power loss across the VTM modeled as pure resistive impedance. ~ PDISSIPATED ~ PNL + PROUT Eq. 3 Therefore, with reference to the diagram shown in Figure 15 POUT = PIN - PDISSIPATED = PIN - PNL - PROUT Eq. 4 Notice that ROUT is temperature and input voltage dependent and PNL is temperature dependent (See Figure 15). The above relations can be combined to calculate the overall module efficiency: = POUT PIN = PIN - PNL - PROUT PIN = VIN * IIN - PNL - (IOUT)2 * ROUT VIN * IIN =1- ( PNL + (IOUT)2 * ROUT VIN * IIN ) Eq. 5 V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 10 of 16 4.0 OPERATING IOUT 6 7 Figure 16 - Timing diagram ISSP IOCP 1 b v i c o r p o w e r. c o m 23 4 5 d 8 a c e f g VC VVC-EXT VOVLO VIN NL 26 V VOUT TM VIV0105THJ VTM-AMB PC 5V 3V Notes: - Timing and voltage is not to scale - Error pulse width is load dependent V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 1. Initiated VC pulse 2. Controller start 3. VIN ramp up 4. VIN = VOVLO 5. VIN ramp down no VC pulse 6. Over current 7. Start up on short circuit 8. PC driven low a: VC slew rate (dVC/dt) b: Minimum VC pulse rate (see section 5) c: TOVLO d: TOCP e: Output turn on delay (TON) f: PC disable time (TPC-DIS) g: VC to PC delay (TVC-PC) PRELIMINARY DATASHEET Page 11 of 16 Rev. 1.5 9/2009 VIV0105THJ 5.0 USING THE CONTROL SIGNALS VC, PC, TM, IM The VTM Control VC pin is an input pin which powers the internal VCC circuitry when within the specified voltage range of 12 V to 17 V. This voltage is required in order for the VTM to start, and must be applied as long as the input is below 26 V. In order to ensure a proper start, the slew rate of the applied voltage must be within the specified range. Depending on the sequencing of the VC with respect to the input voltage, the behavior during startup will vary as follows: * Normal Operation (VC applied prior to VIN): In this case the controller is active prior to the input. When the input voltage is applied, the VTM output voltage will track the input allowing for a soft start (See Figure 11). If the VC voltage is removed prior to the input reaching 26 V, the VTM will shut down. * Stand Alone Operation (VC applied after VIN): In this case the VTM output will begin to rise upon the application of the VC voltage (See Figure 10). The output rate of rise will vary depending on the amount of output capacitance in order to limit the inrush current. In this mode of operation, the maximum output capacitance is 1,000 F due to limitations of the inrush limiting circuitry. Some additional notes on the using the VC pin: * In most applications, the VTM will be powered by an upstream PRM, in which case the PRM will provide a 10 ms VC pulse during startup. In these applications the VC pins of the PRM and VTM should be tied together. * The fault response of the VTM is latching. A positive edge on VC is required in order to restart the unit. * The VTM is not designed for continuous operation with VC applied. The VC voltage must be removed within 20 ms of application. * The VTM is capable of reverse operation. If a voltage is present at the output of the VTM which satisfies the condition VOUT > VIN * K at the time the VC voltage is applied, then energy will be transferred from secondary to primary. The input to output ratio of the VTM will be maintained. The VTM will continue to operate in reverse once the VC voltage is removed as long as the input and output voltages are within the specified range. The VIV0105THJ has not been qualified for continuous reverse operation. PRELIMINARY DATASHEET The Primary Control (PC) pin can be used to accomplish the following functions: * Delayed start: Upon the application of VC, the PC pin will source a constant 100 A current to the internal RC network. Adding an external capacitor will allow further delay in reaching the 2.5 V threshold for module start * Auxiliary voltage source: Once enabled in regular operational conditions (no fault), each VTM PC provides a regulated 5 V, 2 mA voltage source * Output Disable: PC pin can be actively pulled down in order to disable the module. Pull down impedance shall be lower than 850 . * Fault detection flag: The PC 5V voltage source is internally turned off as soon as a fault is detected. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of PC signal. It is important to notice that PC doesn't have current sink capability (only 150 k pull down is present), therefore in an array PC line will not be capable of disabling all the modules if a fault is detected on one of them. The Temperature Monitor (TM) pin provides a voltage proportional to the absolute temperature of the converter control IC. It can be used to accomplish the following functions: * Monitor the control IC temperature: The temperature in degrees Kelvin is equal to the voltage on the TM pin scaled by x100. (i.e. 3.0 V = 300K = 27C). It is important to remember that V*I Chips are multi-chip modules, whose temperature distribution greatly vary for each part number as well with input/output conditions, thermal management and environmental conditions. Therefore, TM cannot be used to thermally protect the system. * Fault detection flag: the TM voltage source is internally turned off as soon as a fault is detected. The Current Monitor (IM) pin provides a voltage proportional to the output current of the VTM. The voltage will vary between 0.3 V and 2.1 V over the output current range of the VTM (See Figure 7). The accuracy of the IM pin will be within 25% under all line and temperature conditions between 50% and 100% load. The accuracy of the pin can be improved using a predictive algorithm based on the input voltage and internal temperature. Please contact Applications Engineering for more information. V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 12 of 16 VIV0105THJ 6.0 FUSE SELECTION V*I Chips are not internally fused in order to provide flexibility in configuring power systems. Input line fusing of V*I Chips is recommended at system level, to provide thermal protection in case of catastrophic failure. The fuse shall be selected by closely matching system requirements with the following characteristics: * Current rating (usually greater than maximum VTM current) * Maximum voltage rating (usually greater than the maximum possible input voltage) * Ambient temperature * Nominal melting I2t 7.0 CURRENT SHARING The SAC topology bases its performance on efficient transfer of energy through a transformer, without the need of closed loop control. For this reason, the transfer characteristic can be approximated by an ideal transformer with some resistive drop and positive temperature coefficient. PRELIMINARY DATASHEET This type of characteristic is close to the impedance characteristic of a DC power distribution system, both in behavior (AC dynamic) and absolute value (DC dynamic). When connected in an array (with same K factor), the VTM module will inherently share the load current with parallel units, according to the equivalent impedance divider that the system implements from the power source to the point of load. It is important to notice that, when successfully started, VTMs are capable of bi-directional operations (reverse power transfer is enabled if the VTM input falls within its operating range and the VTM is otherwise enabled). In parallel arrays, because of the resistive behavior, circulating currents are never experienced, because of energy conservation law. General recommendations to achieve matched array impedances are (see also AN016 for further details): * to dedicate common copper planes within the PCB to deliver and return the current to the modules * to provide the PCB layout as symmetric as possible * to apply same input/output filters (if present) to each unit VIN ZIN_EQ1 VTM1 RO_1 ZOUT_EQ1 VOUT ZIN_EQ2 + - VTM2 RO_2 ZOUT_EQ2 DC Load ZIN_EQn VTMn RO_n ZOUT_EQn Figure 17 - VTM Array V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 13 of 16 VIV0105THJ 8.0 INPUT AND OUTPUT FILTER DESIGN A major advantage of a SAC systems versus conventional PWM converter is that the former does not require large functional filters. The resonant LC tank, operated at extreme high frequency, is amplitude modulated as function of input voltage and output current and efficiently transfers charge through the isolation transformer. A small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionality and is key to achieve power density. This paradigm shift requires system design to carefully evaluate external filters in order to: 1.Guarantee low source impedance: To take full advantage of the VTM dynamic response, the impedance presented to its input terminals must be low from DC to approximately 5 MHz. The connection of the V*I Chip to its power source should be implemented with minimal distribution inductance. If the interconnect inductance exceeds 100 nH, the input should be bypassed with a RC damper to retain low source impedance and stable operation. With an interconnect inductance of 200 nH, the RC damper may be as high as 47 F in series with 0.3 . A single electrolytic or equivalent low-Q capacitor may be used in place of the series RC bypass 2.Further reduce input and/or output voltage ripple without sacrificing dynamic response: Given the wide bandwidth of the VTM, the source response is generally the limiting factor in the overall system response. Anomalies in the response of the source will appear at the output of the VTM multiplied by its K factor. 3.Protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and cause failures: The V*I Chip input/output voltage ranges shall not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even during this condition, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it. A criterion for protection is the maximum amount of energy that the input or output switches can tolerate if avalanched. Owing to the wide bandwidth and low output impedance of the VTM, low frequency bypass capacitance and significant energy storage may be more densely and efficiently provided by adding capacitance at the input of the VTM. PRELIMINARY DATASHEET V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 14 of 16 Figure 18 - VTM block diagram v i c o r p o w e r. c o m C1 Q1 Enable Primary Stage & Resonant Tank +VIN CIN Power Transformer Buck Regulator Supply Primary Gate Drive Lr Cr +VOUT Gate Drive Supply Q2 C2 Q3 COUT Q4 VC -VOUT 10.5 V Synchronous Rectification 18 V Rptc -VIN Modulator Adaptive Soft Start Enable Differential primary current sensing Secondary Gate Drive VIN 100 uA OVLO UVLO 5V 2 mA Fast current limit Vref Over-Current Protection PC Pull-Up & Source IM 3 V max. 240 A max. VIV0105THJ 2.5 V 1.5 k Enable Fault Logic Slow current limit PC Enable V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 150 K 40 K VREF (125C) 2.5 V Over Temperature Protection Temperature dependent voltage source TM 560 pF PRELIMINARY DATASHEET Page 15 of 16 Rev. 1.5 9/2009 VIV0105THJ PRELIMINARY DATASHEET Warranty Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages. Vicor's comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor's Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Intellectual Property Notice Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.5 9/2009 Page 16 of 16 |
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