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19-5126; Rev 0; 1/10
TION KIT EVALUA BLE ILA AVA
Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver MAX4952B
General Description
The MAX4952B dual-channel redriver is designed to redrive one full lane of SAS or SATA signals up to 6.0Gbps and operates from a single +3.3V supply. The MAX4952B is designed for commercial SAS or SAS/SATA applications, such as servers. The MAX4952B features independent output boost and enhances signal integrity at the receiver by re-establishing full output levels. SAS and SATA out-of-band (OOB) signaling are supported using high-speed amplitude detection on the inputs and squelch on the corresponding outputs. Inputs and outputs are all terminated in 50I internally and exhibit excellent return loss. The MAX4952B is available in a small, 20-pin, 4.0mm x 4.0mm TQFN package with flow-through traces for ease of layout. This device is specified over the 0NC to +70NC operating temperature range.
S Single +3.3V Supply Operation S Low Power-Down Current (350A typ) for Power-
Features
Sensitive Applications
S Supports SAS I/II/III P 6.0Gbps S Excellent Return Loss
Exceeds SAS/SATA Return Loss Mask (Better Than 8dB Up to 3GHz)
S Supports SAS/SATA OOB-Level Signaling
Very Fast Entry and Exit Time of 5ns (Max) Programmable SAS/SATA Threshold
S Independent Output-Boost Selection
Two Levels: 0dB, 6dB
S On-Chip 50I Input/Output Terminations S In-Line Signal Traces for Flow-Through Layout S Space-Saving, 4.0mm x 4.0mm TQFN Package S ESD Protection on All Pins: 5.5kV (Human Body
Applications
Servers Data Storage
Model)
Ordering Information
PART MAX4952BCTP+ TEMP RANGE 0NC to +70NC PIN-PACKAGE 20 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed Pad.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver MAX4952B
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) VCC .......................................................................-0.3V to +4.0V All Other Pins (Note 1) ............................. -0.3V to (VCC + 0.3V) Short-Circuit Output Current DAP, DAM, HBM, HBP.........90mA Continuous Power Dissipation (TA = +70NC) 20-Pin TQFN (derate 25.6mW/NC above +70NC) .......2051mW Junction-to-Case Thermal Resistance (BJC) (Note 2) 20-Pin TQFN...................................................................6NC/W Junction-to-Ambient Thermal Resistance (BJA) (Note 2) 20-Pin TQFN.................................................................39NC/W Operating Temperature Range ............................. 0NC to +70NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -55NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC
Note 1: All I/O pins are clamped by internal diodes. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, CCL = 10nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3) PARAMETER DC PERFORMANCE Power-Supply Range Power-Down Current Supply Current Input Impedance, Differential Output Impedance, Differential AC PERFORMANCE 0.1GHz < f P 0.3GHz 0.3GHz < f P 0.6GHz Input Return Loss, Differential (Note 4) RLRX-DIFF 0.6GHz < f P 1.2GHz 1.2GHz < f P 2.4GHz 2.4GHz < f P 3.0GHz 3.0GHz < f P 6.0GHz 0.1GHz < f P 0.3GHz 0.3GHz < f P 0.6GHz Input Return Loss, Common Mode (Note 4) RLRX-CM 0.6GHz < f P 1.2GHz 1.2GHz < f P 2.4GHz 2.4GHz < f P 3.0GHz 3.0GHz < f P 6.0GHz -18 -14 -10 -8 -8 -1 -6 -5 -5 -5 -5 -1 dB dB VCC IPWRDN ICC ZRX-DIFFDC
SYMBOL
CONDITIONS
MIN 3.0
TYP
MAX 3.6
UNITS V mA mA I I
EN = GND EN = VCC DC DC BA = BB = VCC BA = BB = GND 85 85
0.35 100 85 100 100
2 130 100 115 115
ZTX-DIFFDC
2
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Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, CCL = 10nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS 0.1GHz < f P 0.3GHz 0.3GHz < f P 0.6GHz Output Return Loss, Differential (Note 4) RLTX-DIFF 0.6GHz < f P 1.2GHz 1.2GHz < f P 2.4GHz 2.4GHz < f P 3.0GHz 3.0GHz < f P 6.0GHz 0.1GHz < f P 0.3GHz 0.3GHz < f P 0.6GHz Output Return Loss, Common Mode (Note 4) RLTX-CM 0.6GHz < f P 1.2GHz 1.2GHz < f P 2.4GHz 2.4GHz < f P 3.0GHz 3.0GHz < f P 6.0GHz SATA 1.5Gbps, 3Gbps, 6Gbps, M = GND Differential Input Signal Range VRX-DFF-PP SAS 1.5Gbps, 3Gbps, M = VCC SAS 6.0Gbps, M = VCC VSQ-DIFF SATA OOB, M = GND SAS OOB, M = VCC BA = BB = GND BA = BB = VCC 225 275 300 50 120 450 900 300 Figure 1 (Notes 4, 5) Up to 6.0Gbps (Notes 4, 6) Up to 6.0Gbps (Notes 4, 6) (Note 7) Difference between OOB and active-mode output offset Difference between OOB and active-mode output VCM -80 -50 3 40 40 15 1.4 5 +80 +50 MIN TYP MAX -14 -8 -8 -8 -8 -1 -8 -5 -5 -5 -5 -1 1600 1600 1600 150 220 650 1300 mVP-P mVP-P ps ps psP-P psRMS ns mV mV mVP-P dB dB UNITS
MAX4952B
OOB Squelch Threshold Differential Output-Voltage Swing Propagation Delay Output Rise/Fall Time Deterministic Jitter Random Jitter OOB Output Startup/Shutdown Time Differential Offset Delta Common-Mode Delta CONTROL LOGIC Input Logic-Level Low Input Logic-Level High Input Logic Hysteresis Input Pulldown Resistor ESD PROTECTION All Pins Note Note Note Note Note 3: 4: 5: 6: 7:
VTX-DIFF-PP f = 750MHz, 1.5GHz tPD tTX-RISEFALL
tTX-DJ-DD tTX-RJ-DD tOOB DVOOB,DIFF DVOOB,CM
VIL VIH VHYST RDOWN Human Body Model 1.4 100 70 5.5
0.6
V V mV kI kV
All devices are 100% production tested at TA = +70C. Specifications for all temperature limits are guaranteed by design. Guaranteed by design. Rise and fall times are measured using 20% and 80% levels. DJ measured using K28.5 pattern; RJ measured using D10.2 pattern. Total time for OOB detection circuit to enable/squelch the output. _______________________________________________________________________________________ 3
Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver MAX4952B
Typical Operating Characteristics
(VCC = +3.3V, M = GND, TA = +25NC; all eye diagrams measured using K28.5 pattern, unless otherwise noted.)
VIN = 225mVP-P, 1.5Gbps, B_ = 0
400 300 200 100mV/div
MAX4952B toc01
VIN = 225mVP-P, 3Gbps, B_ = 0
400 300 200
VIN = 225mVP-P, 6Gbps, B_ = 0
400 300 200 100mV/div 100 0 -100 -200 -300
MAX4952B toc02
MAX4952B toc03
0 -100 -200 -300 -400 -600 -400 -200 0 200ps/div 200 400 600
100mV/div
100
100 0 -100 -200 -300 -400 -300 -200 -100 0 100ps/div 100 200 300
-400 -150 -100 -50 0 50ps/div 50 100 150
VIN = 225mVP-P, 1.5Gbps, B_ = 1
600 400 200mV/div
MAX4952B toc04
VIN = 225mVP-P, 3Gbps, B_ = 1
600 400 200mV/div
MAX4952B toc05
VIN = 225mVP-P, 6Gbps, B_ = 1
600 400 200mV/div 200 0 -200 -400 -600
MAX4952B toc06
200 0 -200 -400 -600 -600 -400 -200 0 200ps/div 200 400 600
200 0 -200 -400 -600 -300 -200 -100 0 100ps/div 100 200 300
-150
-100
-50
0 50ps/div
50
100
150
VIN = 1600mVP-P, 1.5Gbps, B_ = 0
400 300 200 100mV/div
MAX4952B toc07
VIN = 1600mVP-P, 3Gbps, B_ = 0
400 300 200 100mV/div
MAX4952B toc08
VIN = 1600mVP-P, 6Gbps, B_ = 0
400 300 200 100mV/div 100 0 -100 -200 -300 -400
MAX4952B toc09
100 0 -100 -200 -300 -400 -600 -400 -200 0 200ps/div 200 400 600
100 0 -100 -200 -300 -400 -300 -200 -100 0 100ps/div 100 200 300
-150
-100
-50
0 50ps/div
50
100
150
4
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Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver
Typical Operating Characteristics (continued)
(VCC = +3.3V, M = GND, TA = +25NC; all eye diagrams measured using K28.5 pattern, unless otherwise noted.)
MAX4952B
VIN = 1600mVP-P, 1.5Gbps, B_ = 1
600 400 200mV/div
MAX4952B toc10
VIN = 1600mVP-P, 3Gbps, B_ = 1
600 400 200mV/div
MAX4952B toc11
VIN = 1600mVP-P, 6Gbps, B_ = 1
600 400 200mV/div 200 0 -200 -400 -600
MAX4952B toc12
200 0 -200 -400 -600 -600 -400 -200 0 200ps/div 200 400 600
200 0 -200 -400 -600 -300 -200 -100 0 100ps/div 100 200 300
-150
-100
-50
0 50ps/div
50
100
150
DIFFERENTIAL INPUT RETURN LOSS vs. FREQUENCY
MAX4952B toc13
DIFFERENTIAL OUTPUT RETURN LOSS vs. FREQUENCY
DIFFERENTIAL INPUT RETURN LOSS (dB) -5 -10 -15 -20 -25 -30 -35 -40 0 2 4 6
DIFFERENTIAL INPUT RETURN LOSS (dB)
-5 -10 -15 -20 -25 -30 -35 -40 0
EC TABLE LIMIT
EC TABLE LIMIT MAX4952B
MAX4952B
2
4
6
FREQUENCY (GHz)
FREQUENCY (GHz)
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MAX4952B toc14
0
0
5
Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver MAX4952B
Pin Configuration
DAM DBM 12 DAP GND DBP 11 10 9 MAX4952B 8 7 VCC BA BB EN VCC
TOP VIEW
15 VCC 16 GND 17 GND 18 M 19 VCC 20
14
13
+
1 HAP 2 HAM 3 GND 4
*EP
6 5 HBP
TQFN
*CONNECT EXPOSED PAD (EP) TO GND.
HBM
Pin Description
PIN 1 2 3, 13, 17, 18 4 5 6, 10, 16, 20 7 8 9 11 12 14 15 19 -- NAME HAP HAM GND HBM HBP VCC EN BB BA DBP DBM DAM DAP M EP FUNCTION Noninverting Input from Host Channel A. HAP must be capacitively coupled (see note). Inverting Input from Host Channel A. HAM must be capacitively coupled (see note). Ground Inverting Output to Host Channel B. HBM must be capacitively coupled (see note). Noninverting Output to Host Channel B. HBP must be capacitively coupled (see note). Power-Supply Input. Bypass VCC to GND with low-ESR 0.01FF and 4.7FF capacitors in parallel as close to the device as possible; recommended for each VCC pin. Enable Input. Drive EN low for low-power standby mode. Drive EN high for normal operation. EN is internally pulled down by a 70kI (typ) resistor. Channel B Boost-Enable Input. Drive BB high to enable channel B +6dB output boost. Drive BB low for standard SAS/SATA output level. BB is internally pulled down by a 70kI (typ) resistor. Channel A Boost-Enable Input. Drive BA high to enable channel A +6dB output boost. Drive BA low for standard SAS/SATA output level. BA is internally pulled down by a 70kI (typ) resistor. Noninverting Input from Device Channel B. DBP must be capacitively coupled (see note). Inverting Input from Device Channel B. DBM must be capacitively coupled (see note). Inverting Output to Device Channel B. DAM must be capacitively coupled (see note). Noninverting Output to Device Channel B. DAP must be capacatively coupled (see note). OOB-Mode Logic Input. M is internally pulled down by a 70kI (typ) resistor. Drive M low or leave unconnected for SATA OOB threshold. Drive M high for SAS OOB threshold. Exposed Pad. Internally connected to GND. Connect to a large ground plane for proper thermal and electrical operation. Not intended as an electrical connection point.
Note: For proper operation, Maxim recommends the use of low-ESR, X7R, 10nF, 0402-sized capacitors for all redriver inputs and outputs. 6 ______________________________________________________________________________________
Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver MAX4952B
eSATA CONNECTOR RISE/FALL TIME COMPLIANCE POINT
CONTROLLED IMPEDANCE
2in (5cm) MINIMUM
MAX4952B
Figure 1. Circuit for Measuring tR/F for MAX4952B (refer to the SATA specifications for compliance measurement)
Functional Diagram/Truth Table
VCC
EN 0 1
BA X 0 0 1 1
BB X 0 1 0 1
CHANNEL A OUTPUT LEVEL Power-Down No Boost No Boost Boost Boost
CHANNEL B OUTPUT LEVEL Power-Down No Boost Boost No Boost Boost
VCC
MAX4952B
VCC
1 1 1
DAP DAM
50 HAP HAM VCC
50
50
50
X = Don't care. M 0 1 OOB THRESHOLD SATA SAS/SATA
VCC
50 HBM HBP
50
50
50 DBM DBP
CONTROL LOGIC
GND
EN
M
BA
BB
_______________________________________________________________________________________
7
Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver MAX4952B
+3.3V
4.7 F
0.01 F
10nF (X7R) HAP Tx SAS HOST CONTROLLER Rx 10nF (X7R) HAM
VCC
10nF (X7R) DAP 10nF (X7R) DAM Rx SAS DEVICE CONNECTOR Tx
MAX4952B 10nF (X7R) HBM 10nF (X7R) HBP EP M BA DBP BB GND DBM 10nF (X7R) 10nF (X7R)
GPIO
GPIO
Figure 2. Typical Application Circuit
SAS CABLE
BACKPLANE
MIDPLANE
MAIN BOARD
SAS/SATA HDD
8in BOARD TRACES
MAX4952B
8in BOARD TRACES
SAS CONTROLLER
Figure 3. MAX4952B Driving a SAS Cable
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Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver
Detailed Description
The MAX4952B dual-channel redriver is designed to redrive one full lane of SAS/SATA signals up to 6.0Gbps while operating from a single +3.3V supply. The MAX4952B features independent output boost and enhances signal integrity at the receiver by re-establishing full output levels. SAS/SATA OOB signaling is supported using high-speed amplitude detection on the inputs and squelch on the corresponding outputs. Inputs and outputs are internally 50I terminated to VCC (see the Functional Diagram/Truth Table) and must be AC-coupled using low-ESR, X7R, 10nF capacitors to the SAS/SATA controller IC and SAS/SATA device for proper operation. The MAX4952B features an active-high enable input, EN, which has an internal pulldown resistor of 70kI (typ). When EN is driven low or left unconnected, the MAX4952B enters power-down mode and squelches the output. Drive EN high for normal operation. The MAX4952B supports both SAS and SATA OOB levels. When in SAS mode, the OOB threshold is 120mVP-P (min), and when in SATA mode, the OOB threshold is 50mVP-P (min). Signals below the OOB threshold are squelched to prevent unwanted noise from being redriven at the output. Drive M low or leave unconnected to set SATA OOB levels. Drive M high to set SAS OOB levels. See the Functional Diagram/Truth Table. M has an internal pulldown resistor of 70kI (typ). The MAX4952B has two digital control logic inputs, BA and BB. BA and BB have internal pulldown resistors of 70kI (typ). BA and BB control the boost level of their corresponding redrivers (see the Functional Diagram/ Truth Table). Drive BA or BB low or leave unconnected for standard SATA output levels. Drive BA or BB high to boost the output or for standard SAS output levels. quency design techniques, including minimizing ground inductance and using controlled-impedance transmission lines on data signals. Place low-ESR 0.01FF and 4.7FF power-supply bypass capacitors in parallel as close to VCC as possible, or, as recommended, on each VCC pin. Always connect VCC to a power plane. The MAX4952B requires coupling capacitors for all redriver inputs and outputs. Maxim recommends high-quality, low-ESR, X7R, 10nF, 0402-sized capacitors. The exposed-pad, 20-pin TQFN package incorporates features that provide a very low-thermal resistance path for heat removal from the IC. The exposed pad on the MAX4952B must be soldered to the circuit board ground plane for proper thermal and electrical performance. For more information on exposed-pad packages, refer to Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages. As with all Maxim devices, ESD protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The MAX4952B is protected against ESD up to Q5.5kV (Human Body Model) without damage. The ESD structures withstand Q5.5kV in all states (normal operation and powered down). After an ESD event, the MAX4952B continues to function without latchup. The MAX4952B is characterized for Q5.5kV ESD protection using the Human Body Model (MIL-STD-883, Method 3015). Figure 4 shows the Human Body Model and Figure 5 shows the current waveform it generates when discharged into low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the device through a 1.5kI resistor.
MAX4952B
Input/Output Terminations
Exposed-Pad Package
Enable Input (EN)/Power-Down Mode
ESD Protection
SAS/SATA Mode Input (M)
Human Body Model
Output Boost-Selection Inputs (BA, BB)
Power-Supply Sequencing
Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the device. Proper power-supply sequencing is recommended for all devices. Always apply GND then VCC before applying signals, especially if the signal is not current limited.
Applications Information
Circuit board layout and design can significantly affect the performance of the MAX4952B. Use good, high-fre-
Layout
_______________________________________________________________________________________
9
Dual 1.5/3.0/6.0Gbps SAS/SATA Redriver MAX4952B
RC 1M CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 1500 DISCHARGE RESISTANCE DEVICE UNDER TEST IP 100% 90% AMPS 36.8% 10% 0 Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
CS 100pF
STORAGE CAPACITOR
0
tRL
TIME tDL CURRENT WAVEFORM
Figure 4. Human Body ESD Test Model
Figure 5. Human Body Current Waveform
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 20 TQFN-EP PACKAGE CODE T2044+2 DOCUMENT NO. 21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10
(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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