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NTMD6N04R2 Power MOSFET
40 V, 5.8 A, Dual N-Channel SOIC-8
Features
* Designed for use in low voltage, high speed switching applications * Ultra Low On-Resistance Provides
Higher Efficiency and Extends Battery Life - RDS(on) = 0.027 W, VGS = 10 V (Typ) - RDS(on) = 0.034 W, VGS = 4.5 V (Typ) Miniature SOIC-8 Surface Mount Package Saves Board Space Diode is Characterized for Use in Bridge Circuits Diode Exhibits High Speed, with Soft Recovery Pb-Free Package is Available DC-DC Converters Computers Printers Cellular and Cordless Phones Disk Drives and Tape Drives
VDSS 40 V
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RDS(ON) Typ 27 mW @ VGS = 10 V ID Max 5.8 A
* * * * * * * * *
N-Channel D D
Applications
G S
G S
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Drain Current (Note 1) - Continuous @ TA = 25C - Single Pulse (tp 10 ms) Drain Current (Note 2) - Continuous @ TA = 25C Total Power Dissipation @ TA = 25C (Note 1) @ TA = 25C (Note 2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 40 Vdc, VGS = 5.0 Vdc, Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25 W) Thermal Resistance - Junction-to-Ambient (Note 1) - Junction-to-Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes for 10 Sec Symbol VDSS VGS ID IDM ID PD 2.0 1.29 TJ, Tstg EAS -55 to +150 245 C mJ Value 40 "20 5.8 29 4.6 Unit V V Adc Apk Adc W 8 1 SOIC-8 CASE 751 STYLE 11
MARKING DIAGRAM & PIN ASSIGNMENT
D1 D1 D2 D2 8 E6N04 AYWW G G 1 S1 G1 S2 G2 = Specific Device Code = Assembly Location = Year = Work Week = Pb-Free Package
E6N04 A Y WW G
(Note: Microdot may be in either location)
ORDERING INFORMATION
RqJA C/W 62.5 97 260 C Device NTMD6N04R2G Package SOIC-8 (Pb-Free) Shipping 2500/Tape & Reel
TL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using 1 pad size, t 10 s 2. When surface mounted to an FR4 board using 1 pad size, t = steady state
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2007
1
December, 2007 - Rev. 0
Publication Order Number: NTMD6N04R2/D
NTMD6N04R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mA) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 40 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 40 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) Static Drain-to-Source On-State Resistance (VGS = 10 Vdc, ID = 5.8 Adc) (VGS = 4.5 Vdc, ID = 3.9 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 5.8 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 3 & 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 20 Vdc, VGS = 10 Vdc, ID = 5.8 A) (VDD = 20 Vdc, ID = 5.8 A, VGS = 4.5 V, RG = 6 W) (VDD = 20 Vdc, ID = 5.8 A, VGS = 10 V, RG = 6 W) td(on) tr td(off) tf td(on) tr td(off) tf QT Qgs Qgd 10 20 45 40 15 55 30 35 20 2.5 5.5 18 35 70 65 30 nC ns ns (VDS = 32 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss 723 156 53 900 225 75 pF Vdc VGS(th) VGS(th)/TJ RDS(on) gFS 8.12 0.027 0.034 0.034 0.043 Mhos 1.0 1.9 4.7 3.0 mV/C W Vdc V(BR)DSS V(BR)DSS/TJ IDSS IGSS 1.0 10 "100 nAdc 40 47 45 mV/C mAdc Symbol Min Typ Max Unit
BODY-DRAIN DIODE RATINGS (Note 3) Diode Forward On-Voltage Reverse Recovery Time (IS = 1.7 A, VGS = 0 V, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge (IS = 1.7 A, dIS/dt = 100 A/ms, VGS = 0 V) 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperature. (IS = 1.7 Adc, VGS = 0 V) (IS = 1.7 Adc, VGS = 0 V, TJ = 150C) VSD trr ta tb QRR 0.76 0.56 23 16 7 20 1.1 nC Vdc ns
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NTMD6N04R2
14 6 V - 10 V 12 ID, DRAIN CURRENT (A) 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 2.4 V 3.0 V 2.8 V VGS = 2.6 V 4.5 5 5.5 6 3.6 V 3.2 V 4.0 V 3.8 V TJ = 25C ID, DRAIN CURRENT (A) 3.4 V 20 18 16 14 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 VGS, GATE-TO-SOURCE VOLTAGE (V) TJ = 100C TJ = 25C TJ = -55C VDS w 10 V
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.2
Figure 2. Transfer Characteristics
VGS = 10 V TJ = 25C
0.15
0.1
0.05
0 2 3 4 5 6 7 8 9 10 VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 3. On-Resistance vs. Gate-to-Source Voltage
1.8 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 -50 1 -25 0 25 50 75 100 125 150 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (V) ID = 5.8 A VGS = 10 V IDSS, LEAKAGE (nA) 1000 10000 VGS = 0 V TJ = 150C
100 TJ = 100C 10
Figure 4. On Resistance Variation with Temperature
Figure 5. Drain-to-Source Leakage Current vs. Voltage
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3
NTMD6N04R2
VGS, GATE-TO-SOURCE VOLTAGE (V)
2400 VDS = 0 V VGS = 0 V C, CAPACITANCE (pF) 1800 Ciss TJ = 25C
10 QT 8 VGS VDS
25 VDS, DRAIN-TO-SOURCE VOLTAGE (V)
20
6 Q1
15
1200
Crss Ciss
Q2
10
600 Coss Crss -10 VGS -5 0 5 VDS 10 15
2 ID = 5.8 A TJ = 25C 0 0 3 6 9 12 15 18
5
0
20
0 21
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 6. Capacitance Variation
4 IS, SOURCE CURRENT (A) 3.5 3 2.5 2 1.5 1 0.5 0 0.4 0.01 0.5 0.6 0.7 0.8 0.9 VGS = 0 V TJ = 25C ID, DRAIN CURRENT (A) 10 100
Figure 7. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge
VGS = 20 V Single Pulse TC TA = 25C 10 ms 1 RDS(on) THERMAL LIMIT PACKAGE LIMIT Mounted on FR4 board using 1 in pad size, with die operating 10s max. 0.1 1 10 100 ms 1 ms 10 ms
0.1
dc
100
VSD, SOURCE-TO-DRAIN VOLTAGE (V)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 8. Diode Forward Voltage vs. Current
Figure 9. Maximum Rated Forward Biased Safe Operating Area
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NTMD6N04R2
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
-XA
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-YG C -ZH D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004) M ZY
S
J
X
S
SOLDERING FOOTPRINT*
1.52 0.060
STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTMD6N04R2/D

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