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| SSM4232GM N-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY D2 Low On-Resistance Simple Drive Requirement Dual N MOSFET Package D2 D1 D1 G2 S2 BVDSS RDS(ON) ID G1 30V 22m 7.8A SO-8 S1 DESCRIPTION The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. D1 D2 G1 S1 G2 S2 Pb-free; RoHS-compliant ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current 1 3 3 Rating 30 20 7.8 6.2 30 2 0.016 -55 to 150 -55 to 150 Units V V A A A W W/ Continuous Drain Current Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit /W 09/23/2007 Rev.1.00 www.SiliconStandard.com 1 SSM4232GM ELECTRICAL CHARACTERISTICS @ TJ=25oC ( unless otherwise specified ) Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 30 1 - Typ. 0.02 12 13 3 9 10 7 22 8 720 230 200 1.2 Max. Units 22 32 3 1 25 100 21 1150 1.8 V V/ m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA RDS(ON) Static Drain-Source On-Resistance2 VGS=10V, ID=7A VGS=4.5V, ID=5A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=7A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS=20V ID=7A VDS=24V VGS=4.5V VDS=15V ID=1A RG=3.3,VGS=10V RD=15 VGS=0V VDS=25V f=1.0MHz f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance 2 SOURCE-DRAIN DIODE Symbol VSD Parameter Forward On Voltage 2 2 Test Conditions IS=1.7A, VGS=0V IS=7A, VGS=0V, dI/dt=100A/s Min. - Typ. 16 8 Max. Units 1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board, t <10sec ; 135 /W when mounted on Min. copper pad. 09/23/2007 Rev.1.00 www.SiliconStandard.com 2 SSM4232GM 40 40 T A = 25 C 30 o ID , Drain Current (A) 10V 7.0 V 5.0 V 4.5 V ID , Drain Current (A) T A = 150 o C 30 10V 7.0 V 5.0 V 4.5 V 20 20 10 10 V G = 3.0 V V G = 3.0 V 0 0 1 2 3 4 5 0 0 1 2 3 4 5 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 30 1.6 ID=5A T A =25 Normalized R DS(ON) 25 ID=7A V G =10V 1.3 RDS(ON) (m ) 20 1.0 15 0.7 2 4 6 8 10 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 2.0 8 6 1.5 4 Normalized VGS(th) (V) 1.2 IS(A) 1.0 T j =150 C 2 o T j =25 C o 0.5 0 0 0.2 0.4 0.6 0.8 1 0.0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 09/23/2007 Rev.1.00 Fig 6. Gate Threshold Voltage v.s. Junction Temperature 3 www.SiliconStandard.com SSM4232GM f=1.0MHz 16 1000 ID=7A VGS , Gate to Source Voltage (V) C iss 12 8 C (pF) V DS =15V V DS =20V V DS =24V C oss 4 C rss 0 0 5 10 15 20 25 30 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (Rthja) Duty factor=0.5 0.2 10 100us 1ms ID (A) 1 0.1 0.1 0.05 10ms 100ms 0.02 PDM t T Single Pulse 0.01 0.01 Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 135/W 0.1 T A =25 o C Single Pulse 1s DC 0.01 0.1 1 10 100 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 30 V DS =5V ID , Drain Current (A) T j =25 o C 20 VG T j =150 o C QG 4.5V QGS QGD 10 Charge 0 Q 0 2 4 6 V GS , Gate-to-Source Voltage (V) Fig 11. Transfer Characteristics 09/23/2007 Rev.1.00 Fig 12. Gate Charge Waveform 4 www.SiliconStandard.com SSM4232GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 09/23/2007 Rev.1.00 www.SiliconStandard.com 5 |
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