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ADP3121 Dual Bootstrapped, 12 V MOSFET Driver with Output Disable
The ADP3121 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a non-isolated synchronous buck power converter. Each driver is capable of driving a 3000 pF load with a 20 ns propagation delay and a 15 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3121 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3121 is specified over the commercial temperature range of 0C to 85C and is available in 8-lead SOIC_N and 8-lead LFCSP packages.
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8 1 SO-8 D SUFFIX CASE 751 8 P3121 ALYW G
1
* * * * * * * *
All-in-one Synchronous Buck Driver Bootstrapped High-side Drive One PWM Signal Generates Both Drives Anticross Conduction Protection Circuitry Over Voltage Protection OD for Disabling the Driver Outputs Meets CPU VR Requirement when Used with Flex-ModeTM Controller These are Pb-Free Devices
P3121 = Specific Device Code AL = Assembly Location Y = Year W = Work Week G = Pb-Free Package 8 1 LFCSP8 MN SUFFIX CASE 932AF
Typical Applications
L7Q #YWW G L7Q Y WW G = Specific Device Code = Year = Work Week = Pb-Free Package
* Multiphase Desktop CPU Supplies * Single-supply Synchronous Buck Converters
ORDERING INFORMATION
Device ADP3121JRZ-RL Package SOIC_N (Pb-Free) Shipping 2500/Tape & Reel
ADP3121JCPZ-RL LFCSP_VD 5000/Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
April, 2009 - Rev. 0
1
Publication Order Number: ADP3121/D
ADP3121
PIN CONNECTIONS BST IN OD VCC DRVH SWN PGND DRVL
12V
4 ADP3121 LATCH R1 Q R2 S DELAY
VCC 1 BST CBST1 8 DRVH
D1 CBST2
IN 2
RG RBST
Q1 TO INDUCTOR
7 CMP CMP 1V CONTROL LOGIC DELAY VCC 6 5
SW
DRVL
Q2
OD 3
6
PGND
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 6 7 Pin Name BST IN OD VCC DRVL PGND SW Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET while it is switching. Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. Input Supply. This pin should be bypassed to PGND with an ~1 mF ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. This pin should be closely connected to the source of the lower MOSFET. Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent the lower MOSFET from turning on until the voltage is below ~1 V. Buck Drive. Output drive for the upper (buck) MOSFET.
8
DRVH
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ADP3121
MAXIMUM RATINGS
Rating qJA, SOIC_N 2-Layer Board 4-Layer Board qJA, LFCSP_VD (Note 1) 4-Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) 300 215 260 C C C 64.3 0 to 85 0 to 150 -65 to +150 C/W C C C 123 90 C/W C/W Value Unit
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Internally limited by thermal shutdown, 150C min. 2. 2 layer board, 1 in2 Cu, 1 oz thickness. 3. 60-180 seconds minimum above 237C. 4. This device is ESD sensitive. Use standard ESD precautions when handling
ABSOLUTE MAXIMUM RATINGS
Pin Symbol VCC GND BST Pin Name Main supply voltage input Ground Bootstrap Supply Voltage Input DC <200 ns BST to SW SW Switching Node (Bootstrap Supply Return) DC <200 ns DRVH High-Side Driver Output DC <20 ns <200 ns DRVL Low-Side Driver Output DC <20 ns <200 ns IN OD DRVH and DRVL Control Input Outside Disable VCC + 0.3 V VCC + 2 V VCC + 0.3 V 6.5 V 6.5 V -0.3 V -2 V -2 V -0.3 V -0.3 V BST + 0.3 BST + 2 V BST + 0.3 V SW - 0.3 V SW - 2 V SW - 2 V +15 +25 V -5 V -10 V VCC + 15 +35 +15 -0.3 V -0.3 V -0.3 V Vmax 15 V 0V Vmin -0.3 V 0V
NOTE: All voltages are with respect to PGND except where noted. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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ADP3121
ELECTRICAL CHARACTERISTICS (VCC = 12 V, BST = 4 V to 26 V, TA = 0C to 85C, unless otherwise noted) (Note 5)
Characteristic SUPPLY Supply Voltage Range Supply Current OD INPUTS Input Voltage High Input Voltage Low Input Current Hysteresis PWM INPUTS Input Voltage High Input Voltage Low Input Current Hysteresis HIGH-SIDE DRIVER Output Resistance, Sourcing Current BST - SW = 12 V; TA = 25C BST - SW = 12 V; TA = 0C to 85C Output Resistance, Sinking Current BST - SW = 12 V; TA = 25C BST - SW = 12 V; TA = 0C to 85C Output Resistance, Unbiased Transition Times BST - SW = 0 V BST - SW = 12 V, CLOAD = 3 nF, see Figure 4 BST - SW = 12 V, CLOAD = 3 nF, see Figure 4 Propagation Delay Times BST - SW = 12 V, CLOAD = 3 nF 25C TA 85C, see Figure 4 BST - SW = 12 V, CLOAD = 3 nF, see Figure 4 See Figure 3 See Figure 3 SW Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current TA = 25C TA = 0C to 85C Output Resistance, Sinking Current TA = 25C TA = 0C to 85C Output Resistance, Unbiased Transition Times VCC = PGND CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 Propagation Delay Times CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 See Figure 3 See Figure 3 trDRVL tfDRVL tpdhDRVL tpdlDRVL tpdlOD tpdhOD 100 1.0 10 20 10 15 17 37 180 30 20 35 32 52 1.8 2.4 2.8 1.6 1.8 W W W W kW ns ns ns ns ns ns SW to PGND tpdlDRVH tpdlOD tpdhOD 32 30 20 10 47 45 40 ns ns ns kW trDRVH tfDRVH tpdhDRVH 20 1.7 10 20 20 30 32 30 50 1.7 2.3 2.8 2.3 2.8 W W W W kW ns ns ns -1 90 250 2.0 0.8 +1 V V mA mV -1 90 250 2.0 0.8 +1 V V mA mV BST = 12 V, IN = 0 V VCC ISYS 4.15 2 13.2 5 V mA Test Conditions Symbol Min Typ Max Unit
5. ALL limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods
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ADP3121
ELECTRICAL CHARACTERISTICS (VCC = 12 V, BST = 4 V to 26 V, TA = 0C to 85C, unless otherwise noted) (Note 5)
Characteristic LOW-SIDE DRIVER Timeout Delay Over-voltage Protection Threshold UNDERVOLTAGE LOCKOUT UVLO Voltage Hysteresis VCC rising 1.5 250 3.0 V mV SW = 5 V SW = PGND IN = OD = 0 V, SW = VCC VSW(OVD) 90 70 1.5 170 110 3.5 ns V Test Conditions Symbol Min Typ Max Unit
5. ALL limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods
APPLICATIONS INFORMATION
Theory of Operation Overlap Protection Circuit
The ADP3121 is optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 500 kHz. A functional block diagram of ADP3121 is shown in Figure 1.
Low-Side Driver
The low-side driver is designed to drive a ground referenced N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND. When the driver is enabled, the driver output is 180 out of phase with the PWM input. When the ADP3121 is disabled, the low-side gate is held low.
High-Side Driver
The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit that is connected between the BST and SW pins. The bootstrap circuit comprises Diode D1 and Bootstrap Capacitor CBST1. CBST2 and RBST are included to reduce the high-side gate drive voltage and to limit the switch node slew rate (called a Boot-Snapt circuit). When the ADP3121 starts up, the SW pin is at ground, so the bootstrap capacitor charges up to VCC through D1. When the PWM input goes high, the high-side driver begins to turn on the high-side MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1 turns on, the SW pin rises up to VIN and forces the BST pin to VIN + VC (BST). This holds Q1 on because enough gate-to-source voltage is provided. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET, Q2, turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. The output of the high-side driver is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
The overlap protection circuit prevents both of the main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from the Q1 turn-off to the Q2 turn-on, and by internally setting the delay from the Q2 turn-off to the Q1 turn-on. To prevent the overlap of the gate drives during the Q1 turn-off and the Q2 turn-on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, Q1 begins to turn off (after propagation delay). Before Q2 can turn on, the overlap protection circuit makes sure that SW has first gone high and then waits for the voltage at the SW pin to fall from VIN to 1 V. Once the voltage on the SW pin falls to 1 V, Q2 begins turn-on. If the SW pin has not gone high first, the Q2 turn-on is delayed by a fixed 150 ns. By waiting for the voltage on the SW pin to reach 1 V or for the fixed delay time, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. If SW does not go below 1 V after 190 ns, DRVL turns on. This can occur if the current flowing in the output inductor is negative and flows through the high-side MOSFET body diode.
OVERVOLTAGE PROTECTION
The ADP3121 includes an over-voltage protection (OVP) feature to protect the CPU from high voltages even before the main controller has enough VCC to operate. The ADP3121 looks at the SW node during startup. If the voltage on SW is greater than the OVP threshold, DRVL is latched on and DRVH latched off. An OVP on the SW node will cause DRVL to go high and remain high. To prevent false triggering of OVP, an input logic detection latch is set on the first occurrence of either IN or
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ADP3121
OD going high. If this second latch is set, then OVP is enabled. To clear the OVP or the input detected latch, VCC must fall below UVLO.
Supply Capacitor Selection
where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be calculated by
I F(PEAK) + MOSFET Selection V CC * V D R BST
(eq. 4)
For the supply input (VCC) of the ADP3121, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents that are drawn. Use a 4.7 mF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3121.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBST) and a diode, as shown in Figure 1. These components can be selected after the high-side MOSFET is chosen. The bootstrap capacitor must have a voltage rating that can handle twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitor values are determined by
C BST1 ) C BST2 + 10 Q GATE V GATE
(eq. 1)
When interfacing the ADP3121 to external MOSFETs, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short time duration voltage ratings on the driver pins as well as the external MOSFET. It is also highly recommended to use the Boot-Snap circuit to improve the interaction of the driver with the characteristics of the MOSFETs. If a simple bootstrap arrangement is used, make sure to include a proper snubber network on the SW node.
High-Side (Control) MOSFETs
C BST1 V GATE + V CC * V D C BST1 ) C BST2
(eq. 2)
where: QGATE is the total gate charge of the high-side MOSFET at VGATE. VGATE is the desired gate drive voltage (usually in the range of 5 V to 10 V, 7 V being typical). VD is the voltage drop across D1. Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
C BST1 + 10 Q GATE V CC * V D Q GATE * C BST1 V GATE
CBST2 can then be found by rearranging Equation 1
C BST2 + 10
For example, an NTD60N02 has a total gate charge of about 12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 0.1 V, then CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors should be used. RBST is used to limit slew rate and minimize ringing at the switch node. It also provides peak current limiting through D1. An RBST value of 1.5 W to 2.2 W is a good choice. The resistor needs to handle at least 250 mW due to the peak currents that flow through it. A small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by VCC. The bootstrap diode must have a minimum 15 V rating to withstand the maximum supply voltage. The average forward current can be estimated by
I F(AVG) + Q GATE f MAX
(eq. 3)
A high-side, high speed MOSFET is usually selected to minimize switching losses (see the ADP3186 or ADP3188 data sheet for Flex-Mode controller details). This typically implies a low gate resistance and low input capacitance/charge device. Yet, a significant source lead inductance can also exist that depends mainly on the MOSFET package; it is best to contact the MOSFET vendor for this information. The ADP3121 DRVH output impedance and the input resistance of the MOSFETs determine the rate of charge delivery to the internal capacitance of the gate. This determines the speed at which the MOSFETs turn on and off. However, because of potentially large currents flowing in the MOSFETs at the on and off times (this current is usually larger at turn-off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high-side MOSFETs switch off. This creates a significant drain-source voltage spike across the internal die of the MOSFETs and can lead to a catastrophic avalanche. The mechanisms involved in this avalanche condition are referenced in literature from the MOSFET suppliers. The MOSFET vendor should provide a rating for the maximum voltage slew rate at drain current around which this can be designed. Once this specification is obtained, determine the maximum current expected in the MOSFET by
I MAX + I DC(per phase) ) (V CC * V OUT) D MAX f MAX L OUT
(eq. 5)
where: DMAX is determined for the VR controller being used with the driver. This current is divided roughly equally between MOSFETs if more than one is used (assume a worst-case mismatch of 30% for design margin). LOUT is the output inductor value.
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ADP3121
When producing the design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external MOSFETs as well as the PCB. However, it can be measured to determine if it is safe. If it appears that the dV/dt is too fast, an optional gate resistor can be added between DRVH and the high-side MOSFETs. This resistor slows down the dV/dt, but it increases the switching losses in the high-side MOSFETs. The ADP3121 is optimally designed with an internal drive impedance that works with most MOSFETs to switch them efficiently, yet minimizes dV/dt. However, some high speed MOSFETs can require this external gate resistor depending on the currents being switched in the MOSFET.
Low-Side (Synchronous) MOSFETs
turns on. Contact ON Semiconductor for an updated list of recommended low-side MOSFETs.
PC Board Layout Considerations
The low-side MOSFETs are usually selected to have a low on resistance to minimize conduction losses. This usually implies a large input gate capacitance and gate charge. The first concern is to make sure the power delivery from the ADP3121 DRVL does not exceed the thermal rating of the driver (see the ADP3186, ADP3188, or ADP3189 data sheets for Flex-Mode controller details). The next concern for the low-side MOSFETs is to prevent them from being inadvertently switched on when the high-side MOSFET turns on. This occurs due to the drain-gate (Miller capacitance, also specified as Crss capacitance) of the MOSFET. When the drain of the low-side MOSFET is switched to VCC by the high-side turning on (at a dV/dt rate), the internal gate of the low-side MOSFET is pulled up by an amount roughly equal to VCC x (Crss/Ciss). It is important to make sure this does not put the MOSFET into conduction. Another consideration is the nonoverlap circuitry of the ADP3121 that attempts to minimize the nonoverlap period. During the state of the high-side turning off to low-side turning on, the SW pin is monitored (as well as the conditions of SW prior to switching) to adequately prevent overlap. However, during the low-side turn-off to high-side turn-on, the SW pin does not contain information for determining the proper switching time, so the state of the DRVL pin is monitored to go below one sixth of VCC; then, a delay is added. Due to the Miller capacitance and internal delays of the low-side MOSFET gate, ensure that the Miller-to-input capacitance ratio is low enough, and that the low-side MOSFET internal delays are not so large as to allow accidental turn-on of the low-side when the high-side
Use these general guidelines when designing printed circuit boards: * Trace out the high current paths and use short, wide (>20 mil) traces to make these connections. * Minimize trace inductance between DRVH and DRVL outputs and MOSFET gates. * Connect the PGND pin of the ADP3121 as closely as possible to the source of the lower MOSFET. * Locate the VCC bypass capacitor as close as possible to the VCC and PGND pins. * Use vias to other layers, when possible, to maximize thermal conduction away from the IC. Figure 2 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the PC Board Layout Considerations section of the ADP3188 data sheet.
CBST1
CBST2
RBST
CVCC
Figure 2. External Component Placement Example
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OD
tpdlOD DRVH OR DRVL 90%
tpdhOD
10%
Figure 3. Output Disable Timing Diagram
IN
tpdlDRVL
tfDRVL tpdlDRVH
trDRVL
DRVL
tpdhDRVH
trDRVH
tfDRVH
VTH DRVH-SW
VTH
tpdhDRVL 1V SW
Figure 4. Timing Diagram
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PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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ADP3121
PACKAGE DIMENSIONS
LFCSP8 3x3, 0.5P CASE 932AF-01 ISSUE O
D D1
PIN ONE REFERENCE
AB
E1
E
0.25 C 0.25 C TOP VIEW H 0.10 C
NOTE 4
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D1 D2 E E1 E2 e H K L M MILLIMETERS MIN MAX 0.80 0.90 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.75 BSC 1.59 1.89 3.00 BSC 2.75 BSC 1.30 1.60 0.50 BSC --- 12 0.20 --- 0.30 0.50 --- 0.60
(A3) A
0.08 C
A1 SIDE VIEW
C
SEATING PLANE
4X
M
1
K
PIN 1 INDICATOR 8X
D2 E2
4X
M
SOLDERING FOOTPRINT*
1.90 0.63
8X
L
8
8X
b 0.10 C A B 0.05 C
NOTE 3 PACKAGE OUTLINE
e BOTTOM VIEW
1.61 1
3.30
0.50 PITCH
0.30
8X DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Flex-Mode is protected by U.S. Patent 6683441; other patents pending.
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