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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1Gb NAND FLASH
HY27SF081G2A HY27SF161G2A
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.3 / Nov. 2006 1
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory Revision History
Revision No.
0.01 Initial Draft. 1) Change AC Conditions table 2) Change DC and Operating Characteristics
Test Conditions (ICC1) Before After Test Conditions (IOL) VOL=0.1V VOL=0.2V
History
Draft Date
Mar. 16. 2006
Remark
Preliminary
tRC=30ns,
CE=VIL, IOUT=0mA
tRC=50ns,
CE=VIL, IOUT=0mA Typ (ICC1. ICC2, ICC3)
0.1
Before After
Max (ICC1. ICC2, ICC3) 30 20
Apr. 19. 2006
Preliminary
15 10
3) Change AC Timing Characteristics 4) Correct Supply Vlotage
Before After
Vcc=1.65 to 1.95V Vcc=1.70 to 1.95V May. 18. 2006 Preliminary
0.2
1) Change NOP 1) Change 1Gb Package Type - FBGA package is added
0.3
- Figure & dimension are changed 2) Delet Preliminary 3) Correct copy back function
Nov. 23. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities FAST BLOCK ERASE - Block erase time: 2ms (Typ.) STATUS REGISTER ELECTRONIC SIGNATURE - 1st cycle: Manufacturer Code - 2nd cycle: Device Code SUPPLY VOLTAGE - VCC = 1.7 to 1.95V : HY27SFxx1G2A Memory Cell Array = (2K+64) Bytes x 64 Pages x 1,024 Blocks = (1K+32) Words x 64 Pages x 1,024 Blocks PAGE SIZE - x8 device : (2K+64 spare) Bytes : HY27SF081G2A - x16 device : (1K+32 spare) Words : HY27SF161G2A DATA RETENTION - 100,000 Program/Erase cycles (with 1bit/528byte ECC) - 10 years Data Retention PACKAGE - HY27SF(08/16)1G2A-T(P) : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - HY27SF(08/16)1G2A-T (Lead) - HY27SF(08/16)1G2A-TP (Lead Free) - HY27SF081G2A-S(P) : 48-Pin USOP1 (12 x 17 x 0.65 mm) - HY27SF081G2A-S (Lead) - HY27SF081G2A-SP (Lead Free) - HY27SF081G2A-F(P) : 63-Ball FBGA (9 x 11 x 1.0 mm) - HY27SF081G2A-F (Lead) - HY27SF081G2A-FP (Lead Free) - 3rd cycle: Internal chip number, Cell Type, Number of Simultaneously Programmed Pages. - 4th cycle: Page size, Block size, Organization, Spare size SERIAL NUMBER OPTION CHIP ENABLE DON'T CARE - Simple interface with microcontroller
BLOCK SIZE - x8 device: (128K + 4K spare) Bytes - x16 device: (64K + 2K spare) Words PAGE READ / PROGRAM - Random access: 25us (max.) - Sequential access: 50ns (min.) - Page program time: 200us (typ.) COPY BACK PROGRAM MODE - Fast page copy without external buffering CACHE PROGRAM - Internal (2048+64) Byte buffer to improve the program throughput
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash 1. SUMMARY DESCRIPTION
The Hynix HY27SF(08/16)1G2A series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 1.8V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modify operations can be locked using the WP input pin or using the extended lock block feature described later. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. Even the write-intensive systems can take advantage of the HY27SF(08/16)1G2A extended reliability of 100K program/ erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. The chip could be offered with the CE don't care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The cache program feature allows the data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when consecutive pages have to be streamed out. The HYNIX HY27SF(08/16)1G2A series is available in 48 - TSOP1 12 x 20 mm, 48 - USOP 12 x 17 mm, FBGA 9 x 11 mm.
1.1 Product List
PART NUMBER HY27SF081G2A HY27SF161G2A ORIZATION x8 x16 VCC RANGE 1.7V - 1.95 Volt PACKAGE 63FBGA / 48TSOP1 / 48USOP1 48TSOP1
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8 IO7 - IO0 CLE ALE CE RE WE WP R/B Vcc Vss NC
Data Inputs / Outputs (x16 Only) Data Inputs / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection
Table 1: Signal Names
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 2. 48TSOP1 Contactions, x8 and x16 Device
Figure 3. 48USOP1 Contactions, x8
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 4. 63FBGA Contactions, x8 Device (Top view through package)
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name IO0-IO7 IO8-IO15(1) Description DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CHIP ENABLE This input controls the selection of the device. When the device is busy CE low does not deselect the memory. WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. SUPPLY VOLTAGE The VCC supplies the power for all the operations (Read, Write, Erase). GROUND NO CONNECTION
CLE
ALE
CE
WE
RE
WP R/B VCC VSS NC
Table 2: Pin Description
NOTE: 1. For x16 version only 2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A8 A12 A20
IO1 A1 A9 A13 A21
IO2 A2 A10 A14 A22
IO3 A3 A11 A15 A23
IO4 A4 L
(1)
IO5 A5 L
(1)
IO6 A6 L
(1)
IO7 A7 L(1) A19 A27
A16 A24
A17 A25
A18 A26
Table 3: Address Cycle Map(x8)
NOTE: 1. L must be set to Low. IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A8 A11 A19 IO1 A1 A9 A12 A20 IO2 A2 A10 A13 A21 IO3 A3 L(1) A14 A22 IO4 A4 L(1) A15 A23 IO5 A5 L(1) A16 A24 IO6 A6 L(1) A17 A25 IO7 A7 L(1) A18 A26 IO8-IO15 L(1) L(1) L(1) L(1)
Table 4: Address Cycle Map(x16)
NOTE: 1. L must be set to Low.
FUNCTION READ READ FOR COPY-BACK READ ID RESET PAGE PROGRAM COPY BACK PGM BLOCK ERASE READ STATUS REGISTER CACHE PROGRAM RANDOM DATA INPUT RAMDOM DATA OUTPUT CACHE READ START CACHE READ EXIT
1st CYCLE 00h 00h 90h FFh 80h 85h 60h 70h 80h 85h 05h 00h 34h
2nd CYCLE 30h 35h 10h 10h D0h 15h E0h 31h -
3rd CYCLE -
4th CYCLE -
Acceptable command during busy
Yes
Yes
Table 5: Command Set
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
CLE H L H L L L L X X X X
ALE L H L H L L L X X X X
CE L L L L L L(1) L X X X H
WE Rising Rising Rising Rising Rising H H X X X X
RE H H H H H Falling H X X X X
WP X X H H H X X H H L 0V/Vcc Read Mode
MODE Command Input Address Input(4 cycles) Command Input Address Input(4 cycles)
Write Mode Data Input
Sequential Read and Data Output During Read (Busy) During Program (Busy) During Erase (Busy) Write Protect Stand By
Table 6: Mode Selection
NOTE: 1. With the CE high during latency time does not stop the read operation
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash 2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 6 and table 13 for details of the timings requirements. Command codes are always applied on IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. To insert the 28 addresses needed to access the 1Gbit 4 clock cycles (x8 version) are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 7 and table 13 for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure 8 and table 13 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 9,10,12,13 and table 13 for details of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash 3. DEVICE OPERATION
3.1 Page Read.
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with four address cycles. In two consecutive read operations, the second one does need 00h command, which four address cycles and 30h command initiates that operation. Second read operation always requires setup command if first read operation was executed using also random data out command. Two types of operations are available: random read. The random read mode is enabled when the page address is changed. The 2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 50ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. Random data output is not available in cache read.
3.2 Page Program.
The device is programmed basically by page, but it does allow multiple partial page programming of a word or consecutive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array (X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array (X8 device:1time/16byte ,X16 device:1time/8word). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2112 bytes (X8 device) or 1056 words (X16 device) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data input command (85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The P/E/R Controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 14 details the sequence.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A18 to A27 (X8) or A17 to A26 (X16) is valid while A12 to A17 (X8) or A11 to A16 (X16) are ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the P/E/R controller handles erase and erase-verify. Once the erase process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 18 details the sequence.
3.4 Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copyingprogram with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or 1056word (X16 device) data into the internal data buffer. As soon as the device returns to Ready state, Copy Back command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 16. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation." Figure 16 shows the command sequence for the copy-back operation. The Copy Back Program operation requires three steps: 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). This operation copies all 2KBytes from the page into the Page Buffer. 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 4bus cycles to input the target page address. The value for A27 (x8) from second to the last page address must be same as the value given to A27 (x8) in first address. 3. Then the confirm command is issued to start the P/E/R Controller. Note: 1. On the same plane. 2. It's prohibited to operate copy-back program from an odd address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page (target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 14 for specific Status Register definitions, and Figure 10 for specific timings requirements . The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the 1st cycle (ADh), and 2nd cycle (the device code) and 3rd cycle ID, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 19 shows the operation sequence, while Tables 16 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.8 Cache program
Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (X16 device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. After writing the first set of data up to 2112byte (X8 device) or 1056word (X16 device) into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is input to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache- Busy status bit (I/O 6). Pass/fail status of only the previous page is available upon the return to Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked. See Fig. 17 for more details. NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. tPROG=Program time for the last page + Program time for the (last-1)page - (Program command cycle time + Last page data loading time)
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.9 Cache Read
Cache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page must be at page start (A<10:0>=00h) : in this way after 1st latency time (tr) , automatic data download will be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for x8 device (50us for x16 device). Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache read) user can check operation status using : - R/B ( `0' means latency ongoing, download not possible, `1' means download of n page possible, even if device in ternally is active on n+1 page - Status register (SR<6> behave like R/B, SR<5> is `0' when device is internally reading and `1' when device is idle) To exit cache read operation, a cache read exit command (34h) must be issued. This command can be given any time (both device idle and reading). If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time shorter then tRBSY before becoming again idle and ready to accept any further commands. Figure 21 describes how to handle Cache Read through Status register . If user reads last byte/word of the memory array, then he has to stop by giving a cache read exit command. In general, if user wants to terminate a cache read, then he must give a cache read exit command (or reset command) before starting any new operation. Random data output is not available in cache read. Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash 4. OTHER FEATURES
4.1 Data Protection for Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V (1.8V version). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in Figure 25. The two-step command sequence for program/erase provides additional software protection. If the power is dropped during the ready read/write/erase operation, Power protection function may not guaranteed the data. Power protection function is only available during the power on/off sequence.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-back, cache program and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). It returns to high when the P/E/R controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Figure 26). Its value can be determined by the following guidance.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter Valid Block Number
Symbol NVB
Min 1004
Typ
Max 1024
Unit Blocks
Table 7: Valid Blocks Number
NOTE: 1. The 1st block is guaranteed to be a valid block up to 1K cycles with ECC. (1bit/528bytes)
Symbol
Parameter Ambient Operating Temperature (Temperature Range Option 1) Ambient Operating Temperature (Industrial Temperature Range) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage
Value 1.8V 0 to 70 -40 to 85 -50 to 125 -65 to 150 -0.6 to 4.6 -0.6 to 4.6
Unit V V
TA TBIAS TSTG VIO(2) Vcc
Table 8: Absolute maximum ratings
NOTE: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 5 : Block Diagram
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter Sequential Read Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Leve Output Low Current (R/B)
Symbol
Test Conditions tRC=50ns CE=VIL, IOUT=0mA CE=VIH, WP=0V/Vcc CE=Vcc-0.2, WP=0V/Vcc VIN=0 to Vcc (max) VOUT =0 -to Vcc (max) IOH=-100uA IOL=100uA VOL=0.2V
1.8Volt Min Vccx0.8 -0.3 Vcc-0.1 3 Typ 10 10 10 10 4 Max 20 20 20 1 50 10 10 Vcc+0.3 Vccx0.2 0.1 -
Unit
Operating Current
ICC1 ICC2 ICC3 ICC4 ICC5 ILI ILO VIH VIL VOH VOL IOL (R/B)
mA mA mA mA uA uA uA V V V V mA
Table 9: DC and Operating Characteristics
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (1.7V - 1.95V)
Value 1.8Volt 0V to Vcc 5ns Vcc / 2 1 TTL GATE and CL=30pF
Table 10: AC Conditions
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Item Input / Output Capacitance Input Capacitance
Symbol CI/O CIN
Test Condition VIL=0V VIN=0V
Min -
Max 10 10
Unit pF pF
Table 11: Pin Capacitance (TA=25C, F=1.0MHz)
Parameter Program Time Dummy Busy Time for Cache Program Dummy Busy Time for Cache Read Number of partial Program Cycles in the same page Block Erase Time Main Array Spare Array
Symbol tPROG tCBSY tRBSY NOP NOP tBERS
Min -
Typ 200 3 5 2
Max 700 700 4 4 3
Unit us us us Cycles Cycles ms
Table 12: Program / Erase Characteristics
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter
CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Address to Data Loading Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output High Z CE High to Output High Z RE High Hold Time Output High Z to RE low CE Access Time WE High to RE low RE or CE High to Output Hold Device Resetting Time (Read / Program / Erase) Write Protection time
Symbol
tCLS tCLH tCS tCH tWP tALS tALH tADL(4) tDS tDH tWC tWH tR tAR tCLR tRR tRP tWB tRC tREA tRHZ tCHZ tREH tIR tCEA tWHR tOH tRST tWW(3)
1.8Volt Min
25 10 35 10 25 25 10 100 20 10 45 15 25 10 10 20 25 100 50 30 50 50 15 0 45 60 10 5/10/500(1) 100
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns us ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns
Table 13: AC Timing Characteristics
NOTE: 1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us 2. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 3. Program / Erase Enable Operation : WP high to WE High. Program / Erase Disable Operation : WP Low to WE High. 4. tADL is the time from the WE rising edge of final address cycle to the WE rising of first data cycle.
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
IO 0 1 2 3 4 5 6 7
Pagae Program Pass / Fail NA NA NA NA Ready/Busy Ready/Busy Write Protect
Block Erase Pass / Fail NA NA NA NA Ready/Busy Ready/Busy Write Protect
Cache Program Pass / Fail (N) Pass / Fail (N-1) NA NA NA P/E/R Controller Bit Cache Register Free Write Protect
Read NA NA NA NA NA Ready/Busy Ready/Busy Write Protect
Cache Read
CODING Pass: `0' Fail: `1' Don't care -
P/E/R Controller Bit Ready/Busy
Active: `0' Idle: `1' Busy: `0' Ready': `1' Protected: `0' Not Protected: `1'
Table 14: Status Register Coding
DEVIIDENTIFIER CYCLE 1st 2nd 3rd 4th DESCRIPTION Manufacturer Code Device Identifier Internal chip number, cell Type, Number of Simultaneously Programmed pages. Page size, spare size, Block size, Organization
Table 15: Device Identifier Coding
1st cycle 2nd cycle 3rd Code (Manufacture Code) (Device Code) ADh ADh A1h B1h 80h 80h
Part Number HY27SF081G2A HY27SF161G2A
Voltage 1.8V 1.8V
Bus Width x8 x16
4th Code 15h 55h
Table 16: Read ID Data Table
Rev 0.3 / Nov. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Description Die / Package 1 2 4 Reserved Single Level 2x Multi-level Reserved Reservedl 1 2 3 4 Not Support Support Not Support Support 0 1
IO7
IO6
IO5 IO4
IO3 IO2
IO1 IO0 0 0 1 1 0 1 0 1
String Type
0 0 1 1 0 0 1 1 0 1 0 1 0 1
0 1 0 1
Number of Simultaneously Programmed Pages Interleave Program Between different dice Write Cache
Table 17: 3rd Byte of Device Idendifier Description
Description Page Size (Without Spare Area) Spare Area Size (Byte / 512 Byte) Serial Access Time 1KB 2KB 4KB Reserved 8 16 50ns 30ns 25ns Reserved 64KB 128KB 256KB 512KB X8 X16
IO7
IO6
IO5-4
IO3
IO2
IO1-0 0 0 1 1 0 1 0 1
0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1
Block Size (Without Spare Area) Organization
Table 18: 4th Byte of Device Identifier Description
Rev 0.3 / Nov. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 6: Command Latch Cycle
Figure 7: Address Latch Cycle
Rev 0.3 / Nov. 2006
25
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 8. Input Data Latch Cycle
tCEA
CE
tREA tREH tRP tCHZ* tREA tREA tOH
RE
tRHZ tRHZ* tOH Dout
I/Ox
tRR
Dout tRC
Dout
R/B
Notes : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
Figure 9: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
Rev 0.3 / Nov. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
tCLR
CLE
t CLS tCS tCLH
CE
tCH tWP
WE
tWHR
tCEA
tH tCHZ
RE
tDS tDH tIR tREA tH tRH Status Output
I/Ox
70h
Figure 10: Status Read Cycle
Figure 11: Read Operation (Read One Page)
Rev 0.3 / Nov. 2006
27
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 12: Read Operation intercepted by CE
Rev 0.3 / Nov. 2006
28
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 13 : Random Data output
Rev 0.3 / Nov. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 14: Page Program Operation
Rev 0.3 / Nov. 2006
30
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 15 : Random Data In
Rev 0.3 / Nov. 2006
31
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 16 : Copy Back Program
Rev 0.3 / Nov. 2006
32
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 17 : Cache Program
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33
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 18: Block Erase Operation (Erase One Block)
Figure 19: Read ID Operation
Rev 0.3 / Nov. 2006
34
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 20: start address at page start :after 1st latency uninterrupted data flow
Figure 21: exit from cache read in 5us when device internally is reading
Rev 0.3 / Nov. 2006 35
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
System Interface Using CE don't care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND Flash to make CE don't care read operation was disabling of the automatic sequential read function.
Figure 22: Program Operation with CE don't-care.
Figure 23: Read Operation with CE don't-care.
Rev 0.3 / Nov. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 24: Reset Operation
Figure 25: Power On and Data Protection Timing
VTH = 1.5 Volt for 1.8 Volt Supply devices
Rev 0.3 / Nov. 2006
37
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 26: Ready/Busy Pin electrical specifications
Rev 0.3 / Nov. 2006
38
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte/ 1st Word in the spare area of the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 27. The 1st block, which is placed on 00h block address is guaranteed to be a valid block. Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block.
See the "Copy Back Program" section for more details.
Refer to Table 19 for the recommended procedure to follow if an error occurs during an operation. Operation Erase Program Read Recommended Procedure Block Replacement Block Replacement or ECC (with 1bit/528byte) ECC (with 1bit/528byte)
Table 19: Block Failure
Figure 27: Bad Block Management Flowchart
Rev 0.3 / Nov. 2006 39
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 28~31)
Figure 28: Enable Programming
Figure 29: Disable Programming
Rev 0.3 / Nov. 2006
40
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 30: Enable Erasing
Figure 31: Disable Erasing
Rev 0.3 / Nov. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 32: 48pin-TSOP1, 12 x 20mm, Package Outline
millimeters
Min Typ Max 1.200 0.050 0.980 0.170 0.100 0.150 1.030 0.250 0.200 0.100 11.910 19.900 18.300 12.000 20.000 18.400 0.500 0.500 0 0.680 5 12.120 20.100 18.500
Symbol A A1 A2 B C CP D E E1 e L alpha
Table 20: 48pin-TSOP1, 12 x 20mm, Package Mechanical Data
Rev 0.3 / Nov. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 33. 48pin-USOP1, 12 x 17mm, Package Outline
Symbol A A1 A2 B C C1 CP D D1 E e alpha
millimeters
Min 0 0.470 0.130 0.065 0.450 16.900 11.910 15.300 0 Typ 0.050 0.520 0.160 0.100 0.650 17.000 12.000 15.400 0.500 8 Max 0.650 0.080 0.570 0.230 0.175 0.750 0.100 17.100 12.120 15.500
Table 21: 48pin-USOP1, 12 x 17mm, Package Mechanical Data
Rev 0.3 / Nov. 2006
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HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure 34. 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Outline
NOTE: Drawing is not to scale.
Symbol A A1 A2 b D D1 D2 E E1 E2 e FD FD1 FE FE1 SD SE
Millimeters
Min 0.80 0.25 0.55 0.40 8.90 Typ 0.90 0.30 0.60 0.45 9.00 4.00 7.20 11.00 5.60 8.80 0.80 2.50 0.90 2.70 1.10 0.40 0.40 Max 1.00 0.35 0.65 0.50 9.10
10.90
11.10
Table 22: 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Mechanical Data
Rev 0.3 / Nov. 2006 44
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash MARKING INFORMATION - TSOP1/USOP
P a ck a g M a rk in g E x a m p le
K
O
R
TSO P1 / USOP
H
Y
2
7
S
F
x
x
1
G
2
A
x
x
x
x
Y
W
W
x
x
- h y n ix - KOR - H Y27SFxx1G2A xxxx H Y : H yn ix 2 7 : N A N D Fla sh S : P ow e r S u pp ly F : C la ssifica tion x x : B it O rg a n iza tion 1 G : D e n sity 2 : M o de A : V e rsion x : P acka ge T yp e x : P acka g e M a te ria l x : O p eratin g T e m perature x : B ad B lo ck
: H yn ix S ym b ol : O rigin C o u n try : P a rt N u m b e r
: S (1 .8 V ) : S in g le Le vel C e ll+ S in gle D ie + La rge B lo ck : 0 8 (x8 ), 1 6 (x1 6) : 1 G bit : 1 n C E & 1 R /n B ; S e qu e n tia l R ow R e ad D isa ble : 2 n d G e n era tion : T (4 8 -T S O P 1 ), S (4 8 -U S O P ) : B lank(N o rm al), P(Lead Free) : C (0 ~ 7 0 ), I(-4 0 ~ 8 5 ) : B (In clu d ed B ad B lo ck), S (1 ~ 5 B ad B lo ck), P (A ll G oo d B lock)
- Y : Y e ar (ex: 5= year 20 0 5 , 06 = year 20 0 6 ) - w w : W o rk W eek (e x: 12 = w ork w eek 12 ) - x x : P roce ss C o d e N o te - C a p ita l L e tte r - S m a ll L e tte r : Fixed Ite m : N o n -fixe d Item
Rev 0.3 / Nov. 2006
45
HY27SF(08/16)1G2A Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash MARKING INFORMATION - FBGA
P a ck a g M a rk in g E x a m p le
K
O
R
FBG A
H
Y
2
7
S
F
0
8
1
G
2
A
x
x
x
x
Y
W
W
x
x
- h y n ix - KOR - H Y27SFxx1G2A xxxx H Y : H yn ix 2 7 : N A N D Fla sh S : P ow e r S u pp ly F : C la ssifica tion 0 8 : B it O rg an iza tion 1 G : D e n sity 2 : M o de A : V e rsion x : P acka ge T yp e x : P acka g e M a te ria l x : O p e ratin g T e m pe ra tu re x : B ad B lo ck
: H yn ix S ym b ol : O rigin C o u n try : P a rt N u m b e r
: S (1 .8 V ) : S in g le Le vel C e ll+ S in gle D ie + La rge B lo ck : 0 8 (x8 ) : 1 G bit : 1 n C E & 1 R /n B ; S e qu e n tia l R ow R e ad D isa ble : 2 n d G e n era tion : F (6 3 FB G A ) : B la n k(N o rm a l), P (L e ad F re e ) : C (0 ~ 7 0 ), I(-4 0 ~ 8 5 ) : B (In clu d ed B ad B lo ck), S (1 ~ 5 B ad B lo ck), P (A ll G oo d B lock)
- Y : Y e ar (ex: 5= year 20 0 5 , 06 = year 20 0 6 ) - w w : W o rk W eek (e x: 12 = w ork w eek 12 ) - x x : P roce ss C o d e N o te - C a p ita l L e tte r - S m a ll L e tte r : Fixed Ite m : N o n -fixe d Item
Rev 0.3 / Nov. 2006
46

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