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X RP 7 7 1 4
Quad Channel Digital PWM Step Down Controller
February 2010 Rev. 1.1.3
GENERAL DESCRIPTION
The XRP7714 is a quad-output pulse-width modulated (PWM) step-down DC-DC controller with a built-in LDO for standby power and GPIOs. The device provides a complete power management solution in one IC and is fully programmable via an I2C serial interface. Independent Digital Pulse Width Modulator (DPWM) channels regulate output voltages and provide all required protection functions such as current limiting and over-voltage protection. Each output voltage can be programmed from 0.9V to 5.1V without the need of an external voltage divider. The wide range of the programmable DPWM switching frequency (from 300 KHz to 1.5 MHz) enables the user to optimize between efficiency and component size. Input voltage range is from 4.75V to 25V. An I2C bus interface is provided to program the IC as well as to communicate with the host for fault reporting and handling, power rail parameters monitoring, etc. The device offers a complete solution including independently programmable: soft-start, softstop, start-up delay and ramp of each PWM regulator.
APPLICATIONS
* Multi Channel Power Supplies * Audio-Video Equipments * Industrial & Telecom Equipments * Processors & DSPs Based Equipments
FEATURES
* 4 x 5A Channel Step Down Controller - Programmable Output Voltage 0.9V-5.1V - Programmable 1.5MHz DPWM Frequency - Integrated FETs Drivers * 4.75V-25V Single Input Voltage Range * Up to 6 Reconfigurable GPIO Pins * Fully Programmable via I2C Interface * Independent Digital Pulse Width Modulator (DPWM) channels * Complete Monitoring and Reporting * Complete Power Up/Down Sequencing * Full On Board Protection OTP, UVLO, OCP and OVP * Built-in 3.3V/5V LDO * Configuration Development Tools * Green/Halogen Free 40-pin TQFN
TYPICAL APPLICATION DIAGRAM
Fig. 1: XRP7714 Application Diagram
Exar Corporation 48720 Kato Road, Fremont CA 94538, USA
www.exar.com Tel. +1 510 668-7000 - Fax. +1 510 668-7001
X RP 7 7 1 4
Quad Channel Digital PWM Step Down Controller
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VCCD, LDOOUT, GLx, VOUTx ..................................... 6V VDD..................................................................... 2.0V VIN1, VIN2 ............................................................ 27V LXx .............................................................. -1V to 27V Logic Inputs ............................................................. 6V BSTx, GHx .................................................... VLXx + 6V Storage Temperature .............................. -65C to 150C Lead Temperature (Soldering, 10 sec) ................... 300C
OPERATING RATINGS
Operating Input Voltage VINX ...................... 4.75V to 25V Junction Temperature Range ....................-40C to 125C Thermal Resistance JA ...................................... 18C/W
ELECTRICAL SPECIFICATIONS
Specifications with standard type are for an Operating Junction Temperature of TJ = 25C only; limits applying over the full Operating Junction Temperature range are denoted by a "*". Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Unless otherwise indicated, VIN1 = 4.75V to 25V, VIN2 = 4.75V to 25V.
Quiescent Current
Parameter VIN Supply Current in STANDBY VIN Supply Current in SHUTDOWN VIN Supply Current Min. Typ. 9 Max. Units mA Conditions LDOOUT enabled (no load) No switching converter channels enabled I2C communication active Switching frequency = 400kHz EN=0V, VIN15.2V, VIN225V 4 channels running, GH and GH = 1nF load each VIN=12V, Switching frequency = 300kHz 4 channels running, GH and GH = 1nF load each VIN=12V, Switching frequency = 1MHz
180 28
A mA
VIN Supply Current
50
mA
Step Down Controllers
Parameter VOUT Regulation Accuracy VOUT regulation range VOUT set point resolution VOUT set point resolution VOUT Input Current VOUT Input Resistance Min. -20 -40 0.9 50 100 100 120 nA k Typ. Max. 20 40 5.1 Units mV mV * * * Conditions 0.9V VOUT 2.5V 2.6V VOUT 5.1V Programmable range of each channel1 0.9V VOUT 2.5V 2.6V VOUT 5.1V 0.9V < VOUT <= 2.5V 2.6V VOUT 5.1V
Note 1: Voltages above 5.1V can be obtained by using an external voltage divider.
Low Drop-out Regulator
Parameter LDOOUT Output Voltage LDO=LOW LDOOUT Output Voltage Min. 3.15 4.75 Typ. 3.3 5.0 Max. 3.45 5.25 Units V V * * Conditions 4.75VVIN125V 0mA(c) 2010 Exar Corporation
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Parameter LDO=HIGH LDOOUT Short Circuit Current Limit 110 220 mA * Min. Typ. Max. Units Conditions 0mAAuxiliary ADCs
Parameter Linearity Error Integral Linearity Error Differential Input Dynamic Range VIN1 Input Dynamic Range VIN2 -1 4.75 4.75 Min. Typ. Max. 2 1 25 25 Units LSB LSB V V * * Conditions
Isense ADC
Parameter ADC LSB Input Dynamic Range 0 Min. Typ. 5 -320 Max. Units mV mV Conditions Referred to the input
PWM Generators and Oscillator
Parameter Output frequency range Output Frequency Accuracy Channel-to-channel phase shift Minimum On Time Min. 300 -10 90 40 13 Dead Time Adjustment Step 1.5 CLOCK IN Synchronization Range Maximum Duty Cycle2 ns Typ. Max. 1500 10 Units kHz % deg ns ns 1nF of gate capacitance Switching frequency = 300kHz 10% to 90% duty cycle, Frequency dependant; refer to the graph in performance characteristic section Switching frequency = 1.5MHz 10% to 90% duty cycle, Frequency dependant; refer to the graph in performance characteristic section * * * Switching frequency = 300kHz Switching frequency = 1.5MHz * Conditions Steps defined in the table in the PWM Switching Frequency Setting section below
-5 86 78
5
% % %
Note 2: The maximum duty cycle represents the maximum duty cycle commanded by the DPWM, is guaranteed by design, and internally set to ensure proper sampling of the current during the off-time.
Digital Input/Output Pins (GPIO0-GPIO5)
3.3V CMOS logic compatible, 5V tolerant. Parameter Input Pin Low Level Input Pin High Level Input Pin Leakage Current Input pin Capacitance Output Pin Low Level Output Pin High Level Output Pin High Level (no load) 2.4 3.3 3.6 5 0.4 2.0 10 Min. Typ. Max. 0.8 Units V V A pF V V V * * * ISINK=1mA ISOURCE=1mA ISOURCE=0mA * * * VIO=3.3V Conditions
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I2C Specification
Parameter I2C Speed Input Pin Low Level, VIL Input Pin High Level, VIH Hysteresis of Schmitt Trigger Inputs, VHYS Output Pin Low Level (open drain or collector) VOL Input Leakage Current Output Fall Time from VIHMIN to VILMAX Capacitance for each I/O Pin Note 3: Cb is the capacitance of one bus in pF -10 20+0.1Cb
3
Min.
Typ.
Max. 400 1.0
Units kHz V V V
Conditions Based upon I2C master clock
2.31 0.165 0.4 10 250 10
V A ns pF
ISINK=3mA Input is between 0.33V and 2.31V With a bus capacitance from 10pF to 400pF
Gate Drivers
Parameter GH, GL Rise and Fall Time GH, GL Pull-up On-State Output Resistance GH, GL Pull-down On-State Output Resistance GH, GL Pull-down Off-State Output Resistance Min. Typ. 30 6 3 50 Max. Units ns k VIN=VCCD=0V Conditions At 10% to 90% of full scale pulse. 1nF Cload
(c) 2010 Exar Corporation
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BLOCK DIAGRAM
Fig. 2: XRP7714 Block Diagram
(c) 2010 Exar Corporation
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PIN ASSIGNMENT
Fig. 3: XRP7714 Pin Assignment
PIN DESCRIPTION
Name VIN1 Pin Number 39 Description Power source for the internal linear regulators to generate VCCA, VDD and the Standby LDO (LDOOUT). Place a decoupling capacitor close to the controller IC. Also used in UVLO1 fault generation - if VIN1 falls below the user programmed limit, all channels are shut down. The VIN1 pin needs to be tied to VIN2 on the board with a short trace. If the Vin2 pin voltage falls below the user programmed UVLO VIN2 level all channels are shut down. The VIN2 pin needs to be tied to VIN1 on the board with a short trace. Output of the internal 5V LDO. This voltage is internally used to power analog blocks. Note that a compensation capacitor should be used on this pin (see application note). Gate Drive input voltage. This is not an output voltage. This pin can be connected to VCCA to provide power for the Gate Drive. VCCD should be connected to VCCA with the shortest possible trace and decouple with a minimum 1F capacitor. Alternatively, VCCD could be connected to an external supply (not greater than 5V). Power Ground. Ground connection for the low side gate driver. Output of the internal 1.8V LDO. A decoupling capacitor should be placed between AVDD and AGND close to the chip (with short traces). Input for powering the internal digital logic. This pin should be connected to AVDD. Digital Ground. This pin should be connected to the ground plane at the exposed pad with a separate trace.
VIN2 VCCA
38 37
VCCD PGND1- PGND4 AVDD DVDD DGND
26 36,31,16,21 1 2 10
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Name AGND GL1-GL4 GH1-GH4 Pin Number 11 17,22,30,35 19,24,28,33 Description Analog Ground. This pin should be connected to the ground plane at the exposed pad with a separate trace Output pin of the low side gate driver. Connect directly to the respective gate of an external N-channel MOSFET. Output pin of the high side gate driver. Connect directly to the respective gate of an external N-channel MOSFET. Lower supply rail for the high-side gate driver (GHx). Connect this pin to the switching node at the junction between the two external power MOSFETs and the inductor. These pins are also used to measure voltage drop across bottom MOSFETs in order to provide output current information to the control engine. High side driver supply pin(s). Connect BST to an external boost diode and a capacitor as shown in the front page diagram. The high side driver is connected between the BST pin and LX pin. These pins can be configured as inputs or outputs to implement custom flags, power good signals and enable/disable controls. A GPIO pin can also be programmed as an input clock synchronizing IC to external clock. Refer to the "GPIO Pins" Section and the "External Clock Synchronization" Section for more information. I2C serial interface communication pins. These pins can be re-programmed to perform GPIO functions in applications when I2C bus is not used. Voltage sense. Connect to the output of the corresponding power stage. Output of the Standby LDO. It can be configured as a 5V or 3.3V output. A compensation capacitor should be used on this pin [see Application Note]. If ENABLE is pulled high, the chip powers up (logic reset, registers configuration loaded, etc.). If pulled low for longer than 100us, the XRP7714 is placed into shutdown. Analog Ground. Connect to analog ground (as noted above for pin 11).
LX1-LX4
34,29,23,18
BST1-BST4
32,27,20,25
GPIO0-GPIO3 GPIO4_SDA, GPIO5_SCL VOUT1-VOUT4 LDOOUT ENABLE AGND
3,4,5,6
7,8 12,13,14,15 40 9 Exposed Pad
ORDERING INFORMATION
Part Number XRP7714ILB- F XRP7714ILBTR-F XRP7714EVB Temperature Range Marking Package Packing Quantity Bulk 3K/Tape & Reel Note 1 Halogen Free Halogen Free Note 2 XRP7714ILB 40-pin TQFN -40CTJ+125C YYWW X XRP7714ILB 40-pin TQFN -40CTJ+125C YYWW X XRP7714 Evaluation Board
"YY" = Year - "WW" = Work Week - "X" = Lot Number
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TYPICAL PERFORMANCE CHARACTERISTICS
All data taken at TJ = TA = 25C, unless otherwise specified - Schematic and BOM from Application Information section of this datasheet.
1
0.9
3.3V 2.5V 1.8V
Efficiency
0.8
1.0V
0.7
0.6
0.5 0 1 2 3 4
OutputCurrent(Amps)
Fig. 4: 12Vin Efficiency: Single Channel 300kHz - Channels not in use are disabled FET: Si4944; Inductor: 744314xxx 7x7x5mm
Fig. 5: 12Vin Efficiency: Single Channel 300kHz - Channels not in use are disabled FET: FDS8984; Inductor: 744310200 7x7x3mm
100%
1
2.5V
90%
1.8V 1.2V 1.0V
0.9
3.3V 1.8V
Efficiancy
Efficiency
80%
0.8
1.2V 1.0V
70%
0.7
60%
0.6
50%
0.5
0
1
2
3
4
5
0
1
2
3
4
OutputCurrent(Amps)
OutputCurrent(Amps)
Fig. 6: 5Vin Efficiency: Single Channel 300kHz - Channels not in use are disabled FET: Si4944; Inductor: 744314xxx 7x7x5mm
Fig. 7: 5Vin Efficiency: Single Channel 300kHz - Channels not in use are disabled FET: FDS8984; Inductor: 744310200 7x7x3mm
100%
90%
Efficiency
80%
70%
60%
50% 0 1 2 3 4
OutputCurrentAmps
Fig. 8: 12Vin Combined Efficiency 5V & 3V3 1V8 & 1V@ 5A - 300 kHz FET: FDS8984; Inductor: 744310200 7x7x3mm
Fig. 9: 12Vin Efficiency: Single Channel 1MHz - Channels not in use are disabled FET: FDS8984; Inductor:744310200 7x7x3mm
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200 190 180 170
ISD (A)
ISD (A)
2000 1800 1600 1400 1200 1000 800 600 400 200 0 5 10 VIN (V) 15 20 25 4.7 4.8 4.8 4.9 4.9 VIN (V) 5.0 5.0 5.1 5.1 5.2
160 150 140 130 120 110 100
Fig. 10: Shutdown Current 5.1V to 25V
Fig. 11: Shutdown Current 4.8V to 5.1V
Fig. 12: Simultaneous Start-up CH1:3.3V, CH2:5V, CH3:1V, CH4:1.8V
Fig. 13: Simultaneous Soft-stop CH1:3.3V, CH2:5V, CH3:1V, CH4:1.8V
Fig. 14: Sequential Start-up CH1:3.3V, CH2:5V, CH3:1V, CH4:1.8V
Fig. 15: Sequential Soft-stop VOUT Shutdown=0.8V, 3A load CH1:3.3V, CH2:5V, CH3:1V, CH4:1.8V
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Fig. 16: Sequential Soft-stop VOUT Shutdown=0.8V, 3A load CH1:3.3V, CH2:5V, CH3:1V, CH4:1.8V
Fig. 17: Load Transient Response CH1: Iout (1A/div) CH2:Vout(3.3V)
1.818 1.814 1.81 1.806
1.01
1.006
1.002
Vout
NoLoad
1.798 1.794 1.79 1.786 1.782 40 15 10 35 60 85
Vout
1.802
"FullLoad"
NoLoad
0.998
FullLoad
0.994
0.99 40 15 10 35 60 85
Ambient,DegreesC
Ambient,DegreesC
Fig. 18: Temperature Regulation 1.8V out (1% Vout window)
Fig. 19: Temperature Regulation 1.0V out (1% Vo window)
Fig. 20: Temperature and Voltage Regulation 1.8V out (1% Vout window)
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Quad Channel Digital PWM Step Down Controller
FEATURES AND BENEFITS
General DPWM Benefits:
* Eliminate temperature and time variations associated with passive components in: - Output set point - Feedback compensation - Frequency set point - Under voltage lock out - Input voltage measurement - Gate drive dead time * Tighter parameter frequency set point tolerances including operating - 2 GPIOs can be dedicated to the I2C Interface as required by the customers design * Frequency and Synchronization Capability - Selectable switching frequency between 300kHz and 1.5MHz - Channel to channel phase relationship is a fixed 90 degrees - Main oscillator clock and DPWM clock can be synchronized to external sources - `Master', `Slave' and `Stand-alone' Configurations are possible * Internal MOSFET Drivers - Internal FET drivers (3/6) for each Channel - Built-In Automatic Dead-time adjustment - 30ns Rise and Fall times * GUI (Graphical User Configuration Software: Interface) Design and
* Easy configuration and re-configuration for different Vout, Iout, Cout, and Inductor selection by simply changing internal PID coefficients. No need to change external passives for a new output specification. * Higher integration: Many external circuits can be handled by monitoring or modifying internal registers * Selectable DPWM Frequency frequency and Controller Clock
- In its simplest form only VIN, VOUT, and Iout for each channel is required. The XRP7714 Configuration Software can generate all parts for a system bill of material including: Input Capacitor, FETs, Inductor and Output Capacitor. - Tool calculates configuration register content based upon customer requirements. PID coefficients for correct loop response (for automatic or customized designs) can be generated and sent to the device. - Configurations can be saved and/or recalled - GPIOs can be configured easily and intuitively - Synchronization configuration can be adjusted - Interface can be used for real-time debugging and optimization * Customizing XRP7714 with customer parameters - Once a configuration is finalized it can be sent to EXAR and can reside in pre-programmed parts that customers can order with an individual part number. - Allows parts to be used without I2C interface
Other Benefits:
* A single voltage is needed for regulation [no External LDO required]. * I C interface allows: - Communication with a System Controller or other Power Management devices for optimized system function - Access to modify or read internal registers that control or monitor: - Output Current - Input and Output Voltage - Soft-Start/Soft-Stop Time - `Power Good' - Part Temperature - Enable/Disable Outputs - Over Current - Over Voltage - Temperature Faults - Adjusting fault limits and disabling/enabling faults - Packet Error Checking (PEC) on I2C communication * 6 Configurable GPIO pins, (4 if I C is in use). Pins can be configured in several ways: - Fault reporting (including OCP, OVP, Temperature, Soft-Start in progress, Power Good) - Allows a Logic Level interface with other non-digital IC's or as logic inputs to other devices - Possible to configure as traditional `enable' pin for all 4 outputs
2 2
System Benefits:
* Reliability is enhanced via communication with the system controller which can obtain real time data on an output voltage, input voltage and current. * System processors can communicate with the XRP7714 directly to obtain data or make adjustments to react to circuit conditions * A system process or could also be configured to log and analyze operating history, perform diagnostics and if required, take the supply off-line after making other system adjustments. * If customer field service is a possibility for your end product, parameter reporting and history would provide additional capabilities for troubleshooting or aid in future system upgrades.
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FUNCTIONAL DESCRIPTION AND OPERATION
The XRP7714 is a quad-output digital pulse width modulation (DPWM) controller with integrated gate drivers for the use in synchronous buck switching regulators. Each output voltage can be programmed from 0.9V to 5.1V without the need of an external voltage divider. The wide range of the programmable DPWM switching frequency (from 300kHz to 1.5MHz) enables the user to optimize for efficiency or component sizes. The digital regulation loop requires no external passive components for network compensation. The loop performance does not need to be compromised due to component tolerance, aging, and operating condition. Each digital controller provides a number of safety features, such as over-current protection (OCP) and over-voltage protection (OVP). The chip also provides over-temperature protection (OTP) and under-voltage lock-out (UVLO) for two input voltage rails. The XRP7714 also has up to 6 GPIOs and a Standby Linear Regulator to provide standby power. An I2C bus interface is provided to program the IC as well as to communicate with the host for fault reporting and handling, power rail monitoring, channel enable and disable, Standby LDO voltage reconfiguration, and Standby LDO enable and disable. The XRP7714 offers a complete solution for soft-start and soft-stop. The delay and ramp of each PWM regulator can be independently controlled. During soft-stop, the output voltage ramps down with a programmable slope until it reaches a pre-set value. This pre-set value can be programmed between within zero volts and the target voltage with the same set target voltage resolution.
REGISTER TYPES
There are two types of registers in the XRP7714: read/write registers and read-only registers. The read/write registers are used for the control functions of the IC and can be programmed using configuration non-volatile memory (NVM) or through an I2C command. The read-only registers are for feedback functions such as error/warning flags and for reading the output voltage or current.
NON-VOLATILE CONFIGURATION MEMORY
The non-volatile memory (NVM) in XRP7714 stores the configuration data for the chip and all of the power rails. This memory is normally configured during manufacturing time. Once a specific bit of the NVM is programmed, that bit can never be reprogrammed again [i.e. one-time programmable]. During chip power up, the contents in the NVM are automatically transferred to the internal registers of the chip. Programmed cells have been verified to be permanent for at least 10 years and are highly reliable.
CHIP POWER-UP
The figure below shows the power-up sequence of XRP7714 during the normal operation. The startup stage is divided into three phases. The first phase is the internal LDO power-up phase. The second phase is the configuration transfer phase. The third phase is chip ready phase. The power up sequence is less than 1ms.
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Quad Channel Digital PWM Step Down Controller
Phase 1
VIN1 ENABLE_PIN VCC VDD VDDOK SYS_RESET CONFIG_TRANSFER CHIP_READY
Phase 2
Phase 3
Fig. 21: Power Up Sequence
INTERNAL LDO POWER-UP PHASE - PHASE 1
When the ENABLE pin is set, internal VCC and VDD power up upon the power up of VIN1. Once the bandgap reference is stable and VCC and VDD fall into the acceptable range, an internal VDDOK flag is generated. A SYS_RESET remains low for a few clock cycles to reset all the internal registers. After that the internal CONFIGURATION_TRANSFER signal raises high and the chip transits to the second phase.
CONFIGURATION TRANSFER PHASE - PHASE 2
In this phase, the contents in the configuration memory are transferred to the internal registers. The internal oscillator switches to the programed switching frequency. The GPIO pins are properly configured as either inputs or outputs. If the chip is programmed to run in the I2C mode, GPIO4 and GPIO5 are configured to serve as SDA and SCL for the I2C bus. If chip is programmed to run in the NON-I2C mode, then these two pins can be used as GPIO4 and GPIO5 respectively.
CHIP READY PHASE - PHASE 3
In this phase, the chip is ready for normal operation. An internal CHIP_READY flag goes high and enables the I2C to acknowledge the Host's serial commands. Channels that are configured as always-on channels are enabled. Channels that are configured to be enabled by GPIOs are also enabled if the respective GPIO is asserted.
STANDBY LOW DROP-OUT REGULATOR
This 100mA low drop-out regulator can be programmed as 3.3V or 5V in SET_STBLDO_EN_CONFIG register. Its output is seen on the LDOOUT Pin. This LDO is fully controllable via the Enable Pin (configured to turn on as soon as power is applied), a GPIO, and/or I2C communication. The 5V output setting of the regulator is only available if VIN1 is above 6.5V, and the 3.3V output setting is available for the entire VIN1 range from 4.75 to 25V.
ENABLING, DISABLING AND RESET
The XRP7714 is enabled via raising the ENABLE Pin high. The chip can then be disabled by lowering the same ENABLE Pin. There is also the capability for resetting the Chip via an I2C SOFTRESET Command.
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For enabling a specific channel, there are several ways that this can be achieved. The chip can be configured to enable a channel at start-up as the default configuration residing in the non-volatile configuration memory of the IC. The channels can also be enabled using GPIO pins and/or an I2C Bus serial command. The registers that control the channel enable functions are the SET_EN_CONFIG and SET_CH_EN_I2C.
INTERNAL GATE DRIVERS
The XRP7714 integrates Internal Gate Drivers for all 4 PWM channels. These drivers are optimized to drive both high-side and low side N-MOSFETs for synchronous operations. Both high side and low side drivers have the capability of driving 1nF load with 30ns rise and fall time. The drivers have built-in non-overlapping circuitry to prevent simultaneous conduction of the two MOSFETs. The built-in non-overlapping feature is disabled when the programmable dead time is selected.
PROGRAMMABLE DEAD TIME
The programmable dead time feature provides customers the flexibility to optimize the system performance over PWM switching frequency, efficiency and component selections. There are three registers to control the dead time. The programmable dead time feature is enabled in the SET_CONTROL_BIT_REG register. If disabled, the built-in dead time control inside the driver will take over. The dead time between the turn off of the low side MOSFET and the turn on of high side MOSFET is controlled by the SET_DT_RISE_CHx. On the other hand, the dead time between the turn off of high side MOSFET and the turn on of the low side MOSFET is controlled by SET_DT_FALL_CHx. The actual LSB of the registers is variable depending on the switching frequency. 1 256
FAULT HANDLING
While the chip is operating there are four different types of fault handling: * * * * Under Voltage Lockout (UVLO) monitors the input voltage to the chip, and the chip will shutdown all channels if the voltage drops to critical levels. Over Temperature Protection (OTP) monitors the temperature of the chip, and the chip will shutdown all channels if the temperature rises to critical levels. Over Voltage Protection (OVP) monitors the voltage of channel and will shutdown the channel if it surpasses its voltage threshold. Over Current Protection (OCP) monitors the current of a channel, and will shutdown the channel if it surpasses its current threshold. The channel will be automatically restarted after a 200ms delay.
Under Voltage Lockout (UVLO) There are two locations where the under voltage can be sensed: VIN1 and VIN2. The SET_UVLO_WARN_VINx register that sets the under voltage warning set point condition at 100mV increments. When the warning threshold is reached, the Host is informed via a GPIO or by reading the READ_WARN_FLAG register. The SET_UVLO_TARG_VINx register that controls the under voltage fault set point condition at 100mV increments. This fault condition will be indicated in the READ_FAULT_WARN register.
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Quad Channel Digital PWM Step Down Controller
When an under voltage fault condition occurs (either on VIN1 or VIN2), the fault flag register is set and all of the XRP7714 outputs are shut down. The measured input voltages can be read back using the READ_VIN1 or READ_VIN2 register, and both registers have a resolution of 100mV per LSB. When the UVLO condition clears (voltage rises above the UVLO Warning Threshold), the chip can be configured to automatically restart. VIN1 This is a multi-function pin that provides power to both the Standby Linear Regulator and internal linear regulators to generate VCCA, VDD, and the Standby LDO (LDOUT). It is also used as a UVLO detection pin. If Vin1 falls below its user programmed limit, all channels are shut down. VIN2 VIN2 is required to be tied to VIN1 pin. It can be used as a UVLO detection pin. If VIN2 falls below its user programmed limit, all channels are shut down. Temperature Monitoring and Over Temperature Protection (OTP)
*
Reading the junction temperature
This register allows the user to read back the temperature of the IC. The temperature is expressed in Kelvin with a maximum range of 520K, a minimum of 200K, and an LSB of 5 degrees K. The temperature can be accessed by reading the READ_VTJ register.
*
Over Temperature Warning
There are also warning and fault flags that get set in the READ_OVV_UVLO_OVT_FLAG register. The warning threshold is configurable to 5 or 10 Degrees C below the fault threshold. When the junction temperature reaches 5 or 10 Degrees C below the user defined set point, the overtemperature warning bit [OTPW] gets set in the READ_OVV_UVLO_OVT_FLAG register to warn the user that the IC might go into an over temperature condition (and shutdown all of the regulators).
*
Over Temperature Fault
If the over temperature condition occurs both the OTP and OTPW bits will be set in the READ_OVV_UVLO_OVT_FLAG register and the IC will shut down all channels (but I2C will remain operational). The actual over temperature threshold can be set by the user by using a 7bit SET_THERMAL_SHDN register with an LSB of 5K. If the over temperature fault condition clears, then the IC can be set to restart the chip automatically. The restart temperature threshold can be set by the SET_THERMAL_RESTART register.
OUTPUT VOLTAGE SETTING AND MONITORING
The Output Voltage setting is controlled by the SET_VOUT_TARGET_CHx register. This register allows the user to set the output voltage with a resolution of 50mV for output voltages between 0 and 2.5V and with a resolution of 100mV for output voltages between 2.6V and 5.1V. Output voltages higher than 5.1V can be achieved by adding an external voltage divider network. The output voltage of a particular channel can be read back using the READ_VOUTx register. Output Voltage from 0.9V to 5.1V Per the equation below, for values between 0.9V and 5.1V the output voltage is equal to the binary number stored in the SET_VOUT_TARGET_CHx register multiplied by 50mV. When programming an
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output voltage from 2.6V to 5.1V, odd binary values should be avoided. As a result, the set resolution for an output voltage higher than 2.5V is 100mV. _ Output VOUT Higher Than 5.1V To set the output voltage higher than 5.1V, the user needs to add an external voltage divider. The resistors used in the voltage divider should be below 10k. The SET_VOUT_TARGET_CHx register should be set to 0x32 which is equivalent to an output voltage of 2.5V without the external divider network. The output voltage regulation in this case might exceed 2% due to extra error from the resistor divider. R1 and R2 follows the definition below.
Vout>5.1V
_
_
50
R1
Voutx pin
R2
Fig. 22: External divider network for high output voltage
1 Output Voltage Lower Than 0.9V
_
_
_
50
The XRP7714 can be programmed to regulate an output voltage lower than 0.9V. However, in this case the specification of 20mV output voltage accuracy is not guaranteed.
OVER-VOLTAGE PROTECTION (OVP)
The Over-Voltage Protection (OVP) SET_OVVP_REGISTER sets the over-voltage condition in predefined steps per channel. The over-voltage protection is always active even during soft-start condition. When the over-voltage condition is tripped, the controller will shut down the channel. When the channel is shut down the controller will then set corresponding OVP Fault bits in the READ_OVV_UVLO_OVT_FLAG register. The VOUT OVP Threshold is 150mV to 300mV above nominal VOUT for a Voltage Target of 2.5V or less. For the Voltage Target of 2.6V to 5.1V, the VOUT OVP Threshold is 300mV to 600mV. Once the over-voltage Channel is disabled, the controller will check the SET_FAULT_RESP_CONFIG_LB and SET_FAULT_RESP_CONFIG_HB to determine whether there are any "following" channels that need to be shut down. Any following channel will be disabled when the channel with the Over Voltage Fault is disabled. The channel(s) will remain disabled, until the Host takes action to enable the channel(s). Any of the fault and warning conditions can also be configured to be represented using the general purpose input output pins (GPIO) to use as an interface with non I2C compatible devices. For further information on this topic see the "GPIO Pins" Section. During OVP fault shutdown of the channel, the customer has the option to choose two types of shutdown for each channel. The first shutdown is `passive shutdown' where the IC merely stops outputting pulses. The second shutdown is a `brute force' shutdown where the GL remains on as the channel reaches its discharged voltage. Note that if the `brute force' method is chosen, then GL will permanently remain high until the channel is re-enabled.
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OUTPUT CURRENT SETTING AND MONITORING
XRP7714 utilizes a low side MOSFET Rdson current sensing technique. The voltage drop on Rdson is measured by dedicated current ADC. The ADC results are compared to a maximum current threshold and an over-current warning threshold to generate the fault and warning flags. Maximum Output Current The maximum output current is set by the SET_VIOUT_MAX_CHx register and SET_ISENSE_PARAM_CHx register. The SET_VIOUT_MAX_CHx register is an 8 bit register. Bits [5:0] set the maximum current threshold and bits [7:6] set the over-current warning threshold. The LSB for the current limit register is 5 mV and the allowed voltage range is between 0 and 315mV. To calculate the maximum current limit, the user needs to provide the MOSFET Rdson. The maximum current can be calculated as:
Where Kt is the temperature coefficient of the MOSFET Rdson; Vsense is the voltage across Rdson; IOUTMAX is the maximum output current. Over-Current Warning The XRP7714 also offers an Over-Current warning flag. This warning flag resides in the READ_OVC_FLAG register. The warning flag bit will be set when the output current gets to within a specified value of the output current limit threshold enabling the host to reduce power consumption. The SET_VIOUT_MAX_CHx register allows the warning flag threshold to be set 10mV, 20mV, 30mV or 40mV below VIOUT_MAX. The warning flag will be automatically cleared when the current drops below the warning threshold. Over-Current Fault Handling When an over-current condition occurs, PWM drivers in the corresponding channels are disabled. After a 200ms timeout, the controller is re-powered and soft-start is initiated. When the overcurrent condition is reached the controller will check the SET_FAULT_RESP_CONFIG_LB and SET_FAULT_RESP_CONFIG_HB to determine whether there are any "following" channels that need to be similarly restarted. The controller will also set the fault flags in READ_OVC_FAULT_WARN register. Typically the over-current fault threshold would be set to 130-140% of the maximum desirable output current. This will help avoid any over-current conditions caused by transients that would shut down the output channel.
CHIP OPERATION AND CONFIGURATION SOFT-START
The SET_SS_RISE_CHx register is a 16 bit register which specifies the soft-start delay and the ramp characteristics for a specific channel. This register allows the customer to program the channel with a 250s step resolution and up to a maximum 16ms delay. Bits [15:10] specify the delay after enabling a channel but before outputting pulses; where each bit represents 250s steps. Bits [9:0] specify the rise time of the channel; these 10 bits define the number of microseconds for each 50mV increment to reach the target voltage.
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Enable Signal
Vout DELAY Bit [15:10]
RISE TIME Bit [9:0]
SS_RISE_CHx REGISTER
Fig. 23: Channel Power Up Sequence
SOFT-STOP
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and ramp (fall-time) characteristics for when the chip receives a channel disable indication from the Host to shutdown the channel. Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the channel; where each bit represents 250s steps. Bits [9:0] specify the fall time of the channel; these 10 bits define the number of microseconds for each 50mV increment to reach the discharge threshold.
Ena ble Signal
Vout
DELAY Bit [15 :10]
FALL TIME Bit [9:0]
PD_DELAY_CHx REGISTER
Fig. 24: Channel Soft-Stop Sequence
POWER GOOD FLAG
The XRP7714 allows the user to set the upper and lower bound for a power good signal per channel. The SET_PWRG_TARG_MAX_CHx register sets the upper bound, the SET_PWRG_TARG_MIN_CHx register sets the lower bound. Each register has a 20mV LSB resolution. When the output voltage is within bounds the power good signal is asserted high. Typically the upper bound should be lower than the over-voltage threshold. In addition, the power good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx register. The power good delay is only set after the soft-start period is finished. If the channel has a precharged condition that falls into the power good region, a power good flag is not set until the softstart is finished.
PWM SWITCHING FREQUENCY
The PWM switching frequency is set by choosing the corresponding oscillator frequency and clock divider ratio in the SET_SW_FREQUENCY register. Bits [6:4] set the oscillator frequency and bits
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[2:0] set the clock divider. The tables below summarize the available Main Oscillator and PWM switching frequency settings in the XRP7714. Main Oscillator Frequency
SET_SW_FREQUENCY[6:4] Main Oscillator Frequency Ts 000 48MHz 20.8ns 001 44.8MHz 22.3ns 010 41.6MHz 24ns 011 38.4MHz 26ns 100 35.2MHz 28.4ns 101 32MHz 31.25ns 110 28.8Mhz 34.7ns 111 25.6MHz 39ns
PWM Switching Frequency
SET_SW_FREQUENCY[6:4] SET_SW_FREQUENCY[2:0] 000 001 010 011 100 101 110 111 000 NA 1.5MHz 1.0MHz 750KHz 600KHZ 500KHz 429KHZ 375KHz 001 NA 1.4MHz 933KHz 700KHz 560KHz 467KHZ 400KHZ 350KHz 010 NA 1.3MHz 867KHz 650KHz 520KHz 433KHz 370KHz 325KHz 011 NA 1.2MHz 800KHz 600KHz 480KHz 400KHz 343KHz 300KHz 100 NA 1.1MHz 733KHz 550KHz 440KHz 367KHz 314KHz NA 101 NA 1.0MHz 667KHz 500KHz 400KHz 333KHz NA NA 110 NA 900KHz 600KHz 450KHz 360KHz 300KHz NA NA 111 NA 800KHz 533KHz 400KHz 320KHz NA NA NA
There are a number of options that could result in similar PWM switching frequency as shown above. In general, the chip consumes less power at lower oscillator frequency. When synchronization of the Main Oscillator Frequency to an external system clock is desired, the user must choose the oscillator frequency to be within 5% of the external clock frequency. A higher Main Oscillator frequency will not improve accuracy or any performance efficiency. Note: It is the intention of the synchronization feature to sync to a system clock or to another compatible Exar device, not the switching frequency.
PWM SWITCHING FREQUENCY CONSIDERATIONS
There are several considerations when choosing the PWM switching frequency. Minimum On Time Minimum on time determines the minimum duty cycle at the specific switching frequency. The minimum on time for the XRP7714 is 40ns. % 100 As an example the minimum duty cycle is 4% for 1MHz PWM frequency. This is important since the minimum on time dictates the maximum conversion ratio that the PWM controller can achieve. % Maximum Duty Cycle The maximum duty cycle is dictated by the minimum required time to sample the current when the low side MOSFET is on, this depends on the frequency of the main oscillator and the selected PWM frequency. It is best to choose the highest main oscillator frequency available for any specific PWM frequency. The maximum duty cycle for each PWM frequency is shown in the table below:
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Main Oscillator Frequency Maximum Duty Cycle 78% 86% 84% 89% 88% 88% 86% 48MHz 1.5MHz 1.0MHz 750KHz 600KHZ 500KHz 429KHZ 375KHz 44.8MHz 1.4MHz 933KHz 700KHz 560KHz 467KHZ 400KHZ 350KHz 41.6MHz 1.3MHz 867KHz 650KHz 520KHz 433KHz 370KHz 325KHz 38.4MHz 1.2MHz 800KHz 600KHz 480KHz 400KHz 343KHz 300KHz 35.2MHz 1.1MHz 733KHz 550KHz 440KHz 367KHz 314KHz NA 32MHz 1.0MHz 667KHz 500KHz 400KHz 333KHz NA NA 28.8Mhz 900KHz 600KHz 450KHz 360KHz 300KHz NA NA 25.6MHz 800KHz 533KHz 400KHz 320KHz NA NA NA
Fig. 25: PWM Frequency
It is highly recommended that the maximum duty cycle obtained from the table above be programmed into each of the channels using the SET_DUTY_LIMITER_CHx register. This ensures that under all conditions (including faults), there will always be sufficient sampling time to measure the output current. When the duty cycle limit is reached, the output voltage will no longer regulate and will be clamped based on the maximum duty cycle limit setting. Efficiency The PWM Switching frequency plays an important role on overall power conversion efficiency. As the switching frequency increase, the switching losses also increase. Please see the APPLICATION INFORMATION, Typical Performance Data for further examples. Component Selection and Frequency Typically the components become smaller as the frequency increases, as long as the ripple requirements remain constant. At higher frequency the inductor can be smaller in value and have a smaller footprint while still maintaining the same current rating.
FREQUENCY SYNCHRONIZATION FUNCTION AND EXTERNAL CLOCK
The user of the XRP7714 can choose to use an external source as the primary clock for the XRP7714. This function can be configured using the SET_SYNC_MODE_CONFIG register. This register sets the operation of the XRP7714 when an external clock is required. By selecting the appropriate bit combination the user can configure the IC to function as a master or a slave when two or more XRP7714s are used to convert power in a system. Automatic clock selection is also provided to allow operation even if the external clock fails by switching the IC back to an internal clock. External Clock Synchronization Even when configured to use an external clock, the chip initially powers up with its internal clock. The user can set the percent target that the frequency detector will use when comparing the internal clock with the clock frequency input on the GPIO pin. If the external clock frequency is detected to be within the window specified by the user, then a switchover will occur to the external clock. If the IC does not find a clock in the specified frequency target range then the external clock will not be used and the IC will run on the internal clock that was specified by the user. If the external clock fails the user can chose to have the internal clock take over, using the automatic switch back mode in the SET_SYNC_MODE_CONFIG register.
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CLK_IN
GPIO1 XRP7714 Configured for external clock use
Fig. 26:XRP7714 Configured For External Clock Use
Synchronized Operation as a Master and Slave Unit Two XRP7714s can be synchronized together. This Master-Slave configuration is described below. * Master When the XRP7714 powers up as a master unit after the internal configuration memory is loaded the unit will send CLK_OUT and SYNC_OUT signals to the slave on the preconfigured GPIO pins. * Slave When powering in sync mode the slave unit will initially power up with its internal clock to transfer the configuration memory. Once this transfer occurs, then the unit is set to function as a slave unit. In turn the unit will take the external clock provided by the master to run as its main internal clock.
GPIO1 CLK_OUT SYNC_OUT
CLK_IN SYNC_IN
GPIO1 GPIO2 XRP7714 configured as a slave
GPIO2 XRP7714 configured as a master
Fig. 27: Master/Slave Configuration of the XRP7714
External Clock Synchronization Master Slave combination When an external clock is used, the user will need to setup the master to also have an external clock in function. All of the same rules apply as in the External clock synchronization, Synchronized operation as a Slave unit section of this document. There are two ways of synchronizing this, either the external clock going to both Master/Slave CLK_IN, or CLK_IN can go to the Master, and the Master can synchronize SYNC_OUT and CLK_OUT to the Slave.
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CLK_IN
GPIO1 GPIO2 XRP7714 Configured as a master with external clock sync SYNC_OUT
CLK_IN SYNC_IN
GPIO1 GPIO2 XRP7714 configured as slave
Fig. 28: External Clock Synchronization Master Slave Combination
CLK_IN
GPIO3
GPIO1 GPIO2
CLK_OUT SYNC_OUT
CLK_IN SYNC_IN
GPIO1 GPIO2 XRP7714 configured as slave
XRP7714 Configured as a master with external clock sync
Fig. 29:Alternative External clock synchronization Master Slave combination
PHASE SHIFT
Each switching channel is configured to run with a phase shift of 90 degrees.
GPIO PINS
The General Purpose Input Output (GPIO) Pins are the basic interface between the XRP7714 and the system. Although all of the stored data within the IC can be read back using the I2C bus it is sometimes convenient to have some of those internal register to be displayed and or controlled by a single data pin. Besides simple input output functions the GPIO pins can be configured to serve as external clock inputs. These pins can be programmed using OTP bits or can be programmed using the I2C bus. This GPIO_CONFIG register allows the user close to 100 different configuration functions that the GPIO can be programmed to do. NOTE: the GPIO Pins (and all I/Os) should NOT be driven without a 10K resistor when VIN is not being applied to the IC. GPIO Pins Polarity The polarity of the GPIO pin can be set by using the GPIO_ACT_POL register. This register allows any GPIO pin whether configured as an input or output to change polarity. Bits [5:0] are used to set the polarity of GPIO 0 though 5. If the IC operates in I2C mode, then the commands for Bits [5:4] are ignored.
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Supply Rail Enable Each GPIO can be configured to enable a specific power rail for the system. The GPIOx_CFG register allows a GPIO to enable/disable any of the following rails controlled by the chip: * * * A single buck power controller The Standby LDO Any mix of the Standby LDO and power controller(s)
When the configured GPIO is asserted externally, the corresponding rails will be enabled, and they will be similarly disabled when the GPIO is de-asserted. This supply enabling/disabling can also be controlled through the I2C interface. Power Good Indicator The GPIO pins can be configured as Power Good indicators for one or more rails. The GPIO pin is asserted when all rails configured for this specific IO are within specified limits for regulation. This information can also be found in the READ_PWRGD_SS_FLAG status register. Fault and Warning Indication The GPIOs can be configured to signal Fault or Warning conditions when they occur in the chip. Each GPIO can be configured to signal one of the following: * * * * * * OCP Fault on Channel 1 - 4 OCP Warning on Channel 1 - 4 OVP Fault on Channel 1 - 4 UVLO Fault on VIN1 or VIN2 UVLO Warning on VIN1 or VIN2 Over Temperature Fault or Warning
I2C COMMUNICATION
The I2C communication is standard 2-wire communication available between the Host and the IC. The communication has the option of enabling Packet Error Checking in order to deal with noisy environments where bit-errors could occur in the communication. This packet error checking is a CRC-8 code appended to all communication between the Host and the IC. The I2C Slave address is saved in the NVM. Therefore, each customer can choose the 7-bit Slave Address which will work best in their design (in relation to any other I2C devices on the bus).
EXTERNAL COMPONENT SELECTION
Inductor Selection Select the Inductor for inductance L and saturation current Isat. Select an inductor with Isat higher than the programmed over current limit. Calculate inductance from: 1 Where: Vin is the converter input voltage Vout is the converter output voltage fs is the switching frequency
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Irip is the inductor peak-to-peak current ripple (nominally set to 30% of Iout) Keep in mind that a higher Irip results in a smaller inductance value which has the advantages of smaller size, lower DC equivalent resistance (DCR), and allows the use of a lower output capacitance to meet a given step load transient. A higher Irip, however, increases the output voltage ripple, requires higher saturation current limit, and increases critical conduction. Notice that this critical conduction current is half of Irip. Capacitor Selection * Output Capacitor Selection Select the output capacitor for voltage rating, capacitance and Equivalent Series Resistance (ESR). Nominally the voltage rating is selected to be at least twice as large as the output voltage. Select the capacitance to satisfy the specification for output voltage overshoot/undershoot caused by the current step load. A sudden decrease in the load current forces the energy surplus in the inductor to be absorbed by Cout. This causes an overshoot in output voltage that is corrected by power switch reduced duty cycle. Use the following equation to calculate Cout:
Where: L is the output inductance I2 is the step load high current I1 is the step load low current Vos is output voltage including the overshoot Vout is the steady state output voltage Or it can be expressed approximately by 2 Here,
V = Vos - Vout is the overshoot voltage deviation.
Select ESR such that output voltage ripple (Vrip) specification is met. There are two components in Vrip. First component arises from the charge transferred to and from Cout during each cycle. The second component of Vrip is due to the inductor ripple current flowing through the output capacitor's ESR. It can be calculated for Vrip: 1 8 Where: Irip is the inductor ripple current fs is the switching frequency Cout is the output capacitance Note that a smaller inductor results in a higher Irip, therefore requiring a larger Cout and/or lower ESR in order to meet Vrip. With the current generation of ultra-low ESR ceramic capacitors it is common to operate with Irip 30% of Iout.
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When trying to optimize control loop bandwidth, particularly at switching frequencies below 600kHz, an effective ESR in the range of 7 to 20mohm can help significantly. The Digital Power Studio design tool is used to verify what will work best in your application. * Input Capacitor Selection Select the input capacitor for Voltage, Capacitance, ripple current, ESR and ESL. Voltage rating is nominally selected to be at least twice the input voltage. The RMS value of input capacitor current, assuming a low inductor ripple current, can be approximated as: 1 Where: Iin is the RMS input current Iout is the DC output current D is the duty cycle In general, the total input voltage ripple should be kept below 1.5% of VIN. The input voltage ripple also has two major components: the voltage drop on the main capacitor VCin and the voltage drop due to ESR calculated from:
VESR . The contribution to Input voltage ripple by each term can be
VCin =
I out V out (Vin - V out ) 2 f s C inVin
VESR = ESR ( I out + 0.5 I rip )
Total input voltage ripple is the sum of the above:
VTot = VCin + VESR
Power MOSFETs Selection Selecting MOSFETs with lower Rdson reduces conduction losses at the expense of increased switching losses. A simplified expression for conduction losses is given by:
Pcond = I out Rdson
MOSFET's junction temperature can be estimated from:
2
Vout Vin
T j = 2 Pcond Rthja + Tambient
This assumes that the switching loss is the same as the conduction loss. Rthja is the total MOSFET thermal resistance from junction to ambient.
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PACKAGE SPECIFICATION 40-PIN 6MMX6MM TQFN
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REVISION HISTORY
Revision 1.1.3 Date 02/21/2010 Initial release of data sheet Description
FOR FURTHER ASSISTANCE
Email: Exar Technical Documentation: customersupport@exar.com http://www.exar.com/TechDoc/default.aspx?
EXAR CORPORATION HEADQUARTERS AND SALES OFFICES
48720 Kato Road Fremont, CA 94538 - USA Tel.: +1 (510) 668-7000 Fax: +1 (510) 668-7030 www.exar.com
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. or its in all
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