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1/4 Structure Product Model F u n c t Name Name i o n Silicon monolithic integrated circuits 1CH LDO Regulator of mounting on micro side for 15V input
BD9995NUV
(1) Input voltage: 15[V]MAX (2) Output current: 0.6[A]MAX (3) Low current consumption At the standby: 1[A] or lessStandard (4) Built-in soft start function (5) Built-in on/off function (6) Built-in output voltage change ability function (7) Over current protectionHeating protection
(8) VSON008V2030 Space saving achievement by package Absolute maximum ratings (Ta=25) Item Supply voltage Power dissipation 12 Operating temperature range Storage temperature range VOUT terminal maximum input voltage FB terminal maximum input voltage EN terminal maximum input voltage SEL terminal maximum input voltage Junction temperature Symbol Vcc Pd Topt Tstg VINVOUT VINFB VINEN VINSEL Tjmax Limit -0.315.5 2.82 -25+85 -55+150 -0.3Vcc+ 0.3 -0.3Vcc+ 0.3 -0.3Vcc+ 0.3 -0.3Vcc+ 0.3 +150 Unit V W V V V V
1ROHM 4 layer board76.2x114.3x1.6[mm3] The copper area on 2,3 layer 5655 mm2 2Power dissipation depends on the mounted wiring pattern.
Operating conditions (Ta25) Item Supply voltage1SEL=Vcc 3 Supply voltage2SEL=Open 3 Supply voltage3SEL=GND 3 Output currentVcc-Vout=1.1V 3
3 Do not, however exceed Pd.
No radiation-proof design Status of this document The Japanese version of this document is the formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document, formal version takes priority.
Symbol Vcc1 Vcc2 Vcc3 Iout
Min. 8.7 9.7 10.7 -
Typ. 12.0 12.0 12.0 -
Max. 15.0 15.0 15.0 0.60
Unit V V V A
REV. A
2/4
Electric Characteristics Unless otherwise specified, Vcc=12.0[V],Ta=25[] Limit Min. 351 7.7.6 8.73 9.70 0.45 0 2.4 53 Typ. 1.0 540 8.00 9.00 10.00 0.85 75 Max. 10.0 729 8.24 9.27 10.30 1.25 0.5 Vcc 97 0.8
Parameter Current consumption at stand by Current consumption when operating Output voltage1 Output voltage2 Output voltage3 Soft start time EN Low Input threshold voltage EN High Input threshold voltage EN Input Current Minimum I/O voltage difference
Symbol ICC1 ICC2 VOUT1 VOUT2 VOUT3 TSOFT VthENL VthENH ICCEN VIO
Unit A A V V V S V V uA V
Condition Vcc=12.0[V], SEL=GND Vcc=12.0[V], SEL=GND No load Vcc=12.0[V], SEL=Vcc Vcc=12.0[V], SEL=Open Vcc=12.0[V], SEL=GND Time of output voltage 85[%]
EN=3.0[V] ,Vcc=12.0[V] VOUT=10.0[V], Output load =450[mA]
Package outline

Lot.No.
( UNIT:mm )
REV. A
3/4
Block Diagram
Terminal No./Terminal name
Terminal No 1 2 3 4 5 6 7 8
Terminal name EN GND SEL FB VOUT VOUT Vcc Vcc
REV. A
4/4 Operation Notes 1About ground potential .The ground line is where the lowest potential and transient voltages are connected to the IC. Moreover, all terminals except the terminal GND must not become the voltage of GND or less actually including transients. 2About starting Keep light Load at VOUT output while start-up. 3About board pattern Use separates ground lines for small control signals and high current outputs. Because these high current outputs that flows to the wire impedance changes the GND voltage for control signal. Therefore each ground of IC must be connected at one point on the set circuit board. As for GND of external parts, it's similar to the above-mentioned. 4About peripheral circuit Bypass capacitor between power supply and ground should be use low ESR ceramic capacitor and placed close to the IC pin as possible. The output condenser is necessary to be placed as near to the IC as possible with shortest distance. Monitor the output voltage at both end of capacitor connected to VOUT. 5About absolute maximum rating Exceeding supply voltage and operating Temp. over Absolute Maximum Ratings may cause degradation of IC and even may destroy the IC. If special mode such that exceeding Absolute Maximum Ratings is expected, please have safe countermeasure such as adding POLY SWITCH and fuse to avoid from over stressing. 6About heat design Do not exceed the power dissipation (PD) of the package specification rating under actual operation. 7About Short between pins and the mis-installation While mounting IC on the printing board, check direction and position of the IC. If inadequately mounted, the IC may destroy. Moreover this IC might be destroyed when dust short the terminals between pins or pin and ground. 8About operation in strong electromagnetic field Strong electromagnetic radiation can cause operation failures. 9About heat interception circuit (TSD) The heat interception circuit is built into this IC. When the junction temperature (Tj) reaches 175, the output is switched to off. It is a circuit to aim to intercept IC from thermal reckless driving to the last, and it aims at no protection and the guarantee of neither set nor IC. Therefore, operate this circuit and use neither continuous use from now on nor operation. 10About over current protection circuit The over current protection circuit is built into this IC. It operates by the effective one of the protection circuit continuous for the destruction prevention due to broken accident, and avoids the load about this circuit about use to which the operation of this function is required because it is not the one to the use when it is excessive IC destruction. 11About inspection by set substrate The stress might hang to IC by connecting the capacitor to the terminal with low impedance. Then, please discharge electricity in each and all process. Moreover, in the inspection process, please turn off the power before mounting the IC, and turn on after mounting the IC. In addition, please take into consideration the countermeasures for electrostatic damage, such as giving the earth in assembly process, transportation or preservation. 12About each input terminal This IC is a monolithic IC, and has P+ isolation and P substrate for the element separation. Therefore, a parasitic PN junction is firmed in this P-layer and N-layer of each element. When the GND voltage potential is greater than the voltage potential at Terminals A or B, the PN junction operates as a parasitic diode. In addition, the parasitic NPN transistor is formed in said parasitic diode and the N layer of surrounding elements close to said parasitic diode. These parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes the wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than GND (P substrate). Please do not apply the voltage to the input terminal when the power -supply voltage is not impressed. Moreover, please impress each input terminal lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power-supply voltage is impressing.
REV. A
Notice
Notes
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