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| SS6383B(G) 3A DDR Termination Regulator FEATURES Source and sink current capability of 3A Low output voltage offset, 20mV DESCRIPTION The SS6383B linear regulator is designed to provide 3A source and sink current while regulating an output voltage to within 45mV. The SS6383B converts voltage supplies ranging from 1.6V to 6V into an output voltage that is set by two external voltage-divider resistors. It provides an excellent voltage source for active termination schemes for high-speed transmission lines such as those seen in highspeed memory buses. The built-in current-limiting in source and sink mode, together with thermal shutdown, provides maximum protection to the SS6383B against fault conditions. High accuracy output voltage at full-load VOUT adjustable by external resistors Low external component count Current limit protection Thermal protection SO-8, TO-252-5 and TO-263-5 packages APPLICATIONS Mother Boards Graphic Cards DDR Termination Voltage Supply - supports DDR1 (1.25VTT), DDR2 (0.9VTT), and meets JEDEC SSTL-2 and SSTL-3 term. specifications TYPICAL APPLICATION CIRCUIT VIN=2.5V + CIN 470F 1 2 3 VIN VOUT GND VCNTL VREF 5 R1 100K COUT 220F + VOUT 4 VCNTL=3.3V + CCNTL 47F SS6383BCE5 R2 C1 100K 100pF EN SSM7002EN This device is available with Pb-free lead finish (second-level interconnect) as SS6383BGxx 11/07/2004 Rev.2.01 www.SiliconStandard.com 1 of 8 SS6383B(G) ORDERING INFORMATION SS6383BXXX XX Packing TR: Tape and reel Package type CM5: TO-263-5, commercial CE5 : TO-252-5, commercial CS : SO-8, commercial GM5 : TO-263-5, commercial, Pb-free GE5 : TO-252-5, commercial, Pb-free GS : SO-8, commercial, Pb-free TO-263-5 FRONT VIEW 1: VIN 2: GND 3. VCNTL 4. VREF 5: VOUT PIN CONFIGURATION 12345 TO-252-5 TOP VIEW 1: VIN 2: GND 3. VCNTL 4. VREF 5: VOUT 1234 5 Example: SS6383BGE5TR in TO-252-5 package, with Pb-free lead finish, shipped on tape and reel SO-8 TOP VIEW VIN 1 GND 2 VREF 3 VOUT 4 8 VCNTL 7 VCNTL 6 VCNTL 5 VCNTL ABSOLUTE MAXIMUM RATINGS Supply Voltage Operating Temperature Range Storage Temperature Range Lead Temperature (Solder, 10sec) Thermal Resistance JC TO-263 TO-252 SO-8 Thermal Resistance JA (Assume no ambient airflow, no heatsink) TO-263 TO-252 SO-8 -0.4V to 7V -40C~85C -65C ~150C 260C 3C /W 12.5C /W 40C /W 60C /W 100C /W 160C /W Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 11/07/2004 Rev.2.01 www.SiliconStandard.com 2 of 8 SS6383B(G) TEST CIRCUIT 2.5V 1 2 3 VIN VOUT GND VREF VCNTL SS6383B 4 5 VOUT + 1.25V COUT 10F 3.3V ELECTRICAL CHARACTERISTICS (VCNTL=3.3V, VIN=2.5V, VREF=0.5VIN, COUT=10F, TA=25C, unless otherwise specified) PARAMETER Input Voltage (DDR1/2) Output Voltage Output Voltage Offset Load Regulation (DDR1/2) Quiescent Current TEST CONDITIONS Keep VCNTLVIN during power on and off sequences IOUT = 0mA IOUT = 0mA IOUT =0.1mA ~ +3A IOUT =0.1mA ~ -3A VREF<0.2V, VOUT = OFF SYMBOL VIN VCNTL VOUT VOS VLOR IQ ICNTL 0 IIL 3.2 4 -20 35 35 8 3 MIN. 1.6 3.0 TYP. 2.5 3.3 VREF 20 45 mV 45 30 10 1 6.5 A mA A A MAX. 6 V 6 V mV UNIT Operating Current of VCNTL No load VREF Bias Current Current Limit THERMAL PROTECTION Thermal Shutdown Temperature Thermal Shutdown Hysteresis 3.3VVCNTL5V Guaranteed by design VREF=1.25V TSD 125 150 C C 30 SHUTDOWN SPECIFICATIONS Shutdown Threshold Output ON (VREF=0V 1.25V) Output OFF (VREF=1.25V 0V) 0.8 V 0.2 Note 2: VOS is the voltage measurement, which is defined as the difference between VOUT and VREF. Note 3: Load regulation is measured at constant junction temperature, using pulse testing with a low ON time. Note 4: Current limit is measured by pulsing a short time. Note 5: To operate the system safely; V CNTL must be always greater than VIN. Note 6: Specifications are guaranteed by Statistical Quality Controls (SQC), and not production tested, within the operating temperature range of -40C to 85C. Note 7: DDR2 is not supported in the TO-263 package. 11/07/2004 Rev.2.01 www.SiliconStandard.com 3 of 8 SS6383B(G) TYPICAL PERFORMANCE CHARACTERISTICS 0.52 Threshold Voltage (V) Threshold Voltage (V) VCNTL=3.3V VIN=2.5V 0.52 VCNTL=5V 0.48 0.44 0.40 0.36 0.32 0.48 0.44 0.40 0.36 0.32 VIN=2.5V -20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120 Temperature (C) Fig. 1 Turn-On Threshold vs. Temp. Temperature (C) Fig. 2 Turn On Threshold vs. Temp. 6 Output Voltage Offset (mV) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40 Sourcing Current (A) VCNTL=3.3V VIN=2.5V VREF=1.25V No Load 5 VCNTL=3.3V VIN=2.5V VREF=1.25V 4 3 -20 0 20 40 60 80 100 120 2 -40 -20 0 20 40 60 80 100 120 Temperature (C) Fig. 3 Output Voltage Offset vs. Temp. Temperature (C) Fig. 4 Current-Limit (Sourcing) vs. Temp. 6 Sinking Current (A) 5 VCNTL=3.3V VIN=2.5V VREF=1.25V VCNTL=3.3V VIN=2.5V, VREF=1.25V 4 VOUT, 50mV/div IOUT, 2A/div 3 2 -40 -20 0 20 40 60 80 100 120 Temperature (C) Fig. 5 Current-Limit (Sinking) vs. Temp. Fig. 6 Transient Response at 1.25VTT/3A 11/07/2004 Rev.2.01 www.SiliconStandard.com 4 of 8 SS6383B(G) TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VCNTL=3.3V VIN=2.5V VREF=1.25V VCNTL=3.3V VIN=2.5V VREF=1.25V Iout, 2A/div Iout, 2A/div Fig. 7 Output Short-Circuit Protection (Sinking) Fig. 8 Output Short-Circuit Protection (Sourcing) BLOCK DIAGRAM VCNTL VIN + Control VREF VOUT Current Limit Thermal Shutdown VOUT Shutdown GND 11/07/2004 Rev.2.01 www.SiliconStandard.com 5 of 8 SS6383B(G) PIN DESCRIPTIONS (Pin numbers refer to TO-252/263) PIN 4: PIN 1: - Input supply pin. It provides main power to create the external reference voltage by divider resistors for regulating VREF and VOUT. GND - Ground pin. VCNTL - Input supply pin. It is used to supply all the internal control circuitry. VIN PIN 5: VREF - Reference voltage input. Pull this pin low to shutdown device. VOUT - Output pin. PIN 2: PIN 3: APPLICATION INFORMATION Layout Consideration As the SS6383B is in either SO-8, TO-252-5 or TO-263-5 packages, it is unable to dissipate heat easily when it operates at high current. To avoid exceeding the maximum junction temperature, a suitable copper area must be used. The large copper area shown at V CNTL pins is able to relieve the thermal dissipation. Using the via to direct heat into the large copper area shown on the bottom layer also helps significantly. All capacitors should be placed as close as possible to the relevant pins. Fig. 9 Top layer for SO-8 Fig. 10 Bottom layer for SO-8 Fig. 11 Placement for SO-8 11/07/2004 Rev.2.01 www.SiliconStandard.com 6 of 8 SS6383B(G) PHYSICAL DIMENSIONS TO-263-5 E L2 A c2 SYMBOL A A1 C2 D MIN 4.06 0 1.14 8.38 9.65 14.61 2.29 MAX 4.83 0.15 1.40 9.65 10.29 1.70 BSC 15.88 2.79 1.40 0.25 BSC D L E e L L1 L2 A A e Gauge Plane Seating Plane L4 L1 A1 0 8 L4 TO-252-5 E b3 L3 A c2 SYMBOL A A1 b3 c2 D H MIN 2.19 0 5.21 0.46 5.33 6.35 MAX 2.38 0.13 5.46 0.58 5.59 6.73 1.27 BSC 10.41 1.78 2.67 REF 0.51 BSC D E e H L 9.40 1.4 e A A L1 L2 L3 L L2 L1 A1 1.52 0 2.03 8 11/07/2004 Rev.2.01 www.SiliconStandard.com 7 of 8 SS6383B(G) PHYSICAL DIMENSIONS (cont.) SO-8 D SYMBOL A A1 H E MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 1.27 B C D E e A C A1 e H L L 1.27(TYP) B Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 11/07/2004 Rev.2.01 www.SiliconStandard.com 8 of 8 |
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