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| SSM4500GM N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY D2 N-CH BVDSS RDS(ON) ID G2 S2 20V 30m 6A -20V 50m -5A Simple Drive Requirement Low On-resistance Fast Switching D2 D1 D1 P-CH BVDSS RDS(ON) ID SO-8 S1 G1 DESCRIPTION The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is universally preferred for all commercialindustrial surface mount applications and suited for low voltage applications such as DC/DC converters. G1 D1 D2 G2 S1 S2 Pb-free; RoHS-compliant ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 20 12 6 4.8 20 2.0 0.016 -55 to 150 -55 to 150 P-channel -20 12 -5 -4 -20 Units V V A A A W W/ Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit /W 02/13/2008 Rev.1.00 www.SiliconStandard.com 1 SSM4500GM N-CH Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage 2 Test Conditions VGS=0V, ID=250uA Min. Typ. Max. Units 20 0.5 0.037 30 45 1.2 1 25 15 480 - V V/ m m V S uA uA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA RDS(ON) Static Drain-Source On-Resistance VGS=4.5V, ID=6A VGS=2.5V, ID=5.2A 18.5 9 1.8 4.2 29 65 60 50 300 255 115 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70oC) o VDS=VGS, ID=250uA VDS=10V, ID=6A VDS=20V, VGS=0V VDS=16V, VGS=0V VGS=12V ID=6A VDS=10V VGS=4.5V VDS=10V ID=1A RG=6,VGS=4.5V RD=10 VGS=0V VDS=8V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 100 nA Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=1.7A, VGS=0V IS=6A, VGS=0V, dI/dt=100A/s Min. Typ. Max. Units 26 17 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge 02/13/2008 Rev.1.00 www.SiliconStandard.com 2 SSM4500GM P-CH Electrical Characteristics@Tj=25 C(unless otherwise specified) Symbol BVDSS BVDSS/Tj o Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=70 C) o o Test Conditions VGS=0V, ID=250uA 2 Min. Typ. Max. Units -20 -0.5 -0.037 50 90 -1 -1 -25 20 - V V/ m m V S uA uA nC nC nC ns ns ns ns pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=-1mA RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss VGS=-4.5V, ID=-2.2A VGS=-2.5V, ID=-1.8A VDS=VGS, ID=-250uA VDS=-10V, ID=-2.2A VDS=-20V, VGS=0V VDS=-16V, VGS=0V VGS= 12V ID=-5A VDS=-16V VGS=-4.5V VDS=-10V ID=-2.2A RG=6,VGS=-10V RD=4.5 VGS=0V VDS=-20V f=1.0MHz 2.5 14 2 5.6 10 11 58 38 400 160 Gate-Source Leakage Total Gate Charge 2 100 nA Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 940 1500 pF SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=-1.8A, VGS=0V IS=-2.2A, VGS=0V, dI/dt=100A/s Min. Typ. Max. Units 25 21 -1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in copper pad of FR4 board ; 135/W when mounted on Min. copper pad. 2 02/13/2008 Rev.1.00 www.SiliconStandard.com 3 SSM4500GM N-Channel 25 25 T A =25 o C ID , Drain Current (A) 20 ID , Drain Current (A) 4.5V 3.5V 3.0V 2.5V T A =150 o C 20 4.5V 3.5V 3.0V 2.5V 15 15 10 10 V GS =2.0V 5 V GS =2.0V 5 0 0 1 2 3 4 5 0 0 1 2 3 4 5 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 45 1.8 40 I D =6A T A =25 C Normalized RDS(ON) o 1.6 I D =6A V GS =4.5V 1.4 RDS(ON) (m ) 35 1.2 30 1.0 25 0.8 20 2 3 4 5 0.6 -50 0 50 100 150 V GS (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 1.5 100.00 10.00 1 1.00 T j =150 o C T j =25 o C VGS(th) (V) 0.5 0 -50 IS(A) 0.10 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 0 50 100 150 V SD (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage v.s. Junction Temperature 02/13/2008 Rev.1.00 www.SiliconStandard.com 4 SSM4500GM N-Channel f=1.0MHz 6 1000 5 VGS , Gate to Source Voltage (V) I D =6A V DS =10V 4 Ciss C (pF) Coss 100 3 2 Crss 1 0 10 0 2 4 6 8 10 12 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (Rthja) Duty Factor = 0.5 10 0.2 1ms ID (A) 10ms 1 0.1 0.1 0.05 100ms 1s 0.1 0.02 0.01 PDM 0.01 t T Single Pulse T A =25 o C Single Pulse 10s DC Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135o C/W 0.01 0.001 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS (V) t , Pulse Width (s) Fig9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 02/13/2008 Rev.1.00 www.SiliconStandard.com 5 SSM4500GM P-Channel 25 25 T A =25 o C 20 -ID , Drain Current (A) -ID , Drain Current (A) 4.5V 4.0V 3.5V 3.0V T A =150 o C 20 4.5V 4.0V 3.5V 3.0V 15 15 10 V GS =2. 5 V 10 V GS =2. 5 V 5 5 0 0 1 2 3 4 5 0 0 1 2 3 4 5 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 1.8 90 I D =-2.2A T A =25 Normalized RDS(ON) 1.6 I D =-2.2A V GS = -4.5V 80 1.4 RDS(ON) (m ) 70 1.2 60 1 50 0.8 40 30 0.6 2 3 4 5 -50 0 50 100 150 -V GS (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 1 100.00 0.8 10.00 1.00 T j =150 C o T j =25 C o -VGS(th) (V) 1.3 1.5 0.6 -IS(A) 0.4 0.10 0.2 0.01 0 0.1 0.3 0.5 0.7 0.9 1.1 -50 0 50 100 150 -V SD (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 02/13/2008 Rev.1.00 Fig 6. Gate Threshold Voltage v.s. Junction Temperature 6 www.SiliconStandard.com SSM4500GM P-Channel f=1.0MHz 6 10000 -VGS , Gate to Source Voltage (V) 5 I D =-5A V DS =-16V 1000 4 Ciss Coss Crss 3 C (pF) 100 10 1 2 1 0 0 4 8 12 16 20 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty Factor = 0.5 10 1ms 10ms Normalized Thermal Response (R thja) 0.2 0.1 0.1 -ID (A) 0.05 1 100ms 1s 0.02 0.01 PDM 0.01 t T Single Pulse 0.1 T A =25 o C Single Pulse 0.01 10s DC Duty factor = t/T Peak Tj = PDM x Rthja + T a Rthja=135 oC/W 0.001 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS (V) t , Pulse Width (s) Fig9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 02/13/2008 Rev.1.00 Fig 12. Gate Charge Waveform 7 www.SiliconStandard.com SSM4500GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 02/13/2008 Rev.1.00 www.SiliconStandard.com 8 |
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