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| SSM9971GH,J N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low gate-charge Simple drive requirement Fast switching G D BV DSS R DS(ON) ID 60V 36m 25A S Description The SSM9971GH is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM9971GJ in TO-251, is available for low-footprint vertical mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. GD S TO-252 (H) Pb-free lead finish (second-level interconnect) G D S TO-251 (J) Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=100C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current 1 Rating 60 20 25 16 80 39 0.31 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 3.2 110 Unit C/W C/W 2/16/2005 Rev.2.2 www.SiliconStandard.com 1 of 5 SSM9971GH,J Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance2 Test Conditions VGS=0V, ID=250uA Min. 60 1 Typ. 0.05 17 18 6 11 9 24 26 7 160 110 Max. Units 36 50 3 1 25 100 30 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA VGS=10V, ID=18A VGS=4.5V, ID=12A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150 C) o o VDS=VGS, ID=250uA VDS=10V, ID=18A VDS=60V, VGS=0V VDS=48V ,VGS=0V VGS= 20V ID=18A VDS=48V VGS=4.5V VDS=30V ID=18A RG=3.3 , VGS=10V RD=1.67 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1700 2700 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 Test Conditions IS=25A, VGS=0V IS=18A, VGS=0V, dI/dt=100A/s Min. - Typ. 37 38 Max. Units 1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. 2/16/2005 Rev.2.2 www.SiliconStandard.com 2 of 5 SSM9971GH,J 100 70 T C =25 o C 80 10V 7.0V ID , Drain Current (A) 5.0V T C =150 C 60 o 10V 7.0V 5.0V 4.5V ID , Drain Current (A) 50 60 4.5V 40 30 40 20 20 V G =3.0V 0 V G =3.0V 10 0 0 1 2 3 4 5 0 1 2 3 4 5 6 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 40 2.5 I D = 18 A T C =25 C 35 o I D =18A V G =10V 2.0 Normalized R DS(ON) RDS(ON) (m ) 1.5 1.0 30 0.5 25 0.0 3 5 7 9 11 -50 0 50 100 rr o V GS , Gate-to-Source Voltage (V) Qrr 150 T j , Junction Temperature ( C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 3 20 2.5 16 T j =150 o C 12 T j =25 o C VGS(th) (V) 2 IS(A) 1.5 8 1 4 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( C) o Fig 5. Forward Characteristic of Reverse Diode 2/16/2005 Rev.2.2 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9971GH,J f=1.0MHz 14 10000 I D =18A 12 VGS , Gate to Source Voltage (V) 10 V DS =30V V DS =38V V DS =48V C (pF) Ciss 1000 8 6 100 4 Coss Crss 2 0 0 10 20 30 40 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 100us Duty factor=0.5 1ms 10 Normalized Thermal Response (R thjc) 0.2 10ms ID (A) 100ms 1 0.1 0.1 0.05 PDM 0.02 0.01 1s DC T C =25 C Single Pulse o t T Duty factor = t/T Peak Tj = PDM x Rthjc + TC Single Pulse 0.1 0.1 1 10 100 1000 0.01 0.00001 0.0001 0.001 0.01 0.1 rr V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Qrr 1 Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 2/16/2005 Rev.2.2 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9971GH,J Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/16/2005 Rev.2.2 www.SiliconStandard.com 5 of 5 |
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