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merging Memory & Logic Solutions Inc.
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
EM640FP8 Series
Low Power, 512Kx8 SRAM
Revision History
Revision No.
0.0 0.1 0.2
History
Initial Draft 2'nd Draft 3' Draft rd Changed Icc, Icc1 value Changed I SB1 test conditions, Changed VDR & IDR measurement condition
Draft Date
October 24,2002 November 11 , 2002 December 23 , 2002
Remark
Preliminary
0.3
4'th Draft
Add Pb-free part number
February 13 , 2004
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1
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FEATURES
* * * * * * Process Technology : 0.18m Full CMOS Organization : 512K x 8 bit Power Supply Voltage : 1.65V ~ 2.2V Low Data Retention Voltage : 1.0V(Min) Three state outputs Package Type : 36-FPBGA 6.0x7.0
EM640FP8 Series
Low Power, 512Kx8 SRAM
GENERAL DESCRIPTION
The EM640FP8 families are fabricated by EMLSI's advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (I SB1 , Typ) 1 A Operating (I CC1.Max) 2 mA PKG Type
EM640FP8
Industrial (-40 ~ 85o C)
1.65~2.2V
70ns 1 )
36 FPBGA (6.0x7.0)
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
1 A B C D E F G H 2 3 4 5 6
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A0 I/O 5 I/O 6 V SS VC C I/O 7 I/O 8 A9
A1 A2
CS2 WE DNU
A3 A4 A5
A6 A7
A8 I/O1 I/O2 VCC V SS
Row S elect
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VC C VSS
Memory Array 2048 x 2048
I/O1 ~ I/O4 I/O5 ~ I/O8
Data Cont Data Cont
I/O Circuit Column Select
A18 OE A10 CS1 A11
A17 A16 A12 A15 A13
I/O3 I/O4 A14
A A A13 A1 A A A A 11 12 4 15 16 17 18
36-FPBGA : Top view (ball down)
W E O E CS 1
Control Logic
Name CS 1 ,CS 2 OE A 0 ~A18 I/O1 ~I/O 8
Function Chip select inputs Output Enable input Address Inputs Data Inputs/outputs
Name WE Vcc Vss DNU
Function Write Enable input Power Supply Ground Do Not Use
CS 2
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ABSOLUTE MAXIMUM RATINGS * Parameter
Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature
EM640FP8 Series
Low Power, 512Kx8 SRAM
Symbol
VIN , VOUT VCC PD TA
Ratings
-0.5V to VCC+0.3V (Max.2.5V) -0.3V to 2.5V 1.0 -40 to 85
Unit
V V W
oC
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS 1 H X L L L CS 2 X L H H H OE X X H L X WE X X H H L I/O High-Z High-Z High-Z Data Out Data In Mode Deselected Deselected Output Disabled Read Write Power Stand by Stand by Active Active Active
Note: X means don't care. (Must be low or high state)
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RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter Supply voltage Ground Input high voltage Input low voltage
1. 2. 3. 4.
EM640FP8 Series
Low Power, 512Kx8 SRAM
Symbol VCC VSS VIH VIL
Min 1.65 0 1.4 -0.3 3)
Typ 1.8 0 -
Max 2.2 0 VCC + 0.32) 0.4
Unit V V V V
TA= -40 to 85oC, otherwise specified Overshoot: VCC +1.0 V in case of pulse width < 20ns Undershoot: -1.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE 1) (f =1MHz, TA=25oC)
Item Input capacitance Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested
Symbol C IN CIO
Test Condition VIN=0V VIO =0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO I CC ICC1 Average operating current ICC2 Output low voltage Output high voltage VOL VOH
V IN = VSS to V CC CS 1 =VIH , CS2 =V IL or OE=V IH or WE=V IL, V IO =VSS to VCC IIO =0mA, CS 1 = VIL , CS 2= W E=VIH , V IN=V I H or V IL Cycle time=1s, 100% duty, I IO =0mA, CS 1 <0.2V, CS2 >V CC-0.2V, V IN <0.2V or V IN >V CC-0.2V Cycle time = Min, I IO =0mA, 100% duty, CS 1 = VIL , CS 2=V IH, V IN = VIL or V I H
Test Conditions
Min -1 -1 -
Typ -
Max 1 1 2 2
Unit A A mA
mA
70ns
1.4
-
12 0.2 -
mA V V
IOL = 0.1mA IOH = -0.1mA CS 1 >V CC -0.2V, CS 2 >V CC-0.2V (CS 1 controlled) or 0V< CS2 <0.2V (CS 2 controlled), Other inputs=0 ~ VCC (Typ. condition : VCC=1.8V @ 25 o C) (Max. condition : VCC =2.2V @ 85o C)
Standby Current (CMOS)
ISB1
LL LF
-
1
5
A
4
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AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2V to VCC-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 0.9V Output Load (See right) : CL = 100pF+ 1 TTL CL 1) = 30pF + 1 TTL 1. Including scope and Jig capacitance 2. R1 =3070, R 2 =3150 3. VTM=1.8V
EM640FP8 Series
Low Power, 512Kx8 SRAM
VTM 3) R12)
CL1)
R22)
READ CYCLE (V cc =1.65 to 2.2V, Gnd = 0V, T A = -40oC to +85oC)
Parameter
Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change
Symbol
tRC tAA tco1, tco2 tO E tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tOH
70ns Min 70 10 5 0 0 10 Max 70 70 35 25 25 -
Unit
ns ns ns ns ns ns ns ns ns
WRITE CYCLE (Vcc =1.65 to 2.2V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Write cycle time Chip select to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z
Symbol
tWC tCW1, tCW2 tAs tAW tWP tWR tWHZ tDW tDH tOW
70ns Min 70 60 0 60 55 0 0 30 0 5 Max 25
Unit
ns ns ns ns ns ns ns ns ns ns
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TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1).
EM640FP8 Series
Low Power, 512Kx8 SRAM
(Address Controlled, CS1=OE=VIL, CS2 =WE=V IH )
tRC Address tAA tOH Data Out
Previous Data Valid Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC Address tAA CS 1 CS 2 tHZ tOE OE tOLZ Data Out High-Z
Data Valid
tOH tCO
tOHZ
tLZ
NOTES (READ CYCLE) 1. t HZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ(Min.) both for a given device and from device to device interconnection.
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TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC Address tCW (2) CS 1 CS 2 tAW
EM640FP8 Series
Low Power, 512Kx8 SRAM
tWR (4)
tWP (1) WE tAS(3) Data in High-Z
Data Valid
tDW
tDH High-Z tOW
tWHZ Data out Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC Address tAS(3) CS 1 CS 2 tAW tCW (2) tWR (4)
tWP (1) WE tDW Data in
Data Valid
tDH
Data out
High-Z
High-Z
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TIMING WAVEFORM OF WRITE CYCLE(3) ( CS2 CONTROLLED)
EM640FP8 Series
Low Power, 512Kx8 SRAM
tWC Address tCW(2) CS 1 tAS(3) tW R(4)
CS 2
tAW tW P(1)
WE tDW Data in Data out High-Z
Data Valid
tDH
High-Z
NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP ) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition when CS1 goes high, CS2 goes hagh and WE goes high. The t WP is measured from the beginning of write to the end of write. 2. t CW is measured from the CS1 going low to end of write. 3. t A S is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high.
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DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES
EM640FP8 Series
Low Power, 512Kx8 SRAM
Symbol
VDR I DR tSDR tRDR
Test Condition
ISB1 Test Condition (Chip Disabled)
1)
Min
1.0 0
Typ
-
Max
2.2 2 -
Unit
V A
VCC =1.2V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form
0.5 -
t RC
ns -
1. See the IS B 1 measurement condition of datasheet page 4.
DATA RETENTION WAVE FORM CS1 Controlled
Vcc 1.65V
tSDR
Data Retention Mode
tRDR
1.4V VDR CS1 GND
CS 1 > Vcc-0.2V
CS2 Controlled
Vcc 1.65V CS 2 tSDR
Data Retention Mode
tRDR
VDR 0.4V GND
CS 2 < 0.2V
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PACKAGE DIMENSION
36 Ball Fine Pitch BGA (0.75mm ball pitch) Top View
B
EM640FP8 Series
Low Power, 512Kx8 SRAM
Unit: millimeters
Bottom View
A1 index Mark
B B1 6 A B C 5 4 3 21
0.5 0.5 Y C1 C B/2
#A1
C
D E C1/2 F G H
Side View
0.26 E2 D
0.25 Typ.
Detail A
A
E E1
Min A B B1 C C1 D E E1 E2 Y 5.95 6.95 0.30 1.00 -
Typ 0.75 6.00 3.75 7.00 5.25 0.35 1.04 0.79 0.25 -
Max 6.05 7.05 0.40 1.10 0.08
NOTES. 1. Bump counts : 36(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max)
10
0.79Typ.
C
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MEMORY FUNCTION GUIDE
EM640FP8 Series
Low Power, 512Kx8 SRAM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory 2. Device Type 3. Density 4. Option 5. Technology 6. Operating Voltage
1. Memory Component 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ STRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 4. Option 0 ----------------------- Dual CS 1 ----------------------- Single CS 5. Technology Blank ------------------ CMOS F ------------------------ Full CMOS 6. Operating Voltage Blank ------------------- 5V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 7. Orginzation 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 11
11. Power 10. Speed
9. Packages 8. Version 7. Orgainzation
8. Version Blank ----------------- Mother Die A ----------------------- First revision B ----------------------- Second revision C ----------------------- Third revision D ----------------------- Fourth revision 9. Package Blank ---------------------- Package W --------------------- Wafer 10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free) L ---------------------- Low Power S ---------------------- Standard Power

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