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MB88R157
PIN ASSIGNMENT
TOP VIEW
XOUT OE PEX VSS
1 2 3 4
8 7 6 5
XIN NC VDD OUT
(FPT-8P-M02)
PIN DESCRIPTION
Pin name XOUT OE Pin no. 1 2 I/O O I/O Resonator connection pin Clock output enable pin L : output disable, H : output enable Serial input/output pin (only program mode) Programmable enable setting pin L : program mode, H : normal operation GND pin Modulation clock output pin Power supply voltage pin Non-connection pin (do not connect anything) Resonator connection pin/clock input pin Description
PEX VSS OUT VDD NC XIN
3 4 5 6 7 8
I O I
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I/O CIRCUIT TYPE
Pin name PEX
50 k
Circuit type
Remarks * CMOS hysteresis input * With pull-up resistor (50 k)
OE
50 k
With pull-up resistor (50 k) * CMOS hysteresis input (Input) In serial output mode * CMOS output * IOL = 3 mA
OUT
* CMOS output * IOL = 3 mA/7 mA selectable (Selectable by Output driver setting bit) * Hi-Z or "L" output at OE = "L" (Selectable by OUT pin setting bit)
Note : About XIN and XOUT pins, please refer to the chapter of " CRYSTAL OSCILLATION CIRCUIT".
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HANDLING DEVICES
* Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than power supply voltage or a voltage lower than GND is applied to an input or output pin or (b) a voltage higher than the rating is applied between power supply and GND. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. * Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pulldown resistor. * To use external clock input To use an external clock signal, input the clock signal to the XIN pin with the XOUT pin connected to nothing. * Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between power supply and GND near the device, as a bypass capacitor. * Oscillation circuit Noise near the XIN pin and XOUT pin may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN pin or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN pin and XOUT pin with ground in order to stabilize operation.
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MEMORY MAP
Address bit0-bit11 bit12-bit22 bit23-bit29 bit30-bit32 bit33-bit36 bit37-bit41 bit42-bit44 bit45 bit46 bit47 bit48 bit49-bit55 bit56-bit62 bit63 Function M divider setting (12-bit) N divider setting (11-bit) K divider setting (7-bit) L divider setting (3-bit) Charge Pump setting (4-bit) VCO Gain setting (5-bit) Modulation rate setting (3-bit) OUT pin setting (1bit) Output drive setting (1bit) Source clock dividing mode (1bit) PLL mode setting (1bit) XIN oscillation stabilization capacitance setting (7-bit) XOUT oscillation stabilization capacitance setting (7-bit) Reserve Remarks Selectable in the range of 1 to 4096 Selectable in the range of 1 to 2048 Selectable in the range of 1 to 128 Modulation frequency setting (the value is due to the input frequency) Charge pump current setting due to VCO oscillation frequency VCO gain setting due to VCO oscillation frequency No modulation, 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50%, 1.75% are selectable Selectable OUT pin situation at OE pin = L 0 : L output 1 : Hi-Z output OUT pin driving ability setting 0 : Ability small 1 : Ability large Source clock selectable to K divider 0 : VCO output 1 : Source clock 0 : Normal mode 1 : PLL mode Capacitance is selectable from 5 pF to 10 pF by 0.039 pF Step Capacitance is selectable from 5 pF to 10 pF by 0.039 pF Step
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OPERATION SETTING
* Frequency setting Output frequency can be set by writing the internal memory to each divider parameter in the PLL block. Internal oscillation frequency and output frequency can be calculated following expressions : Internal oscillation frequency (fvco*) = Input frequency (fin) x (M+1) / (N+1) * : Please set the fvco range from 20 MHz to 134 MHz. Output frequency (fOUT*) = Input frequency (fin) x (M+1) / ( (N+1) x K) * : Please set the fOUT range from 1 MHz to 134 MHz. (Setting example) fin = 27 MHz, fOUT = 60 MHz M divider parameter : 1999 ( = 7CFH) , N divider parameter : 899 ( = 383H) , K divider parameter : 1 ( = 01H) 27 x (1999+1) / ( (899+1) x 1) = 60 [MHz] (fvco = 27 x (1999+1) / (899+1) = 60 [MHz]) Note: Recommended value of each divider parameter is different at PLL mode and normal mode. Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. * Modulation frequency setting Modulation frequency can be set by writing the internal memory to L divider parameter. The average of modulation frequency can be calculated following expressions : Input frequency 266 x (L+1)
(L = 1, 2, 3, 4, 5, 6, 7)
Note: Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. * Modulation rate setting Modulation rate can be selectable from no modulation, 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50%, 1.75%. bit44 0 0 0 0 1 1 1 1 bit43 0 0 1 1 0 0 1 1 bit42 0 1 0 1 0 1 0 1 Modulation rate setting No modulation 0.25% 0.50% 0.75% 1.00% 1.25% 1.50% 1.75%
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* Charge Pump setting, VCO gain setting Note: Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. * OUT pin setting OUT pin situation can be selected at OE pin "L" input. bit45 0 1 "L" output "Hi-Z" output OUT pin situation
Note : Internal oscillation circuit has been operating when OE pin is input "L". * Output drive ability setting Output drive ability of OUT pin can be selected. bit46 0 1 OUT pin drive ability Small (IOL = 3 mA) Large (IOL = 7 mA)
* Source clock dividing setting Source clock to K divider can be selected. When "input frequency" is selected, source clock or its divided clock can be output. But modulation setting is not enable. bit47 0 1 Source clock to K divider VCO output clock Input clock (Source clock)
Note: When "input frequency " is selected, internal oscillation circuit has been operating. About M and N divider parameter setting, please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. * PLL mode setting It can be selected normal mode and PLL mode by bit48 setting in the memory map. PLL mode is good jitter specification at non modulation. When the mode is selected, it becomes non modulation setting, the resistance and capacitance value of the loop filter is changed, so oscillation specification is change. bit48 0 1 SSCG mode PLL mode Operation mode
Note: When PLL mode is selected, recommended value of M, N, K divider is changed. Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools.
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MEMORY ACCESS
pa
Read/write to the built-in non-volatile memory is enabled through the serial communication with the OE pin functioned as the I/O pin. Set for the communication protocol. Also, set the transfer speed as 1/512 of the source clock. * Asynchronous transfer mode of UART * LSB fast * NRZ format * Bit length: 8 bits * No parity * Stop bit: 1 bit * Transfer sequence
30 ms
2.5 V
VDD
OE PEX
Memory access mode signal (internal)
OUT
Source clock output 1. Set the PEX pin to "L" more than 30 ms after this device is turned on, input a command from the OE pin set MB88R157 into memory access mode.(When a command is input by serial communication, data of "FDH" is sent.) Note: When memory access is available, source clock can be output from the OUT pin. Fix the PEX pin to "H", or fix the OE pin to "H" or "L" until command input.
2. At writing, "00H" is sent serially, and at reading, "40H" is sent. Note: This device needs to stop outputting to the OE pin of the transferred device within 15 s after transferring "40H" serially at the reading state and place it to a receivable state. 3. At writing : Send 8-byte data blocks from the lower address of the memory map in turn with more than 100 s between each data block. At read : This device outputs 8-byte data blocks from the lower address of the memory map in turn. 4. Repeat the operations of 2. and 3. for re-writing and re-reading. To operate the device using the written data, turn on the power again. However, the oscillation stabilization capacitance is set simultaneously with writing to memory. When the oscillation stabilization capacitance and the crystal oscillation frequency are adjusted, change the oscillation stabilization capacitance value so that the clock output from the OUT pin is set to the desired frequency.
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* Interconnection example
*1
UO UI UCK
OE
MB88R157
Microcontroller with built-in UART etc.
Clock Generator
*2
* 1 : Set the UO pin to Hi-z to read from memory, as the UO pin serves for serial I/O. UO : UART serial data output pin UI : UART serial data input pin UCK : UART serial synchronous clock I/O pin *2 : Because the transfer rate is set to 1/512 of source oscillation in MB88R157, the clock generator is used as shown in above figure, so that the transfer speed is set to 1/512 of source clock in MB88R157. However, the clock generator is not needed if the transfer speed can be maintained from an internal clock of the baud rate generator of the UART.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage* Input voltage* Output voltage* Storage temperature Operation junction temperature Output current Overshoot Undershoot Symbol VDD VI VO TST TJ IO VIOVER VIUNDER Rating Min - 0.5 VSS - 0.5 VSS - 0.5 - 55 - 40 - 14 VSS - 1.0 (tUNDER 50 ns) Max + 4.0 VDD + 0.5 VDD + 0.5 + 125 + 125 + 14 VDD + 1.0 (tOVER 50 ns) Unit V V V C C mA V V
* : This parameter is based on VSS = 0.0 V WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot
tUNDER 50 ns VIOVER VDD + 1.0 V
VDD
Input pin tOVER 50 ns
VSS
VIUNDER VSS - 1.0 V
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RECOMMENDED OPERATING CONDITONS
(VSS = 0.0 V) Parameter Power supply voltage "H" level input voltage "L" level input voltage Input clock duty cycle Symbol VDD VIH VIL tDCI Pin name VDD OE, PEX, XIN XIN Conditions Input slew rate for XIN pin only 3 V/ns 10 MHz to 50 MHz Write to the internal non-volatile memory Operating temperature Ta Operating test after the re-flow Other than those above Value Min 3.0 VDD x 0.80 VSS 40 Typ 3.3 50 Max 3.6 VDD + 0.3 VDD x 0.20 60 Unit V V V % C
+ 20
+ 50
-20
+ 85
C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Input clock duty cycle (tDCI = tb / ta)
ta tb
1.5 V
XIN
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ELECTRICAL CHARACTERISTICS
* DC Characteristics (Ta = - 20 C to + 85 C, VDD = 3.3 V 0.3 V, VSS = 0.0 V) Parameter Symbol Pin name Conditions 24 MHz input (Crystal) , 24 MHz internal oscillation, 24 MHz output no load capacitance 50 MHz input clock, 134 MHz internal oscillation, 134 MHz output 15 pF load capacitance "H" level output Driving voltage (low) IOH = -3 mA, Driving voltage (high) IOH = -7 mA "L" level output Driving voltage (low) IOL = 3 mA, Driving voltage (high) IOL = 7 mA Ta = + 25 C, VDD = VI = 0.0 V, f = 1 MHz Value Min Typ Max Unit
ICC Power supply current ICC2 VDD
5.5
7.0
mA
26
mA
VOH Output voltage VOL Pull-up resistance Load capacitance RPU CIN OE, PEX XIN, OE, PEX OUT
VDD - 0.5
VDD
V
VSS 25
50
0.4 200 16
V k pF
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* AC characteristics (1) (Ta = - 20 C to + 85 C, VDD = 3.3 V 0.3 V, VSS = 0.0 V) Parameter Crystal oscillation frequency Input frequency Internal oscillation frequency Output frequency Sym- Pin bol name fx fin fVCO Conditions Value Min 10 10 20 1 16 Typ Max 40 40 134 134 134 Unit MHz MHz MHz
XIN, Fundamental oscillation XOUT XIN Operation in PLL mode and at non modulation Operation at modulation 0.4 V to 2.4 V load capacitance 15 pF Driving ability small: at 1 MHz to 60 MHz output Driving ability large: at 60 MHz to 134 MHz OUT output Driving ability small Driving ability large VCO clock output At reference clock output VDD 0.2 V to 3.0 V No load capacitance, Ta = + 25 C VDD = 3.3 V OUT ta = 1 / fOUT ta = 1 / fOUT fOUT 2 MHz fOUT< 2 MHz
fOUT
MHz
Output slewing rate
SR
0.3
V/ns
Output impedance Output clock duty cycle Modulation frequency (number of clocks par one modulation) Power supply time Lock-up time
ZO tDCC tDCR
45 tDCI-10*
75 38
55 tDCI+10*
%
fMOD (nMOD) tR tLK
fin/ (224 x fin/ (266 x fin/ (308 x kHz (L+1) ) (L+1) ) (L+1) ) (clks) (224 x (L+1) ) (266 x (L+1) ) (308 x (L+1) ) 0.05 270/fin+5 20 270/fin+10 100 150 2 x ta 2 x ta ms ms psrms
Cycle-cycle jitter
tJC
Output stop time from OE exit. Output start time after OE entry
tOD tOE
ns ns
* : The duty cycle value (tDCR) of the source clock output depends on the duty cycle of input clock tDCI. Either case of A or B will be guaranteed. A. Resonator : Oscillating with the resonator connected with XIN, XOUT B. External clock input : The input level is Full - swing (VSS - VDD).
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DEFINITION of MODULATION FREQUENCY and NUMBER of INPUT CLOCKS PER MODULATION
f (Output frequency)
Modulation wave form
t
FMOD(Min) FMOD(Max)
V
Input clock Clock count
NMOD(Max)
Clock count
NMOD(Min)
t
This product contains the modulation period to realize the efficient EMI reduction. The modulation period FMOD depends on the input frequency and changes between FMOD (Min) and FMOD (Max). Furthermore, the typical value of the electrical characteristics is equivalent to the average value of the modulation period FMOD.
TURNING ON POWER SUPPLY AND LOCK-UP TIME
tR 3.0 V VDD 0.2 V XIN
clock stabilization wait time
tLK
OUT
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OUTPUT CLOCK DUTY CYCLE (tDCC = tb / ta)
ta tb OUT
VDD/2
INPUT FREQUENCY (fin = 1 / tin)
tin
0.8 VDD
XIN
OUTPUT SLEW RATE (SR)
2.4 V
OUT tr tf
0.4 V
Note: SR = (2.4 - 0.4) /tr, SR = (2.4 - 0.4) /tf
CYCLE-CYCLE JITTER (tJC = | tn - tn+1 | )
OUT tn tn+1
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OUTPUT TIMING AT OE CHANGE
* Output stop time from OE exit
OE VDD x 0.2[V]
ta
tOD
OUT
"Hi-z" or "L" (depend on setting of bit 45)
* Output start time after OE entry
VDD x 0.8[V]
OE
tOE
OUT
"Hi-z" or "L" (depend on setting of bit 45)
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* AC characteristics (2) (Serial interface timing) (Ta = - 20 C to + 85 C, VDD = 3.3 V 0.3 V, VSS = 0.0 V) Parameter Cycle time of transfer and receiver Read operation Read command receive OE in read data output Read operation Final read data output OE pin input mode exchanged Symbol Pin name Conditions tSCYC Value Min (tin x 512) x 0.93 15 Typ tin x 512 Max (tin x 512) x 1.025 Unit s s
tRDO
OE
tOTI
65
s
* Command / write data transfer
VDD*0.8
OE
VDD*0.2
D0 tSCYC
D1
D2
D3
D4
D5
D6
D7
* Read operation Output read data
OE D7 Stop bit Hi-z tRDO Start bit D0
Read command received OE pin output
OE D7 Stop bit
Received data
Hi-z tOTI
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INTERCONNECTION CIRCUIT EXAMPLE
Xtal
1 2 3 4 MB88R157
8 7 6 5
R1 C1 C2
C1 : Capacitor of 10 F or higher C2 : Capacitor of about 0.01 F (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device) R1 : Impedance matching resistor for board pattern
CRYSTAL OSCILLATION CIRCUIT
The figure below shows the connection example about general resonator. The oscillation circuit has the built-in feedback resistor (500 k) and oscillation stabilization capacitance (C1 and C2). C1 and C2 value can be changeable by setting bit49 to bit55 and bit56 to bit62 in memory. It is necessary to set suitable parameter for each resonator. To use an external clock signal (without using the resonator), input the clock signal to the XIN pin with the XOUT pin connected to nothing.
Rf (500 k) C1 C2
LSI internal
XIN pin
XOUT pin
LSI external Fundamental resonator
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ORDERING INFORMATION
Part number MB88R157PNF-G-JNE1 MB88R157PNF-G-JN-ERE1 MB88R157PNF-G-JN-EFE1 Package 8-pin plastic SOP (FPT-8P-M02)
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PACKAGE DIMENSION
8-pin plastic SOP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 1.27 mm 3.9 x 5.05 mm Gullwing Plastic mold 1.75 mm MAX 0.06 g
(FPT-8P-M02)
8-pin plastic SOP (FPT-8P-M02)
Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder.
+.010
*1 5.05 -0.20 .199 -.008
8
+0.25
0.22 -0.07 .009 -.003
5
+0.03 +.001
*2 3.900.30 6.000.40 (.154.012) (.236.016)
Details of "A" part 45 1.550.20 (Mounting height) (.061.008) 0.25(.010)
0.40(.016)
1 4
"A"
0~8
1.27(.050)
0.440.08 (.017.003)
0.13(.005)
M
0.500.20 (.020.008) 0.600.15 (.024.006)
0.150.10 (.006.004) (Stand off)
0.10(.004)
(c)2002-2008 FUJITSU MICROELECTRONICS LIMITED F08004S-c-4-8 C
2002 FUJITSU LIMITED F08004S-c-4-7
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/
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MEMO
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MB88R157
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

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