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FUJITSU MICROELECTRONICS DATA SHEET
DS07-12625-3E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95R203
MB95R203
DESCRIPTION
The MB95R203 is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURES
* F2MC-8FX CPU core Instruction set optimized for controllers * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instruction * Bit manipulation instructions etc. * Clock * Selectable Main clock source Main OSC clock (Up to 10 MHz, Maximum Machine clock frequency is 5 MHz) External clock (Up to 20 MHz, Maximum Machine clock frequency is 10 MHz) Internal main CR clock (Typ 1 MHz, Machine clock frequency is 1 MHz) * Selectable Sub clock source Sub OSC clock (32 kHz) Sub internal CR clock (Typ : 100 kHz, Min : 50 kHz, Max : 200 kHz) (Continued)
Copyright(c)2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.8
MB95R203
(Continued) * Timer * 8/16-bit composite timer * Timebase timer * Watch prescaler * UART/SIO * Offers clock asynchronous (UART) or clock synchronous (SIO) serial data transfer * Full duplex double buffer 2C *I * Built-in wake-up function * External interrupt * Interrupt by the edge detection (Select rising edge/falling edge/both edges) * Can be used to recover from low-power consumption modes (also called standby mode) * 8/10-bit A/D converter * 8-bit or 10-bit resolutions can be selected * Low-power consumption (standby) mode * Stop mode * Sleep mode * Watch mode * Timebase timer mode * I/O port : Max 16 * General-purpose I/O ports (Max) : CMOS I/O : 12, N-ch open drain : 4 * On-chip debug * 1 wire serial control * Support serial writing. (Asynchronous mode) * Hardware/Software watchdog timer * Built-in Hardware watchdog timer * Low voltage detection circuit (LVD) * Low voltage detection reset circuit * Circuit to monitor FRAM power supply * Clock supervisor counter (CSV) * Built-in Clock supervise function * Programmable input voltage levels of port * CMOS input level / hysteresis input level * FRAM * Non-volatile memory * 8 Kbytes of FRAM integrated on-chip * FRAM memory security function * Protects the content of FRAM memory
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(Continued) Part number Parameter Watch prescaler MB95R203 Eight different time intervals can be selected. Non-volatile memory Number of read/write cycles : (Min)1010 times (Typ)1011 times Data retention characteristics : 10 years ( + 55 C) Read security function Function to monitor FRAM power supply Sleep mode, Stop mode, Watch mode, timebase timer mode SDIP-24, SOP-20
FRAM
Standby Mode Package
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PIN ASSIGNMENT
(TOP VIEW)
X0 NC X1 Vss X1A/PG2 X0A/PG1 Vcc SCL/P65 RST/PF2 TO10/P62 NC TO11/P63
1 2 3 4 5 6 7 8 9 10 11 12
24pin (DIP-24)
*The number of usable pins is 20.
24 23 22 21 20 19 18 17 16 15 14 13
P12/EC0/DBG NC P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00/HCLK2 P04/INT04/AN04/UI/HCLK1/EC0 P03/INT03/AN03/UO P02/INT02/AN02/UCK P01/AN01 P00/AN00 NC P64/EC1/SDA
(DIP-24P-M07)
(TOP VIEW)
X0 X1 Vss X1A/PG2 X0A/PG1 Vcc SCL/P65 RST/PF2 TO10/P62 TO11/P63
1 2 3 4 5 6 7 8 9 10
20pin (SOP-20)
20 19 18 17 16 15 14 13 12 11
P12/EC0/DBG P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00/HCLK2 P04/INT04/AN04/UI/HCLK1/EC0 P03/INT03/AN03/UO P02/INT02/AN02/UCK P01/AN01 P00/AN00 P64/EC1/SDA
(FPT-20P-M09)
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MB95R203
PIN DESCRIPTION
Pin no. SDIP24 SOP20 1 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 Pin name X0 X1 Vss PG2/X1A PG1/X0A Vcc P65/SCL PF2/RST I/O Circuit type* B B C C I A Function Main clock input oscillation pin Main clock input/output oscillation pin Power supply pin (GND) General-purpose I/O port This pin is also used as Sub clock input/output oscillation pin. General-purpose I/O port This pin is also used as Sub clock input oscillation pin. Power supply pin General-purpose I/O port This pin is also used as I2C clock I/O. General-purpose I/O port This pin is also used as reset pin General-purpose I/O port High current port This pin is also used as 8/16-bit composite timer ch.1 output. General-purpose I/O port This pin is also used as 8/16-bit composite timer ch.1 output. High current port General-purpose I/O port This pin is also used as I2C data I/O. This pin is also used as 8/16-bit composite timer ch.1 clock input. General-purpose I/O port This pin is also used as A/D converter analog input. General-purpose I/O port This pin is also used as A/D converter analog input. General-purpose I/O port This pin is also used as external interrupt input. This pin is also used as A/D converter analog input. This pin is also used as UART/SIO clock I/O. General-purpose I/O port This pin is also used as external interrupt input. This pin is also used as A/D converter analog input. This pin is also used as UART/SIO data output. General-purpose I/O port This pin is also used as external interrupt input. This pin is also used as A/D converter analog input. This pin is also used as UART/SIO data input. This pin is also used as 8/16-bit composite timer ch.0 clock input. (Continued)
10
9
P62/TO10
D
12
10
P63/TO11
D
13
11
P64/SDA/EC1
I
15 16
12 13
P00/AN00 P01/AN01
E E
17
14
P02/INT02/AN02/ UCK
E
18
15
P03/INT03/AN03/ UO
E
19
16
P04/INT04/AN04/ UI/HCLK1/EC0
F
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(Continued) Pin no. SDIP24 SOP20 Pin name
I/O Circuit type*
Function General-purpose I/O port This pin is also used as external interrupt input. This pin is also used as A/D converter analog input. The pins are also used as 8/16-bit compound timer ch.0 output. This pin is also used as the external clock input. General-purpose I/O port High current port This pin is also used as external interrupt input. This pin is also used as 8/16-bit compound timer ch.0 output. General-purpose I/O port This pin is also used as external interrupt input. General-purpose I/O port This pin is also used as DBG input pin. This pin is also used as 8/16-bit composite timer ch.0 clock input. Internal connect pin. Be sure this pin is left open.
20
17
P05/INT05/AN05/ TO00/HCLK2
E
21
18
P06/INT06/TO01
G
22
19
P07/INT07
G
24 2, 11, 14, 23
20
P12/EC0/DBG
H
NC
* : For the I/O circuit type, refer to " I/O CIRCUIT TYPE".
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MB95R203
I/O CIRCUIT TYPE
Type A Circuit
Reset input / Hysteresis input Reset output / Digital output
N-ch
Remarks * N-ch open drain output * Hysteresis input * Reset output
B
X1 X0
Clock input
* Oscillation circuit * High-speed side Feedback resistance : approx. 1 M * CMOS output * Hysteresis input
Standby control
C
R P-ch P-ch
Port select Pull-up control Digital output
N-ch
Digital output Standby control Hysteresis input Clock input
* Oscillation circuit * Low-speed side Feedback resistance : approx. 10 M * CMOS output * Hysteresis input * With pull-up control
X1A
X0A
Standby control / Port select Clock input Port select
R
Digital output
P-ch N-ch
Pull-up control Digital output Digital output Standby control Hysteresis input
D
P-ch
Digital output Digital output
* CMOS output * Hysteresis input
N-ch
Standby control Hysteresis input
(Continued)
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(Continued) Type E
R P-ch P-ch N-ch
Circuit
Pull-up control Digital output Digital output
Remarks * CMOS output * Hysteresis input * With pull-up control
Analog input A/D control Standby control Hysteresis input
F
R P-ch P-ch N-ch
Pull-up control Digital output Digital output
* * * *
CMOS output Hysteresis input CMOS input With pull-up control
Analog input A/D control Standby control Hysteresis input CMOS input
G
R P-ch P-ch N-ch
Pull-up control Digital output Digital output Standby control Hysteresis input
* Hysteresis input * CMOS output * With pull-up control
H
Hysteresis input Digital output
N-ch
* N-ch open drain output * Hysteresis input
I
N-ch
Digital output CMOS input
* N-ch open drain output * CMOS input * Hysteresis input
Standby control
Hysteresis input
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MB95R203
NOTES ON DEVICE HANDLING
* Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. * Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power-supply voltage. For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range (50 Hz / 60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. * Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode. * Do not use a sample used in program development as mass-produced product.
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PIN CONNECTION
* Treatment of Unused Input Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. * Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device. * DBG Pin Connect the DBG pin directly to external Pull-up. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the DBG pins to VCC or VSS pins. The DBG pin should not stay at "L" level after power-on until the reset output is released. * RST Pin Connect the RST pin directly to Pull-up. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the RST pins to VCC or VSS pins. The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output can be enabled by the RSTOE bit of the SYSC register, and the reset input function or the general purpose I/O function can be selected by the RSTEN bit of the SYSC register. * Example of DBG / RST connection diagram
R DBG R RST
Pull-up resistor recommended resistance For DBG pin : R = 4.7 k For RST pin : R = 10 k
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MB95R203
RESTRICTIONS
* Data written to FRAM before IR reflow is not guaranteed to retain after IR reflow. (Data written to FRAM might be broken by heart processing at IR reflow.)
NOTES ON DEBUG
* Although the [Upload Flash Memory] button is enabled, clicking it does not start the actual processing. * When you click on the [Erase Flash Memory] button on SOFTUNE Workbench, data is overwritten into the FRAM area, as shown below. Address Data to be overwritten F554H FAAAH FFBCH FFBDH Entire FRAM except the above 55H A0H Indeterminate Indeterminate FFH
* Be very careful not to apply voltages to the pins PF2/RST in excess of the absolute maximum ratings. Especially when handling devices in the environment compatible to the package, such as MB95F200H/210H and so on, the voltage may be erroneously applied to the pins PF2/RST in excess of the maximum rating and it may cause thermal breakdown of the device.
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BLOCK DIAGRAM
F2MC-8FX CPU
PF2*1/RST*2 X1 X0 PG2/X1A*2 PG1/X0A*2
Reset
LVD FRAM (8 Kbytes) with security RAM (496 bytes)
Oscillator circuit
CR Oscillator
Clock control P12*1/DBG On-chip debug Wild register P02/INT02 to P07/INT07 P65*1/SCL*1 P64*1/SDA*1 (P02/UCK) (P04/UI) (P03/UO) External interrupt I2C 8/10-bit A/D converter UART/SIO 8/16-bit composite timer (1) 8/16-bit composite timer (0)
(P05/TO00) (P06/TO01) P12/EC0(P04/EC0) P62/TO10 P63/TO11 (P64/EC1)
(P00/AN00 to P05/AN05)
Port VCC VSS *1 : P12, P64, P65, PF2 is N-ch open drain *2 : Software option
Port
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MB95R203
CPU CORE
1. Memory space
Memory space of the MB95R203 is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95R203 shown below. * Memory Map
MB95R203
0000H 0080H 0090H 0100H 0200H 0280H 0F80H 1000H I/O RAM 496 B Register Extension I/O
-
E000H FRAM 8 KB FFFFH
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I/O MAP
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH to 0015H 0016H 0017H 0018H to 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0034H 0035H 0036H 0037H 0038H 0039H Register abbreviation PDR0 DDR0 PDR1 DDR1 WATR SYCC STBC RSRR TBTC WPCR WDTC SYCC2 PDR6 DDR6 PDRF DDRF PDRG DDRG PUL0 PULG T01CR1 T00CR1 T11CR1 T10CR1 Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (disabled) Oscillation stabilization wait time setting register (disabled) System clock control register Standby control register Reset source register Timebase timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 (disabled) Port 6 data register Port 6 direction register (disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register (disabled) Port G pull-up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 11111111B XXXXXX11B 00000XXXB XXXXXXXXB 00000000B 00000000B 00000000B XX100011B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
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MB95R203
(Continued) Address 0F99H 0F9AH 0F9BH 0F9CH to 0FBDH 0FBEH 0FBFH 0FC0H to 0FC2H 0FC3H 0FC4H to 0FE3H 0FE4H 0FE5H 0FE6H, 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH to 0FFFH Register abbreviation T11DR T10DR TMCR1 PSSR0 BRSR0 AIDRL CRTH CRTL SYSC CMCR CMDR WDTH WDTL ILSR Register name 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 8/16-bit compound timer 10/11 timer mode control register ch.1 (disabled) UART/SIO prescaler select register UART/SIO baud rate setting register (disabled) A/D input disable register lower (disabled) CR-trimming register upper CR-trimming register lower (disabled) System control register Clock monitor control register Clock monitor data register Watchdog ID register upper Watchdog ID register lower (disabled) Input level select register (disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 1XXXXXXXB 000XXXXXB 11000-11B --000000B 00000000B XXXXXXXXB XXXXXXXXB -----0--B
* R/W access symbols R/W : Readable / Writable R : Read only W : Write only * Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. Note : Do not write to the " (Disabled) ". Reading the " (Disabled) " returns an undefined value. 18 DS07-12625-3E
MB95R203
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage*1 Input voltage*1 Output voltage
*1
Symbol Vcc VI1 VI2 VO IOL1 IOL2
Rating Min Max Vss - 0.3 Vss + 4.0 Vss - 0.3 Vss + 4.0 Vss - 0.3 Vss + 6.0 Vss - 0.3 Vss + 4.0 15 15
Unit V V V V mA
Remarks
Other than P64, P65*2 P64, P65 *2 Other than P05, P06, P62 and P63 P05, P06, P62 and P63 Other than P05, P06, P62 and P63 Average output current = operating current x operating ratio (1pin) P05, P06, P62 and P63 Average output current = operating current x operating ratio (1pin)
"L" level maximum output current
IOLAV1 "L" level average current IOLAV2
4 mA 12
"L" level total maximum output current "L" level total average output current "H" level maximum output current
IOL IOLAV IOH1 IOH2

100
mA Total average output current = operating current x operating ratio (Total of pins) Other than P05, P06, P62 and P63 P05, P06, P62 and P63 Other than P05, P06, P62 and P63 Average output current = operating current x operating ratio (1 pin) P05, P06, P62 and P63 Average output current = operating current x operating ratio (1pin)
50 -15 -15 -4
mA
mA
IOHAV1 "H" level average current IOHAV2
mA -8
"H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
IOH IOHAV Pd TA Tstg
-20 -20
-100 -50 320 + 70 + 85
mA Total average output current = operating current x operating ratio (Total of pins)
mA mW C C
(Continued)
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(Continued) *1 : The parameter is based on VSS = 0.0 V. *2 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB95R203
2. Recommended Operating Conditions
(VSS = 0.0 V) Parameter Symbol Rating Min 2.7 Power supply voltage Vcc 3.0 2.6 Operating temperature TA -20 +5 Max 3.6 3.6 3.6 +70 +35 C C V Unit Remarks In normal operating On-chip debug mode Hold condition in STOP mode Other than on-chip debug mode On-chip debug mode
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
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3. DC Characteristics
(Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Parameter Symbol Pin name Condition Value Min 0.7 VCC Typ Max VCC + 0.3 Unit Remarks When CMOS input level (Hysteresis input) is selected When CMOS input level (Hysteresis input) is selected
VIH1
P04
*1
V
VIH2 "H" level input voltage VIHS1
P64, P65 P00 to P07, P12, P62, P63, PG1, PG2 P64, P65 PF2 P04, P64, P65 P00 to P07, P12, P62 to P65, PG1, PG2 PF2 P64, P65 PF2, P12 Output pins other than P05, P06, P62 to P65, PF2, P12 P05, P06, P62, P63 Output pins other than P05, P06, P62, P63 P05, P06, P62, P63
*1
0.7 VCC
VSS + 5.5
V
*1
0.8 VCC

VCC + 0.3 VSS + 5.5 VCC + 0.3 0.3 VCC
V
Hysteresis input
VIHS2 VIHM VIL "L" level input voltage
*1 *1
0.8 VCC 0.8 VCC VSS - 0.3
V V V
Hysteresis input Hysteresis input When CMOS input level (Hysteresis input) is selected
VILS
*1
VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3

0.2 VCC
V
Hysteresis input
VILM Open-drain output application voltage VD1 VD2
0.3 VCC VSS + 5.5 0.2 VCC
V V V
Hysteresis input
"H" level output voltage
VOH1
IOH = -4.0 mA
2.4
V
VOH2
IOH = -8.0 mA
2.4
V
"L" level output voltage
VOL1
IOL = 4.0 mA
0.4
V
VOL2
IOL = 12.0 mA
0.4
V (Continued)
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MB95R203
(Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Parameter Input leak current (Hi-Z output leak current) Open-drain output leak current Pull-up resistance Input capacitance Symbol Pin name Other than ports P64, P65 Condition Value Min -5 Typ Max +5 Unit Remarks When pull-up resistance is disabled
ILI
0.0 V < VI < VCC
A
ILIOD
P64, P65
0.0 V < VI < VSS + 5.5 V VI = 0.0 V f = 1 MHz FCH = 20 MHz, FMP = 10 MHz Main clock mode (divided by 2) FCH = 20 MHz, FMP = 10 MHz Main sleep mode (divided by 2)
+5
A When pull-up resistance is enabled
RPULL
P00 to P07, PG1, PG2 Other than Vcc, Vss
25
50
100
k
CIN
5 6 8
15 9 12
pF mA mA At A/D conversion
ICC
ICCS
3
5
mA
ICCL
Vcc (External clock operation)
FCL = 32 kHz, FMPL = 16 kHz Sub clock mode (divided by 2) TA = +25 C FCL = 32 kHz, FMPL = 16 kHz Sub sleep mode (divided by 2) TA = +25 C FCL = 32 kHz, Watch mode Main stop mode TA = +25 C FCRH = 1 MHz, FMP = 1 MHz Main CR clock mode Sub CR clock mode (divided by 2) TA = +25 C
30
70
A
Power supply current*2
ICCLS
5
40
A
ICCT
3
18
A
ICCMCR Vcc ICCSCR
2
mA
80
300
A (Continued)
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(Continued) (Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Symbol Pin name Condition FCH = 10 MHz, Timebase timer mode TA = +25 C Sub stop mode TA = +25 C Current consumption of internal main CR oscillator VCC ICRL At oscillating 100 kHz current consumption of internal sub CR oscillator Value Min Typ Max Unit Remarks
Parameter
ICCTS
ICCH Power supply current*2
Vcc (External clock operation)
1
3
mA
1
10
A
ICRH
0.2
0.3
mA
20
72
A
*1 : P04, P64, P65 can switch the input level to either the "CMOS input level" or "hysteresis input level". The switching of the input level can be set by the input level selection register (ILSR) . *2 : * The power-supply current is determined by the external clock. when Internal CR are selected, the powersupply current will be a value of adding current consumption of internal CR oscillator (ICRL) to the specified value. * Refer to "4. AC Characteristics (1) Clock Timing" for FCH and FCL. * Refer to "4. AC Characteristics (2) Source Clock/Machine Clock" for FMP and FMPL.
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4. AC Characteristics
(1) Clock Timing (Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Parameter SymCondiPin name bol tion X0, X1 FCH X0, X1, HCLK1, HCLK2 Value Min 1 Typ Max 10 Unit MHz Remarks When the main oscillation circuit is used When the main external clock is used
1
20
MHz
Clock frequency
FCRH
0.95
1
1.05
When the main internal CR clock is used MHz (3.0 V VCC 3.6 V, + 5 C TA + 35 C) MHz kHz kHz ns When the sub oscillation circuit is used When the sub external clock is used When the sub internal CR clock is used When the main oscillation circuit is used When the main external clock is used When using sub clock When the external clock is used, the duty ratio should range between 40% and 60% When the external clock is used When the main-internal CR clock is used When the sub-internal CR clock is used
FCL X0A, X1A FCRL X0, X1 Clock cycle time tHCYL X0, X1, HCLK1, HCLK2 X0A, X1A X0, HCLK1, HCLK2 X0A X0, X0A, HCLK1, HCLK2 50 100
32.768 32.768 100 30.5
200 1000
50 20
1000
ns s ns
tLCYL tWH1 Input clock pulse width tWL1 tWH2 tWL2 Input clock rise time and fall time tCR tCF tCRHWK tCRLWK

15.2
s

5
ns s s
Internal CR oscillation start time
10 10
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tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1
X0, HCLK1, HCLK2
* Figure of main clock input port external connection When using a crystal or Ceramic oscillator When using external clock
X0
X1 FCH
X0
X1
Open
FCH
tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL2
X0A
* Figure of sub clock input port external connection When using a crystal or Ceramic oscillator
When using external clock
X0A
X1A FCL
X0A
X1A
Open
FCL
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MB95R203
(2) Source Clock/Machine Clock (Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Parameter Symbol Pin name Value Min 100 Source clock cycle time*1 (Clock before division) FSP Source clock frequency FSPL 0.5 100 Typ 1 61 20 1 16.384 50 Max 2000 10 32000 Unit Remarks When using main external clock Min : FCH = 20 MHz, divided by 2 Max : FCH = 1 MHz, divided by 2 When using main CR oscillation clock FCRH = 1 MHz When using sub oscillation clock FCL = 32.768 kHz, divided by 2 When using sub oscillation clock FCRL = 100 kHz, divided by 2
ns s s s
tSCLK
MHz When using main oscillation clock MHz When using main CR oscillation clock kHz When using sub oscillation clock kHz When using sub CR clock ns When using main oscillation clock Min : FSP = 10 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using main CR clock Min : FSP = 1 MHz, no division Max : FSP = 1 MHz, divided by 16 When using sub oscillation clock Min : FSPL = 16.384 kHz, no division Max : FSPL = 16.384 kHz, divided by 16 When using sub CR clock Min : FSPL = 50 kHz, no division Max : FSPL = 50 kHz, divided by 16
Machine clock cycle time*2 (Minimum instruction execution time)
1 tMCLK 61
16
s
976.5
s
20 0.031 FMPL 0.0625 1.024 3.125 300

320 10 1 16.384 50 96000
s
FMP Machine clock frequency
MHz When using main oscillation clock MHz When using main CR clock kHz When using sub oscillation clock kHz When using sub CR clock ns When using main oscillation clock Min : FSP = 10 MHz, divided by 3 Max : FSP = 0.5 MHz, divided by 48 When using main CR clock Min : FSP=1 MHz, divided by 3 Max : FSP=1 MHz, divided by 48 When using sub oscillation clock Min : FSPL = 16.384 kHz, divided by 3 Max : FSPL = 16.384 kHz, divided by 48 When using sub CR clock Min : FSPL = 50 kHz, divided by 3 Max : FSPL = 50 kHz, divided by 48 (Continued)
FRAM clock cycle time*3 (Minimum instruction execution time)
3 tFCLK 183
48
s
2929.7
s
60
960
s
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(Continued) Parameter Symbol FFCLK FRAM clock frequency FFCLKL Pin name Value Min 0.010 0.0208 0.341 1.042 Typ Max 3.3 5.461 16.667 Unit Remarks
MHz When using main oscillation clock kHz When using sub oscillation clock kHz When using sub CR clock
0.3333 MHz When using main CR clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. * Main clock divided by 2 * Main CR clock * Sub clock divided by 2 * Sub CR clock divided by 2 *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. * Source clock (no division) * Source clock divided by 4 * Source clock divided by 8 * Source clock divided by 16 *3 : The clock in case of operating code on FRAM, or Read/Write access to FRAM. Its value is machine clock divided by 3. * Outline of clock generation block
FCH (main oscillation) FCRH (Internal main CR clock) FCL (sub oscillation) Divided by 2 Division Circuit x1 x 1/4 x 1/8 x 1/16 Divided by 3
Divided by 2 Divided by 2
SCLK (source clock)
MCLK (machine clock)
FCRL (Internal sub CR clock)
Clock mode select bit (SYCC2:RCS1, RCS0)
FCLK (FRAM clock)
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MB95R203
* Operating voltage - Operating frequency (When TA = - 20 C to + 70 C)
3.6
Operating voltage (V)
3.3 A/D converter operation range 3.0
2.7
2.4
16 kHz
3 MHz
10 MHz
Source clock frequency (FSP)
30
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(3) External Reset (Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Parameter Symbol Value Min 2 tMCLK*1 RST "L" level pulse width tRSTL Oscillation time of oscillator*2 + 100 100 *1 : Refer to " (2) Source Clock/Machine Clock" for tMCLK. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of s and several ms. In the external clock, the oscillation time is 0 ms. Max Unit ns s s Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode At time-base timer mode
* At normal operating
tRSTL
RST
0.2 VCC 0.2 VCC
* At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST 90% of amplitude X0
Internal operating clock
tRSTL 0.2 VCC 0.2 VCC
100 s
Oscillation time of Oscillation stabilization wait time oscillator Internal reset Execute instruction
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(4) Power-on Reset (Vss = 0.0 V, TA = -20 C to +70 C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions Value Min 1 Max 50 Unit ms ms Waiting time until power-on Remarks
tR 2.5 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Note: Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
VCC
2.6 V
Limiting the slope of rising within 30 mV/ms is recommended. Hold Condition in stop mode
VSS
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(5) Peripheral Input Timing (Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Parameter Peripheral input "H" pulse Peripheral input "L" pulse Symbol tILIH tIHIL Pin name INT02 to INT07, EC0, EC1 Value Min 2 tMCLK* 2 tMCLK* Max Unit ns ns
* : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tILIH
tIHIL
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
INT02 to INT07, EC0, EC1
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(6) UART/SIO, Serial I/O Timing (Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Parameter Serial clock cycle time UCK UO time Valid UI UCK UCK valid UI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK UO time Valid UI UCK UCK valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK UCK, UO UCK,UI UCK, UI UCK UCK UCK, UO UCK, UI UCK, UI External clock operation output pin : CL = 80 pF + 1 TTL. Internal clock operation output pin : CL = 80 pF + 1 TTL. Conditions Value Min 4 tMCLK* -190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* 0 2 tMCLK* 2 tMCLK* Max +190 190 Unit ns ns ns ns ns ns ns ns ns
* : Refer to " (2) Source Clock/Machine Clock" for details on tMCLK.
* Internal shift clock mode
tSCYC
UCK
2.4 V 0.8 V tSLOV 0.8 V
UO
2.4 V 0.8 V tIVSH tSHIX
UI
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV
UCK
UO
2.4 V 0.8 V tIVSH tSHIX
UI
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
34
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(7) I2C Timing (Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Value Parameter Symbol Pin name SCL SCL SDA SCL SCL SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA R = 1.7 k, C = 50 pF*1 Conditions Standardmode Min SCL clock frequency (Repeat) Start condition hold time SDA SCL SCL clock "L" width SCL clock "H" width (Repeat) Start condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL Stop condition setup time SCL SDA Bus free time between stop condition and start condition tSCYC tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF 0 4.0 4.7 4.0 4.7 0 0.25 4.0 4.7 Max 100 3.45*2 Fast-mode Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 0.9*3 kHz s s s s s s s s Unit
*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines. *2 : The maximum value of tHD;DAT is applicable only if the device does not extend the "L" width (tLOW) of the SCL signal. *3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met.
tWAKEUP SDA tLOW SCL tHD;STA tSU;DAT tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF
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(Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Parameter SCL clock "L" width SCL clock "H" width Symbol tLOW tHIGH Pin name SCL SCL Conditions Value*2 Min (2 + nm / 2) tMCLK - 20 (nm / 2) tMCLK - 20 Max (nm / 2) tMCLK + 20 Unit ns ns Remarks Master mode Master mode Master mode maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applid. Master mode Master mode
Start condition hold time
tHD;STA
SCL SDA
(-1 + nm / 2) tMCLK - 20
(-1 + nm / 2) tMCLK + 20
ns
Stop condition setup time Start condition setup time Bus free time between stop condition and start condition Data hold time
tSU;STO tSU;STA
SCL SDA SCL SDA SCL SDA SCL SDA
(1 + nm / 2) tMCLK (1 + nm / 2) tMCLK - 20 + 20 (1 + nm / 2) tMCLK (1 + nm / 2) tMCLK - 20 + 20 (2 nm + 4) tMCLK - 20 3 tMCLK - 20 R = 1.7 k, C = 50 pF*1
ns ns
tBUF
ns
tHD;DAT
ns
Master mode Master mode When assuming that "L" of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL. Maximum value is applied to interrupt at 8th SCL. At reception At reception Undetected when 1 tMCLK is used at reception (Continued)
Data setup time
tSU;DAT
SCL SDA
(-2 + nm / 2) tMCLK - 20
(-1 + nm / 2) tMCLK + 20
ns
Setup time between cleaning interrupt and SCL rising SCL clock "L" width SCL clock "H" width Start condition detection
tSU;INT
SCL
(nm / 2) tMCLK - 20
(1 + nm / 2) tMCLK + 20
ns
tLOW tHIGH
SCL SCL SCL SDA
4 tMCLK - 20 4 tMCLK - 20 4 tMCLK - 20

ns ns
tHD;STA
ns
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(Continued) Pin name SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA R = 1.7 k, C = 50 pF*1 Conditions (Vcc = 3.3 V, Vss = 0.0 V, TA = -20 C to +70 C) Symbol tSU;STO tSU;STA tBUF tHD;DAT tSU;DAT tHD;DAT tSU;DAT Value*2 Min 4 tMCLK - 20 2 tMCLK - 20 2 tMCLK - 20 2 tMCLK - 20 tLOW - 3 tMCLK - 20 0 tMCLK - 20 Oscillation stabilization wait time + 2 tMCLK - 20 Max Unit ns ns ns ns ns ns ns Remarks Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception During reception In slave transmission mode In slave transmission mode During reception During reception
Parameter Stop condition detection Restart condition detection condition Bus free time Data hold time Data setup time Data hold time Data setup time SDA SCL (when using wakeup function)
tWAKEUP
ns
*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines. *2 : * Refer to " (2) Source Clock/Machine Clock" for details on tMCLK. * m is the CS4 and CS3 bits (bit 4 and bit 3) of the I2C clock control register (ICCR0) . * n is the CS2 to CS0 bits (bit 2 to bit0) of the I2C clock control register (ICCR0) . * The actual I2C timing is determined by the machine (tMCLK) and the values of m and n configured in bits CS4 to CS0 of the I2C clock control register (ICCR0) . * Standard-mode : m and n can be set in the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. The machine clock to be used is determined by the settings of m and n as follows. (m, n) = (1, 8) : 0.9 MHz < tMCLK 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK 1 MHz * Fast-mode : m and n can be set in the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. The machine clock to be used is determined by the settings of m and n as follows. (m, n) = (1, 8) : 3.3 MHz < tMCLK 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK 10 MHz
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MB95R203
VCC
Von
Voff
time
tf tr
VDL+ VHYS VDL-
Internal reset signal time
td2 td1
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MB95R203
(2) Notes on Using A/D Converter * About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input equivalent circuit
Analog input
R C
Comparator
During sampling : ON 2.7 V Vcc 3.6 V : R = 1.7 k (Max) , C = 14.5 pF (Max) : : Note : The values are reference values.
* The relationship between external impedance and minimum sampling time. [External impedance = 0 k to 100 k] External impedance [k] External impedance [k]
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40
[External impedance = 0 k to 20 k]
20 18 16 14 12 10 8 6 4 2 0 0
Minimum sampling time [s]
Minimum sampling time [s]
1
2
3
4
* About errors |VCC - VSS| becomes smaller, values of relative errors grow larger.
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MB95R203
(Continued) Zero transition error
004
Actual conversion characteristic
3FF
Full-scale transition error
Ideal characteristics Actual conversion characteristic
Digital output
003
Ideal characteristics
Digital output
3FE
002
Actual conversion characteristic
VFST
3FD
(measurement value)
001
VOT (measurement value)
3FC
Actual conversion characteristic
VSS
VCC
VSS
VCC
Analog input
Analog input
Linearity error
3FF 3FE
Actual conversion characteristic
Differential linear error
Ideal characteristics
N+1 {1 LSB x N + VOT}
VFST
(measure-
Digital output
Digital output
3FD
Actual conversion characteristic
V (N+1) T N
ment value) VNT
004 003 002 001 VSS
Actual conversion characteristic Ideal characteristics
N-1
VNT
Actual conversion characteristic
N-2
VOT (measurement value)
Analog input
VCC
VSS
Analog input
VCC
Linearity error in = VNT - {1 LSB x N + VOT} 1 LSB digital output N
Differential linear error = V (N + 1) T - VNT 1 LSB In digital output N
-1
N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N. VOT (Ideal value) = VSS + 0.5 LSB [V] VFST (Ideal value) = VCC - 2.0 LSB [V]
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6. FRAM Characteristics
Parameter Number of read/write cycle Value Min 1010 Typ 1011 Max Unit cycle Remarks
44
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EXAMPLE CHARACTERISTICS
* Power supply current and temperature ICC - VCC TA = + 25 C, FMP = 2, 3, 8, 10 MHz (divided by 2) Main clock mode, at external clock operating
10 8 ICC [mA] 6 4 2 0 2.5 3 VCC [V] 3.5 4
ICC [mA]
ICC - TA VCC = 3.6 V, FMP = 10 MHz (divided by 2) Main clock mode, at external clock operating
10 8 6 4 2 0
10 MHz 8 MHz 4 MHz 2 MHz
-40
0 TA [C]
+40
+80
ICCS - VCC TA = + 25 C, FMP = 2, 3, 8, 10 MHz (divided by 2) Main sleep mode, at external clock operating
10 8 ICCS [mA] 6 4 2 0 2.5 3 VCC [V] 3.5
ICCS - TA VCC = 3.6 V, FMP = 10 MHz(divided by 2) Main sleep mode, at external clock operating
10 8
ICCS [mA]
6 4 2 0 -40
10 MHz 8 MHz 4 MHz 2 MHz
4
0 TA [C]
+40
+80
ICCL - VCC TA = + 25 C, FMPL = 16 kHz (divided by 2) Sub clock mode, at external clock operating
80
ICCL - TA VCC = 3.6 V, FMPL = 16 kHz (divided by 2) Sub clock mode, at external clock operating
80 60 ICCL [A]
60
ICCL [A]
40
40 20 0 -40
20
0 2.5 3
VCC [V]
3.5
4
0 TA [C]
+40
+80
(Continued) DS07-12625-3E 45
MB95R203
ICCLS - VCC TA = + 25 C, FMPL = 16 kHz (divided by 2) Sub sleep mode, at external clock operating
50 40
ICCLS [A]
ICCLS [A]
ICCLS - TA VCC = 3.6 V, FMPL = 16 kHz (divided by 2) Sub sleep mode, at external clock operating
50 40 30 20 10 0
2.5 3 VCC [V] 3.5 4
-40 0 TA [C] +40 +80
30 20 10 0
ICCT - VCC TA = + 25 C, FMPL = 16 kHz (divided by 2) Clock mode, at external clock operating
20
ICCT VCC = 3.6 V, FMPL = 16 kHz (divided by 2) Clock mode, at external clock operating
20
15
ICCT [A]
ICCT [A]
15
10
10
5
5
0 2.5 3 VCC [V] 3.5 4
0 -40 0 TA [C] +40 +80
ICTS - VCC TA = + 25 C, FMP = 2, 4, 8, 10 MHz (divided by 2) Time-base timer mode, at external clock operating
2
ICTS - TA VCC = 3.6 V, FMP = 10 kHz (divided by 2) Time-base timer mode, at external clock operating
2
1.5
ICCTS [mA]
1.5
ICTS [A]
1
1
0.5
10MHz 8MHz 4MHz 2MHz
VCC [V]
0.5
0
0 -40 0 TA [C] +40 +80
(Continued) 46 DS07-12625-3E
MB95R203
(Continued) ICCH - VCC TA = + 25 C, FMPL = (stop) Sub stop mode, at external clock stopping
20
ICCH - TA VCC = 3.6 V, FMPL = (stop) Sub stop mode, at external clock stopping
20
15
ICCH [A]
15
ICCH [A]
10
10
5
5
0 2.5
3 VCC [V]
3.5
4
0 -40
0 TA [C]
+40
+80
ICCMCR - VCC ICCMCR - TA TA = + 25 C, FMP = 1 MHz (No divided) VCC = 3.6 V, FMP = 1 MHz (No divided) Main clock mode, at internal main CR clock operating Main clock mode, at internal main CR clock operating
2
2
ICCMCR [mA]
1.5
ICCMCR [mA]
1.5
1
1
0.5
0.5
0 2.5
0
3 VCC [V] 3.5 4
-40
0 TA [C]
+40
+80
ICCSCR - VCC TA = + 25 C, FMPL = 50 kHz (divided by 2) Sub clock mode, at internal sub CR clock operating
200
ICCSCR - TA VCC = 3.6 V, FMPL = 50 kHz (divided by 2) Sub clock mode, at internal sub CR clock operating
200 150
ICCSCR [A]
150
ICCSCR [A]
100
100 50 0
50
0 2.5
3 VCC [V]
3.5
4
-40
0 TA [C]
+40
+80
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MB95R203
* Input voltage VIHI1, VIH2, VIHS1, VIHS2, VIHM - VCC and VIL, VILS, VILM - VCC TA = + 25 C
3.5 3 2.5
VIH / VIL [V]
2 1.5 1 0.5 0 2.5 3 VCC [V] 3.5
VIH VIL
4
48
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ORDERING INFORMATION
Part number MB95R203P-G-SH-JNE2 MB95R203PF-G-JNE2 Package 24-pin plastic SDIP (DIP-24P-M07) 20-pin plastic SOP (FPT-20P-M09) Remarks
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MB95R203
PACKAGE DIMENSIONS
24-pin plastic DIP Lead pitch Package width x package length Sealing method Mounting height 1.778 mm 6.40 mm x 22.86 mm Plastic mold 4.80 mm Max
(DIP-24P-M07)
24-pin plastic DIP (DIP-24P-M07)
#22.860.10(.900.004)
24
Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion.
13
INDEX
BTM E-MARK 6.400.10 (.252.004)
1
12
7.62(.300) TYP.
4.80(.189)MAX
0.50(.020) MIN
+0.10
3.00 -0.30 .118 -.012
+0.20
+.008
0.25 -0.04 .010 -.002 1.000.10 (.039.004) 0.43 -0.04 .017 -.002
+0.09
+.004
1.778(.070)
+.004
C
2008 FUJITSU MICROELECTRONICS LIMITED D24066S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
52
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(Continued)
20-pin plastic SOP Lead pitch Package width x package length Lead shape Lead bend direction Sealing method Mounting height 1.27 mm 7.50 mm x 12.70 mm Gullwing Normal bend Plastic mold 2.65 mm Max
(FPT-20P-M09)
20-pin plastic SOP (FPT-20P-M09)
#12.700.10(.500.004)
20 11
Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion.
0.25 .010 -.001
+0.07 -0.02 +.003
BTM E-MARK
#7.500.10 10.2 -0.20 (.295.004) .402 +.016 -.008 INDEX Details of "A" part +0.13 2.52 -0.17 (Mounting height) +.005 .099 -.007
+0.40
1
10
+0.09 -0.05 +.004 -.002
"A" 0~8
1.27(.050)
0.40 .016
0.25(.010)
M
0.80 -0.30
+0.47 +.019
.031 -.012
0.200.10 (.008.004) (Stand off)
0.10(.004)
C
2008 FUJITSU MICROELECTRONICS LIMITED F20030S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/
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MAIN CHANGES IN THIS EDITION
Page 4 I/O CIRCUIT TYPE NOTES ON DEBUG I/O MAP 15 Section PRODUCT OVERVIEW Change Results Preliminary Data Sheet Data Sheet Corrected number of read/write cycles for FRAM. 1011 times (Min)1010 times (Typ)1011 times Corrected the remarks of Type G. CMOS input CMOS output Corrected the address. F555H F554H Corrected the register abbreviation and the register name for address 000BH. WTCR WPCR Watch timer control register Watch prescaler control register Changed the register name for address 0F89H, 0F8AH, and 0F8BH to (disabled). ELECTRICAL CHARACTERISTICS 3. DC Characteristics 4. AC Characteristics (4) Power-on Reset Added "TA = + 25 C" to the condition for "Power supply current (ICCLS)". Corrected the voltage for "Hold Condition in stop mode". 2.3 V 2.6 V Added the section.
9 12
17 24 32
45 to 50 EXAMPLE CHARACTERISTICS
The vertical lines marked in the left side of the page show the changes.
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MEMO
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FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

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