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PCA85133
Universal LCD driver for low multiplex rates
Rev. 1 -- 23 October 2009 Product data sheet
1. General description
The PCA85133 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 80 segments and can easily be cascaded for larger LCD applications. The PCA85133 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). AEC-Q100 compliant for automotive applications.
2. Features
I I I I I I Single-chip LCD controller and driver Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 12, or 13 Selectable frame frequency: 82 Hz or 110 Hz Internal LCD bias generation with voltage-follower buffers 80 segment drives: N Up to 40 7-segment alphanumeric characters N Up to 21 14-segment alphanumeric characters N Any graphics of up to 320 elements 80 x 4 bit RAM for display data storage Auto-incremental display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide LCD supply range for low-threshold LCDs, for guest-host LCDs, and high-threshold (automobile) twisted nematic LCDs: from 2.5 V to 8.0 V Low power consumption 400 kHz I2C-bus interface Compatible with 4-bit, 8-bit, or 16-bit microprocessors or microcontrollers May be cascaded for large LCD applications (up to 5120 segments possible) No external components needed Compatible with Chip-On-Glass (COG) technology
I I I I I I I I I I I I I
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17.
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PCA85133
Universal LCD driver for low multiplex rates
I Manufactured using silicon gate CMOS process
3. Ordering information
Table 1. Ordering information Package Name Description Delivery form[1] Version PCA85133 Type number
PCA85133U/2DA/Q1 PCA85133 bare die; 110 bumps; 4.16 x 1.07 x 0.40 mm chip with hard bumps in tray PCA85133 PCA85133U/2DB/Q1 PCA85133 bare die; 110 bumps; 4.16 x 1.07 x 0.40 mm chip with soft bumps in tray
[1] Bump hardness see Table 20.
4. Marking
Table 2. Marking codes Marking code PC85133-1 PC85133-1 Type number PCA85133U/2DA/Q1 PCA85133U/2DB/Q1
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PCA85133
Universal LCD driver for low multiplex rates
5. Block diagram
BP0 BP1 BP2 BP3 S0 to S79
80
VLCD
BACKPLANE OUTPUTS
DISPLAY SEGMENT OUTPUTS
LCD VOLTAGE SELECTOR
DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT AND BLINK CONTROL
VSS
LCD BIAS GENERATOR
PCA85133
CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE
DISPLAY RAM
OSC OSCILLATOR FF
POWER-ON RESET
COMMAND DECODE
WRITE DATA CONTROL
DATA POINTER AND AUTO INCREMENT
SCL SDA
INPUT FILTERS
I2C-BUS CONTROLLER
SUBADDRESS COUNTER
SA0
SDAACK
VDD
A0
A1
A2
013aaa044
Fig 1.
Block diagram of PCA85133
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PCA85133
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
D7 S67 S12 D6 D8 D2
013aaa045
96
+y
0
+x 0
PCA85133
110 97 40 OSC FF A0 A1 A2 SA0 SYNC BP2 BP0 S0 CLK SDA SCL VDD VSS 1
S79 BP3 BP1
D9 S68
41
SDAACK
Viewed from active side. For mechanical details, see Figure 23.
Fig 2.
Pin configuration of PCA85133
6.2 Pin description
Table 3. Symbol SDAACK SDA SCL CLK VDD SYNC OSC FF A0, A1 and A2 SA0 VSS[1] VLCD BP2, BP0, BP3 and BP1 S0 to S79 D1 to D9
[1]
Pin description overview Pin 1 to 3 4 to 6 7 to 9 10 11 to 13 14 15 16 17 to 19 20 21 to 23 24 to 26 27, 28, 109 and 110 29 to 108 Description I2C-bus acknowledge output I2C-bus serial data input I2C-bus serial clock input clock input and output supply voltage cascade synchronization input and output oscillator select frame frequency select subaddress input I2C-bus slave address input ground supply voltage LCD supply voltage LCD backplane output LCD segment output dummy pins
The substrate (rear side of the die) is wired to VSS but should not be electrically contacted.
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PCA85133
Universal LCD driver for low multiplex rates
7. Functional description
The PCA85133 is a versatile peripheral device, designed to interface between any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 80 segments. The display configurations possible with the PCA85133 depend on the required number of active backplane outputs. A selection of display configurations is shown in Table 4. All of the display configurations can be implemented in a typical system as shown in Figure 3.
Table 4. Number of Backplanes 4 3 2 1 Elements 320 240 160 80 Possible display configurations 7-segment alphanumeric Digits 40 30 20 10 Indicator symbols 40 30 20 10 14-segment alphanumeric Characters 20 16 10 5 Indicator symbols 40 16 20 10 320 (4 x 80) 240 (3 x 80) 160 (2 x 80) 80 (1 x 80) Dot matrix
VDD
R
tr 2Cb
SDAACK VDD SDA VLCD
80 segment drives
LCD PANEL
HOST MICROPROCESSOR/ MICROCONTROLLER
SCL OSC FF A0 A1 A2 SA0 VSS
PCA85133
4 backplanes
(up to 320 elements)
VSS
013aaa046
Fig 3.
Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCA85133. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (VDD, VSS, and VLCD) and the LCD panel selected for the application.
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PCA85133
Universal LCD driver for low multiplex rates
7.1 Power-on reset
At power-on the PCA85133 resets to the following starting conditions:
* * * * * * *
All backplane and segment outputs are set to VLCD The selected drive mode is 1:4 multiplex with 13 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) The display is disabled
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors between VLCD and VSS. The center resistor is bypassed by switch if the 1 bias voltage level for the 1:2 multiplex configuration is selected. 2
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command (see Table 10) from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 5.
Table 5. LCD drive mode static 1:2 multiplex 1:2 multiplex 1:3 multiplex 1:4 multiplex Biasing characteristics LCD bias Backplanes Levels configuration 1 2 2 3 4 2 3 4 4 4 static
1 2 1 3 1 3 1 3
Number of:
V off ( RMS ) -------------------------V LCD
0 0.354 0.333 0.333 0.333
V on ( RMS ) V on ( RMS ) ------------------------ D = -------------------------V off ( RMS ) V LCD
1 0.791 0.745 0.638 0.577 2.236 2.236 1.915 1.732
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller.
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PCA85133
Universal LCD driver for low multiplex rates
1 Bias is calculated by ------------ , where the values for a are 1+a
a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1 V on ( RMS ) = a 2 + 2a + n ----------------------------2 n x (1 + a) (1)
V LCD
where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 3 for 1:3 multiplex n = 4 for 1:4 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = a 2 - 2a + n ----------------------------2 n x (1 + a) (2)
V LCD
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
V on ( RMS ) D = ----------------------- = V off ( RMS )
(a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1)
2
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1 1 2 bias 2 bias
is
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
21 is ---------- = 1.528 . 3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows:
* 1:3 multiplex (12 bias): V LCD = 6 x V off ( RMS ) = 2.449V off ( RMS )
) --------------------* 1:4 multiplex (12 bias): V LCD = ( 4 x 3 - = 2.309V off ( RMS )
3
These compare with V LCD = 3V off ( RMS ) when 13 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage.
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Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 4.
Tfr
VLCD BP0 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD
LCD segments
state 1 (on)
state 2 (off)
state 1
0V
-VLCD
VLCD
state 2
0V
-VLCD (b) Resultant waveforms at LCD segment.
013aaa207
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) - VBP0(t). Voff(RMS) = 0 V.
Fig 4.
Static drive mode waveforms
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PCA85133
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA85133 allows the use of 12 bias or 13 bias in this mode as shown in Figure 5 and Figure 6.
Tfr VLCD BP0 VLCD/2 VSS state 1 VLCD BP1 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V
-VLCD/2 -VLCD
LCD segments
state 2
VLCD VLCD/2 state 2 0V
-VLCD/2 -VLCD
(b) Resultant waveforms at LCD segment.
013aaa208
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.354VLCD.
Fig 5.
Waveforms for the 1:2 multiplex drive mode with 12 bias
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PCA85133
Universal LCD driver for low multiplex rates
Tfr
BP0
VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3
LCD segments
state 1 state 2
BP1
Sn
Sn+1
state 1
0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3
state 2
0V -VLCD/3 -2VLCD/3 -VLCD (b) Resultant waveforms at LCD segment.
013aaa209
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD.
Fig 6.
Waveforms for the 1:2 multiplex drive mode with 13 bias
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PCA85133
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 7.
Tfr VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3
-2VLCD/3 -VLCD
LCD segments
BP0
state 1 state 2
BP1
BP2
Sn
Sn+1
Sn+2
(b) Resultant waveforms at LCD segment.
013aaa210
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD.
Fig 7.
Waveforms for the 1:3 multiplex drive mode with 13 bias
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PCA85133
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 8.
Tfr VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD state 1 state 2 LCD segments
BP0
BP1
BP2
BP3
Sn
Sn+1
Sn+2
Sn+3
state 1
state 2
(b) Resultant waveforms at LCD segment.
013aaa211
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD.
Fig 8.
Waveforms for the 1:4 multiplex drive mode with 13 bias
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PCA85133
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCA85133 are timed by a frequency fclk which either is derived from the built-in oscillator frequency fosc: f osc f clk = --------64 or equals an external clock frequency fclk(ext): f clk = f clk ( ext ) (5) (4)
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output from pin CLK provides the clock signal for any cascaded PCA85133 in the system. After power-on, pin SDA must be HIGH to guarantee that the clock starts.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the external clock input. Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing and frame frequency
The clock frequency fclk determines the LCD frame frequency ffr and is calculated as follows:
f clk f fr = --------24
(6)
The internal clock frequency fclk can be selected using pin FF. As a result 2 frame frequencies are available: 82 Hz or 110 Hz (typical), see Table 6.
Table 6. VDD VSS LCD frame frequencies Typical clock frequency (Hz) 1970 2640 LCD frame frequency (Hz) 82 110
Pin FF tied to
The timing of the PCA85133 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between all the PCA85133 in the system.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display register, the LCD segment outputs and one column of the display RAM.
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PCA85133
Universal LCD driver for low multiplex rates
7.8 Segment outputs
The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. When less than 80 segment outputs are required the unused segment outputs must be left open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated in accordance with the selected LCD drive mode.
* In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left open-circuit.
* In 1:3 multiplex drive mode: BP3 carries the same signal as BP1; therefore, these two
adjacent outputs can be tied together to give enhanced drive capabilities.
* In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
* In static drive mode: The same signal is carried by all four backplane outputs; and
they can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 80 x 4 bit RAM which stores LCD data. A logic 1 in the RAM bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map Figure 9 shows rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively.
columns display RAM addresses/segment outputs (S) rows 0 display RAM rows/ backplane outputs 1 (BP) 2 3
013aaa214
0
1
2
3
4
75
76
77
78
79
The display RAM bitmap shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 9.
Display RAM bitmap
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drive mode
LCD segments
LCD backplanes
display RAM filling order columns display RAM address/segment outputs (s) byte1
transmitted display byte
Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6
e d f
a b g c
Sn+1 Sn Sn+7 DP
BP0
rows display RAM 0 rows/backplane 1 outputs (BP) 2 3
n c x x x
n+1 b x x x
n+2 a x x x
n+3 f x x x
n+4 g x x x
n+5 e x x x
n+6 d x x x
n+7 DP x x x MSB cba f LSB g e d DP
BP0 Sn 1:2 Sn+1
f g a b
columns display RAM address/segment outputs (s) byte1 byte2 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n a b x x n+1 f g x x n+2 e c x x n+3 d DP x x MSB ab f LSB g e c d DP
multiplex Sn+2 Sn+3
e d c
BP1 DP
Sn+1 1:3 Sn+2
f
a b g
BP0 Sn n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2c 3x
columns display RAM address/segment outputs (s) byte1 byte2 byte3 n+1 a d g x n+2 f e x x MSB b DP c a d g f LSB
Universal LCD driver for low multiplex rates
multiplex
e d c
BP1 DP
BP2
e
Sn 1:4
f
a b g
columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 BP0 BP2 n rows display RAM 0 a rows/backplane 1c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB egd
multiplex
e c d
PCA85133
BP1 DP
Sn+1
001aaj646
x = data bit unchanged
Fig 10. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
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PCA85133
Universal LCD driver for low multiplex rates
When display data is transmitted to the PCA85133, the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment display showing all drive modes is given in Figure 10; the RAM filling organization depicted applies equally to other LCD types. The following applies to Figure 10:
* In static drive mode the eight transmitted data bits are placed into row 0 of eight
successive 4-bit RAM words.
* In 1:2 multiplex mode the eight transmitted data bits are placed in pairs into
row 0 and 1 of four successive 4-bit RAM words.
* In 1:3 multiplex mode the eight bits are placed in triples into row 0, 1 and 2 of three
successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address, but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted.
* In the 1:4 multiplex mode the eight transmitted data bits are placed in quadruples into
row 0, 1, 2, and 3 of two successive 4-bit RAM words.
7.11 Data pointer
The addressing mechanism for the display RAM is realized using a data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command. Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 10. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode:
* * * *
In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses.
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7.12 Subaddress counter
The storage of display data is conditioned by the content of the subaddress counter. Storage is allowed only when the content of the subaddress counter match with the hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined by the device-select command (see Table 12). If the content of the subaddress counter and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA85133 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 27th display data byte transmitted in 1:3 multiplex mode). The hardware subaddress must not be changed whilst the device is being accessed on the I2C-bus interface.
7.13 Output bank selector
The output bank selector selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence.
* In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, row 2, and then row 3
* In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially * In 1:2 multiplex mode, rows 0 and 1 are selected * In static mode, row 0 is selected
The PCA85133 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled.
7.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The input bank selector functions independently to the output bank selector.
7.15 Blinking
The display blink capabilities of the PCA85133 are very versatile. The whole display can blink at frequencies selected by the blink-select command (see Table 14). The blink frequencies are fractions of the clock frequency. The ratios between the clock and blink frequencies depend on the blink mode selected (see Table 7).
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Universal LCD driver for low multiplex rates
Blink frequencies Operating mode ratio f clk --------768 f clk ----------1536 f clk ----------3072 Blink frequency with respect to fclk (typical) fclk = 1.970 kHz fclk = 2.640 kHz blinking off 3.5 Hz Hz blinking off 2.5 Unit
Table 7.
Blink mode off 1
2
1.3
1.7
Hz
3
0.6
0.9
Hz
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can blink by selectively changing the display RAM data at fixed time intervals. If the entire display can blink at a frequency other then the typical blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 10).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting pin SDAACK to pin SDA on the PCA85133, the SDA line becomes fully I2C-bus compatible. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be significant, possibly a voltage divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a consequence it may be possible that the acknowledge generated by the PCA85133 can't be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle is required, it is therefore necessary to minimize the track resistance from the SDAACK pin to the system SDA line to guarantee a valid LOW level. By separating the acknowledge output from the serial data line (having the SDAACK open circuit) design efforts to generate a valid acknowledge level can be avoided. However, in that case the I2C-bus master has to be set up in such a way that it ignores the acknowledge cycle.2 The following definition assumes SDA and SDAACK are connected and refers to the pair as SDA.
2.
For further information, please consider the NXP application note: Ref. 1 "AN10170".
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Universal LCD driver for low multiplex rates
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 11).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 11. Bit transfer
7.16.1.1
START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 12.
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 12. Definition of START and STOP conditions
7.16.2 System configuration
A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 13.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
Fig 13. System configuration
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Universal LCD driver for low multiplex rates
7.16.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.
* A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
* A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
* The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).
* A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 14.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 14. Acknowledgement on the I2C-bus
7.16.4 I2C-bus controller
The PCA85133 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCA85133 are the acknowledge signals from the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data, and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1, and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress.
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7.16.5 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
7.16.6 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA85133. The least significant bit of the slave address is bit R/W. The PCA85133 is a write-only device. It will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two types of PCA85133 can be distinguished on the same I2C-bus which allows:
* Up to 16 PCA85133 on the same I2C-bus for very large LCD applications * The use of two types of LCD multiplex drive modes on the same I2C-bus
The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the available PCA85133 slave addresses. All PCA85133 with the same SA0 level acknowledge in parallel to the slave address. All PCA85133 with the alternative SA0 level ignore the whole I2C-bus transfer.
R/W = 0 slave address S CR S011100A0A OS 0 control byte RAM/command byte M AS B L SP B
EXAMPLES a) transmit two bytes of RAM data S S011100A0A01 0 A RAM DATA A RAM DATA AP
b) transmit two command bytes S S011100A0A10 0 A COMMAND A00 A COMMAND AP
c) transmit one command byte and two RAM date bytes S S011100A0A10 0 A COMMAND A01 A RAM DATA A RAM DATA AP
mgl752
Fig 15. I2C-bus protocol
After acknowledgement, the control byte is sent, defining if the next byte is a RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data (see Figure 16 and Table 8). In this way it is possible to configure the device and then fill the display RAM with little overhead.
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Universal LCD driver for low multiplex rates
MSB 7
6
5
4
3
2
1
LSB 0
CO RS
not relevant
mgl753
Fig 16. Control byte format Table 8. Bit 7 Control byte description Symbol CO 0 1 6 RS 0 1 5 to 0 Value Description continue bit last control byte control bytes continue register selection command register data register not relevant
The command bytes and control bytes are also acknowledged by all addressed PCA85133 connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCA85133. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be asserted to RESTART an I2C-bus access.
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7.17 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCA85133 are defined in Table 9.
Table 9. Command Bit mode-set load-data-pointer device-select bank-select blink-select Table 10. Bit 7 to 4 3 Definition of commands Operation code 7 1 0 1 1 1 6 1 P6 1 1 1 5 0 P5 1 1 1 4 0 P4 0 1 1 3 E P3 0 1 0 2 B P2 A2 0 A 1 M1 P1 A1 I BF1 0 M0 P0 A0 O BF0 Table 10 Table 11 Table 12 Table 13 Table 14 Reference
Mode-set command bit description Symbol E 0 1 Value 1100 Description fixed value display status[1] disabled (blank) enabled LCD bias configuration 0 1
1 3 1 2
2
B
bias bias
1 to 0
M[1:0] 01 10 11 00
LCD drive mode selection static; 1 backplane 1:2 multiplex; 2 backplanes 1:3 multiplex; 3 backplanes 1:4 multiplex; 4 backplanes
[1]
The possibility to disable the display allows implementation of blinking under external control.
Table 11. Load-data-pointer command bit description See Section 7.11. Bit 7 6 to 0 Symbol P[6:0] Value 0 0000000 to 1001111 Description fixed value 7-bit binary value of 0 to 79, transferred to the data pointer to define one of 80 display RAM addresses
Table 12. Device-select command bit description See Section 7.12. Bit 7 to 3 2 to 0 Symbol A[2:0] Value 11100 000 to 111 Description fixed value 3-bit binary value of 0 to 7, transferred to the subaddress counter to define one of 8 hardware subaddresses
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Table 13. Bank-select command bit description[1] See Section 7.10, Section 7.11, Section 7.12, Section 7.13 and Section 7.14. Bit 7 to 2 1 Symbol I 0 1 0 O 0 1
[1]
Value 111110
Description Static fixed value input bank selection: storage of arriving display data RAM bit 0 RAM bit 2 RAM bit 0 RAM bit 2 RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 1:2 multiplex
output bank selection: retrieval of LCD display data
The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.
Table 14. Blink-select command bit description See Section 7.15. Bit 7 to 3 2 Symbol A 0 1 1 to 0 BF[1:0] 00 01 10 11
[1] [2]
Value 11110
Description fixed value blink mode selection[1] normal blinking blinking by alternating display RAM banks blink frequency selection[2] off 1 2 3
Normal blinking can only be selected in multiplex drive mode 1:3 or 1:4. For the blink frequencies, see Table 7.
7.18 Display controller
The display controller executes the commands identified by the command decoder. It contains the status registers and coordinates their effects. The display controller also loads the display data into the display RAM as required by the storage order.
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8. Internal circuitry
VDD SA0, CLK, SYNC, OSC, FF, A0, A1, A2 VSS VSS SCL, SDA, SDAACK VDD
VSS VLCD BP0, BP1, BP2, BP3, S0 to S79 VSS VSS
001aaj580
VLCD
Fig 17. Device protection diagram
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9. Limiting values
CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD VLCD Vi(n) Vo(n) II IO IDD ISS IDD(LCD) Ptot P/out VESD Ilu Tstg
[1] [2] [3] [4] [5]
Conditions
Min -0.5 -0.5
Max +6.5 +9.0 +6.5 +9.0 +10 +10 +50 +50 +50 400 100 4500 250 200 +150
Unit V V V V mA mA mA mA mA mW mW V V mA C
supply voltage LCD supply voltage voltage on any input voltage on any output input current output current supply current ground supply current LCD supply current total power dissipation power dissipation per output electrostatic discharge voltage latch-up current storage temperature Human Body Model Machine Model
[2] [3] [4] [5]
VDD related inputs VLCD related outputs
-0.5 -0.5 -10 -10 -50 -50 -50 -65
Stresses above these values listed may cause permanent damage to the device. Pass level; Human Body Model (HBM) according to Ref. 5 "JESD22-A114". Pass level; Machine Model (MM), according to Ref. 6 "JESD22-A115". Pass level; latch-up testing, according to Ref. 7 "JESD78" at maximum ambient temperature (Tamb(max) = +95 C). According to the NXP store and transport requirements (see Ref. 9 "NX3-00092") the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document.
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10. Static characteristics
Table 16. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = -40 C to +95 C; unless otherwise specified. Symbol Parameter Supplies VDD VLCD VPOR IDD Logic VI VIH VIL VOH VOL IOH IOL IL CI I2C-bus Input on pins SDA and SCL VI VIH VIL CI IOL(SDA) input voltage HIGH-level input voltage LOW-level input voltage input capacitance LOW-level output current on pin SDA output voltage variation output resistance VOL = 0.4 V; VDD = 5 V
[2]
Conditions VLCD 6.5 V VLCD > 6.5 V VDD 2.5 V VDD < 2.5 V
Min 1.8 2.5 2.5 2.5 1.0
[1] [1]
Typ 1.3 16 2
Max 5.5 5.5 8.0 6.5 1.6 60 20
Unit V V V V V A A
supply voltage LCD supply voltage power-on reset voltage
IDD(LCD) LCD supply current supply current input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage
fclk(ext) = 1536 Hz fclk(ext) = 1536 Hz
-
VSS - 0.5 on pins CLK, SYNC, OSC, A0 to A2, SA0, FF on pins CLK, SYNC, OSC, A0 to A2, SA0, FF 0.7VDD VSS 0.8VDD +1 -1
[2]
VDD + 0.5 V VDD 0.3VDD 0.2VDD -1 +1 7 V V V V mA mA A pF
-
HIGH-level output current on pin CLK; VOH = 4.6 V; VDD = 5 V LOW-level output current leakage current input capacitance on pin CLK, SYNC; VOL = 0.4 V; VDD = 5 V on pins OSC, CLK, SCL, SDA, A0 to A2, SA0, FF; VI = VDD or VSS
-
VSS - 0.5 0.7VDD VSS +3 -
5.5 5.5 0.3VDD 7 -
V V V pF mA
LCD outputs VO RO on pin BPx; Cbpl = 35 nF on pin Sx; Csgm = 5 nF VLCD = 5 V on pin BPx on pin Sx
[1] [2] [3]
[3] [3]
-100 -100 -
1.5 6.0
+100 +100 10 13.5
mV mV k k
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. Not tested, design specification only. Outputs measured individually and sequentially.
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Universal LCD driver for low multiplex rates
11. Dynamic characteristics
Table 17. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = -40 C to +95 C; unless otherwise specified. Symbol Clock Internal: output pin CLK fclk ffr clock frequency frame frequency pin FF = VDD pin FF = VSS pin FF = VDD pin FF = VSS External: input pin CLK fclk(ext) tclk(H) tclk(L) external clock frequency HIGH-level clock time LOW-level clock time
[2] [1][2] [1][2]
Parameter
Conditions
Min
Typ
Max
Unit
1440 1920 60 80 800 90 90 1
1970 2640 82 110 30 -
2640 3600 110 150 5000 30
Hz Hz Hz Hz Hz s s ns s s
Synchronization: input pin SYNC tPD(SYNC_N) SYNC propagation delay tSYNC_NL tPD(drv) I2C-bus: Pin SCL fSCL tHIGH tLOW Pin SDA tSU;DAT tHD;DAT tBUF tSU;STO tHD;STA tSU;STA tr tf Cb tw(spike)
[1] [2] [3] [4]
SYNC LOW time driver propagation delay timing[3][4] SCL clock frequency HIGH period of the SCL clock LOW period of the SCL clock data set-up time data hold time bus free time between a STOP and START condition set-up time for STOP condition hold time (repeated) START condition set-up time for a repeated START condition rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line spike pulse width f clk on bus VLCD = 5 V
Outputs: pins BP0 to BP3 and S0 to S79 -
0.6 1.3 100 0 1.3 0.6 0.6 0.6 -
-
400 0.3 0.3 400 50
kHz s s ns ns s s s s s s pF ns
Pins SCL and SDA
Typical output duty cycle of 50 %.
The corresponding frame frequency is f fr = --------- . 24 All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. For I2C-bus timings see Figure 19.
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Universal LCD driver for low multiplex rates
1 / fCLK tclk(H) CLK tclk(L) 0.7 VDD 0.3 VDD
SYNC tPD(SYNC_N) tSYNC_NL
0.7 VDD 0.3 VDD
0.5 V BP0 to BP3, and S0 to S79 tPD(drv) (VDD = 5 V) 0.5 V
001aag591
Fig 18. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA tSU;STO
mga728
Fig 19. I2C-bus timing waveforms
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12. Application information
12.1 Cascaded operation
In large display configurations up to 16 PCA85133 can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable I2C-bus slave address (SA0).
Table 18. Cluster 1 Addressing cascaded PCA85133 Bit SA0 0 Pin A2 0 0 0 0 1 1 1 1 2 1 0 0 0 0 1 1 1 1 Pin A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Device 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
When cascaded PCA85133 are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCA85133 of the cascade contribute additional segment outputs, but their backplane outputs are left open-circuit (see Figure 20).
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PCA85133
Universal LCD driver for low multiplex rates
SDAACK SDA SCL SYNC CLK OSC FF A0 VLCD VDD tr 2Cb SDAACK
VDD
VLCD
80 segment drives
PCA85133
(2)
BP0 to BP3 (open-circuit) LCD PANEL
A1
A2
SA0 VSS
(up to 5120 elements)
R
VDD SDA SCL SYNC CLK OSC FF A0 A1 A2
VLCD
80 segment drives
HOST MICROPROCESSOR/ MICROCONTROLLER
PCA85133
(1)
4 backplanes
BP0 to BP3
VSS
SA0 VSS
013aaa047
(1) Is master (OSC connected to VSS). (2) Is slave (OSC connected to VDD).
Fig 20. Cascaded PCA85133 configuration
For display sizes that are not multiple of 320 elements, a mixed cascaded system can be considered containing only devices like PCA85133 and PCA85132. Depending on the application, one must take care of the software command and pin connection compatibility. Only one master but multiple slaves are allowed in a cascade. No external clock should be used; the slaves get the clock from the master. The SYNC line is provided to maintain the correct synchronization between all cascaded PCA85133. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by the definition of a multiplex drive mode when PCA85133 with different SA0 levels are cascaded). SYNC is organized as an input/output pin; The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCA85133 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCA85133 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC signal for the various drive modes of the PCA85133 are shown in Figure 21.
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Universal LCD driver for low multiplex rates
Tfr =
1 ffr
BP0
SYNC
(a) static drive mode.
BP0 (1/2 bias)
BP0 (1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0 (1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0 (1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Fig 21. Synchronization of the cascade for the various PCA85133 drive modes
The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, then the device will not be able to synchronize properly. This is particularly applicable to COG applications. Table 19 shows the limiting values for contact resistance.
Table 19. 2 3 to 5 6 to 10 11 to 16 SYNC contact resistance Maximum contact resistance 6000 2200 1200 700
Number of devices
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Universal LCD driver for low multiplex rates
13. Bare die description
13.1 General description
Table 20. Gold bump hardness Min 60 35 Max 120 80 Unit[1] HV HV Type number PCA85133U/2DA/Q1 PCA85133U/2DB/Q1
[1]
Pressure of diamond head: 10 g to 50 g.
13.2 Alignment marks
REF
S1
REF
C1
001aah849
The approximate positions of the alignment marks are shown in Figure 23.
Fig 22. Alignment marks of PCA85133 Table 21. Alignment mark locations All x/y coordinates represent the position of the REF point (see Figure 22) with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol S1 C1 Size (m) 81 x 81 81 x 81 X (m) -1916.1 1855.8 Y (m) 45 45
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Universal LCD driver for low multiplex rates
13.3 Bump locations
Table 22. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol Bump X (m) -968.67 -914.67 -712.17 -658.17 -604.17 -433.17 -379.17 -325.17 -173.52 -61.47 -7.47 46.53 149.58 262.08 345.78 429.48 513.18 596.88 680.58 765.63 819.63 873.63 979.83 1033.83 1087.83 1176.03 1230.03 1284.03 1338.03 1392.03 1446.03 1500.03 1554.03 1608.03 1662.03 1716.03 1770.03 Y (m)
[1]
Description I2C-bus acknowledge output
SDAACK 1 SDAACK 2 SDAACK 3 SDA SDA SDA SCL SCL SCL CLK VDD VDD VDD SYNC OSC FF A0 A1 A2 SA0 VSS VSS VSS VLCD VLCD VLCD BP2 BP0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
PCA85133_1
-1022.67 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5 -436.5
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
[1]
I2C-bus serial data input
I2C-bus serial clock input
clock input/output supply voltage
cascade synchronization input/output oscillator select frame frequency select subaddress input
I2C-bus slave address input; bit 0 ground supply voltage
LCD supply voltage
LCD backplane output LCD segment output
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Universal LCD driver for low multiplex rates
Table 22. Bump locations ...continued All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48
PCA85133_1
Bump 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
X (m) 1824.03 1878.03 1423.53 1369.53 1315.53 1261.53 1207.53 1153.53 1099.53 1045.53 991.53 937.53 883.53 829.53 714.06 660.06 606.06 552.06 498.06 444.06 390.06 336.06 282.06 228.06 112.59 58.59 4.59 -49.41 -103.41 -157.41 -211.41 -265.41 -319.41 -373.41 -427.41 -481.41 -596.88 -650.88 -704.88
Y (m) -436.5 -436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5 436.5
Description LCD segment output
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 -- 23 October 2009
35 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
Table 22. Bump locations ...continued All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 BP3 BP1 D1 D2 D3 D4 D5 D6
PCA85133_1
Bump 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 -
X (m) -758.88 -812.88 -866.88 -920.88 -974.88
Y (m) 436.5 436.5 436.5 436.5 436.5
Description LCD segment output
-1028.88 436.5 -1082.88 436.5 -1136.88 436.5 -1252.35 436.5 -1306.35 436.5 -1360.35 436.5 -1414.35 436.5 -1468.35 436.5 -1522.35 436.5 -1576.35 436.5 -1630.35 436.5 -1684.35 436.5 -1738.35 436.5 -1792.35 436.5 -1876.05 -436.5 -1822.05 -436.5 -1768.05 -436.5 -1714.05 -436.5 -1660.05 -436.5 -1606.05 -436.5 -1552.05 -436.5 -1498.05 -436.5 -1444.05 -436.5 -1390.05 -436.5 -1336.05 -436.5 -1282.05 -436.5 -1228.05 -436.5 -1174.05 -436.5 1932.03 1909.53 1801.53 1693.53 1585.53 1477.53 -436.5 436.5 436.5 436.5 436.5 436.5
(c) NXP B.V. 2009. All rights reserved.
LCD backplane output
[2]
dummy pad
Product data sheet
Rev. 1 -- 23 October 2009
36 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
Table 22. Bump locations ...continued All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 23. Symbol D7 D8 D9
[1] [2]
Bump -
X (m) -1953
Y (m) 436.5
Description dummy pad
-1846.35 436.5 -1930.05 -436.5
For most applications SDA and SDAACK are shorted together; see Section 7.16. The dummy pads are connected to VSS but are not tested.
PCA85133_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 -- 23 October 2009
37 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
14. Bare die outline
Bare die; 110 bumps; 4.16 x 1.07 x 0.40 mm PCA85133
D 96 +y +x 0 E 41
X
0
PC85133-1
40
97
110 1 Y
A b e e1 A2 A1
L
detail Y
detail X
0 Dimensions Unit mm A(1) A1(1) A2(1) b(1) D E e(1) e1(1)
1 scale L(1)
2 mm
max 0.018 nom 0.40 0.015 min 0.012
0.388 0.385 0.0338 4.156 1.069 0.054 0.2026 0.090 0.382
PCA85133_do
Note 1. Dimension not drawn to scale. Outline version PCA85133 References IEC --JEDEC --JEITA --European projection
Issue date 09-08-18 09-09-24
Fig 23. Bare die outline of PCA85133
PCA85133_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 -- 23 October 2009
38 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards.
16. Packing information
16.1 Tray information for PCA85133
A C
1.1 1.2 1.3
2.1 2.2
3.1
x.1 D
F
1.y
B
y E x
001aai624
Fig 24. Tray details for PCA85133
PCA85133_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 -- 23 October 2009
39 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
Table 23. Tray dimensions of PCA85133 tray See Figure 24. Symbol A B C D E F N M Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets, x direction number of pockets, y direction Value 6.3 mm 3 mm 4.26 mm 1.17 mm 50.8 mm 50.8 mm 7 15
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray (see Figure 25). Refer to the bump location diagram (see Figure 23) for the orientation and position of the type name on the die surface.
marking code
001aaj643
Fig 25. Tray alignment for PCA85133 tray
PCA85133_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 -- 23 October 2009
40 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
17. Abbreviations
Table 24. Acronym CMOS COG DC HBM I2C IC ITO LCD MM RAM RC RMS Abbreviations Description Complementary Metal-Oxide Semiconductor Chip-On-Glass Direct Current Human Body Model Inter-Integrated Circuit Integrated Circuit Indium Tin Oxide Liquid Crystal Display Machine Model Random Access Memory Resistance-Capacitance Root Mean Square
18. References
[1] [2] [3] [4] [5] [6] [7] [8] [9] AN10170 -- Design guidelines for COG modules with NXP monochrome LCD drivers AN10706 -- Handling bare die IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 -- Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD78 -- IC Latch-Up Test JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices NX3-00092 -- NXP store and transport requirements
[10] UM10204 -- I2C-bus specification and user manual
PCA85133_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 -- 23 October 2009
41 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
19. Revision history
Table 25. Revision history Release date 20091023 Data sheet status Product data sheet Change notice Supersedes Document ID PCA85133_1
PCA85133_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 -- 23 October 2009
42 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA85133_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 -- 23 October 2009
43 of 44
NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
22. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 6 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . . 8 7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 8 7.4.2 1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . . 9 7.4.3 1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 11 7.4.4 1:4 Multiplex drive mode . . . . . . . . . . . . . . . . . 12 7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5.1 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.6 Timing and frame frequency . . . . . . . . . . . . . . 13 7.7 Display register . . . . . . . . . . . . . . . . . . . . . . . . 13 7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 7.10 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.11 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.12 Subaddress counter . . . . . . . . . . . . . . . . . . . . 17 7.13 Output bank selector. . . . . . . . . . . . . . . . . . . . 17 7.14 Input bank selector . . . . . . . . . . . . . . . . . . . . . 17 7.15 Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.16 Characteristics of the I2C-bus . . . . . . . . . . . . . 18 7.16.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.16.1.1 START and STOP conditions . . . . . . . . . . . . . 19 7.16.2 System configuration . . . . . . . . . . . . . . . . . . . 19 7.16.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.4 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 20 7.16.5 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.6 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 7.17 Command decoder . . . . . . . . . . . . . . . . . . . . . 23 7.18 Display controller . . . . . . . . . . . . . . . . . . . . . . 24 8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 27 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 28 12 Application information. . . . . . . . . . . . . . . . . . 30 12.1 Cascaded operation . . . . . . . . . . . . . . . . . . . . 30 13 13.1 13.2 13.3 14 15 16 16.1 17 18 19 20 20.1 20.2 20.3 20.4 21 22 Bare die description . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Alignment marks . . . . . . . . . . . . . . . . . . . . . . Bump locations. . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Tray information for PCA85133 . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 33 34 38 39 39 39 41 41 42 43 43 43 43 43 43 44
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 October 2009 Document identifier: PCA85133_1

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