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Sitronix
1. INTRODUCTION
ST7585
66 x 102 Dot Matrix LCD Controller/Driver
ST7585 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102-segment and 65-common with 1-icon-common driver circuits. This chip is connected directly to a microprocessor which accepts 3-line or 4-line serial peripheral interface (SPI) or 8-bit parallel interface. Display data stores in an on-chip display data RAM (DDRAM) of 66 x 102 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Single-chip LCD Controller & Driver Driver Output Circuits 102-segment / 65-common+1-icon-common (1/66 duty) On-chip Display Data RAM Capacity: 66X102= 6,732 bits Low Power Consumption Analog Circuit Voltage booster (X5) Voltage regulator generates LCD operating voltage (Temperature Gradient: -0.05%/C) Electronic contrast control (32 steps) Voltage follower generates LCD bias voltages (1/7 and 1/9 bias) Wide Supply Voltage Range VDD1 - VSS1 : 1.8V ~ 3.3V (covers 1.7V~3.4V) VDD2 - VSS2 : 2.7V ~ 3.3V (covers 2.6V~3.4V)
Microprocessor Interface 8-bit parallel bi-directional interface for 6800-series or 8080-series MPU 3-line & 4-line SPI (serial peripheral interface) are available (write only) Compatible with I C interface
2
Recommend Display Supply Voltage Vop: 8.5V ~ 9.5V (1/9 bias)
External RESB (reset) Pin Built-in Oscillation Circuit Oscillator requires no external component
LCD Module Size: 1.4" (up to 1.8") Temperature Range: -30C ~ +85C
Built-in OTP (One-Time Programmable) Function
ST7585 ST7585i
6800 , 8080 , 4-Line , 3-Line interface I2C interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
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3. ST7585 PAD ARRANGEMENT
Chip Size: 4720 X 650 Chip Thickness: 300 PAD No. 5~11 1~4, 12~78 79~248 PAD No. 5~11 1~4, 12~78 79~248 Unit: um Bump Height: 15 Bump Size 35 X 57 45 X 57 15 X 137.5 Bump Pitch (min) 50 60 27
* Refer "PAD CENTER COORDINATES" section for ITO layout.
Fig 1.
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4. PAD CENTER COORDINATES
66 Duty (TMX=TMY=0)
PAD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Name VPP VPP VPP XEN VDD1 MODE TA BR PS2 PS1 PS0 TMX TMX TMY TMY Reserved Reserved Reserved Reserved Reserved Reserved Reserved VSS1 VSS1 VSS2 VSS2 VSS2 VDD1 VDD1 VDD2 VDD2 VDD2 RESB CSB RWR ERD A0 D[7] D[6] D[5] D[4] X -2298.50 -2238.50 -2178.50 -2118.50 -2053.50 -2003.50 -1953.50 -1903.50 -1853.50 -1803.50 -1753.50 -1698.50 -1638.50 -1578.50 -1518.50 -1458.50 -1398.50 -1338.50 -1278.50 -1218.50 -1158.50 -1098.50 -1034.50 -966.50 -897.50 -837.50 -777.50 -717.50 -657.50 -597.50 -537.50 -477.50 -417.50 -357.50 -297.50 -237.50 -177.50 -117.50 -57.50 2.50 62.50 Y -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 PAD# 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Name D[3] D[2] D[1] D[0] OSC VDD1 Reserved Reserved Reserved Reserved VSS1 VSS1 VSS2 VSS2 VSS2 VMO VGO VGO VGS VGI VGI VGI VGI V0I V0I V0I V0I V0S V0O V0O XV0O XV0O XV0S XV0I XV0I XV0I XV0I Reserved COMS2 COM[64] COM[63] X 122.50 182.50 242.50 302.50 362.50 426.50 494.50 558.50 618.50 678.50 738.50 798.50 858.50 918.50 978.50 1038.50 1098.50 1158.50 1218.50 1278.50 1338.50 1398.50 1458.50 1518.50 1578.50 1638.50 1698.50 1758.50 1818.50 1878.50 1938.50 1998.50 2058.50 2118.50 2178.50 2238.50 2298.50 2305.50 2278.50 2251.50 2224.50 Y -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 -258.50 217.75 217.75 217.75 217.75
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PAD# 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Name COM[62] COM[61] COM[60] COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] COM[35] COM[34] COM[33] SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] X 2197.50 2170.50 2143.50 2116.50 2089.50 2062.50 2035.50 2008.50 1981.50 1954.50 1927.50 1900.50 1873.50 1846.50 1819.50 1792.50 1765.50 1738.50 1711.50 1684.50 1657.50 1630.50 1603.50 1576.50 1549.50 1522.50 1495.50 1468.50 1441.50 1414.50 1363.50 1336.50 1309.50 1282.50 1255.50 1228.50 1201.50 1174.50 1147.50 1120.50 1093.50 1066.50 1039.50 1012.50 Y 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 PAD# 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 Name SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] X 985.50 958.50 931.50 904.50 877.50 850.50 823.50 796.50 769.50 742.50 715.50 688.50 661.50 634.50 607.50 580.50 553.50 526.50 499.50 472.50 445.50 418.50 391.50 364.50 337.50 310.50 283.50 256.50 229.50 202.50 175.50 148.50 121.50 94.50 67.50 40.50 13.50 -13.50 -40.50 -67.50 -94.50 -121.50 -148.50 -175.50 Y 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75
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PAD# 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 Name SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] X -202.50 -229.50 -256.50 -283.50 -310.50 -337.50 -364.50 -391.50 -418.50 -445.50 -472.50 -499.50 -526.50 -553.50 -580.50 -607.50 -634.50 -661.50 -688.50 -715.50 -742.50 -769.50 -796.50 -823.50 -850.50 -877.50 -904.50 -931.50 -958.50 -985.50 -1012.50 -1039.50 -1066.50 -1093.50 -1120.50 -1147.50 -1174.50 -1201.50 -1228.50 -1255.50 -1282.50 -1309.50 -1336.50 Y 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 Note: PAD# 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 Name SEG[101] COMS1 COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] COM[32] X -1363.50 -1414.50 -1441.50 -1468.50 -1495.50 -1522.50 -1549.50 -1576.50 -1603.50 -1630.50 -1657.50 -1684.50 -1711.50 -1738.50 -1765.50 -1792.50 -1819.50 -1846.50 -1873.50 -1900.50 -1927.50 -1954.50 -1981.50 -2008.50 -2035.50 -2062.50 -2089.50 -2116.50 -2143.50 -2170.50 -2197.50 -2224.50 -2251.50 -2278.50 -2305.50 Y 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75 217.75
l l l
Tolerance: +/- 0.02um Please refer to "Fig 12" (Page 18) for detailed output map for TMX=1 or TMY=1. Please don't use the "Reserved" pads.
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5. BLOCK DIAGRAM
Fig 2.
Block Diagram
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6. PINNING DESCRIPTIONS
LCD Driver Output Pins
Pin Name Type LCD segment driver outputs. The display data and the frame control the output voltage. Display data SEG0 to SEG101 O H H L L Frame + + Segment driver output voltage Normal display VG VSS VSS VG VSS Reverse display VSS VG VG VSS VSS 102 Description No. of Pins
Display OFF, Power Save LCD common driver outputs.
The internal scanning signal and the frame control the output voltage. Scan signal COM0 to COM64 O H H L L Frame + + Common driver output voltage Normal display XV0 V0 VM VM VSS 2 Reverse display 65
Display OFF, Power Save COMS1, COMS2 (COMS) TMX O
LCD common driver outputs for icons. These two pins are identical. Choose one of them if using icon. When icon is not used, left these pins open. Select SEG output direction. Refer to "Fig 12". TMX="L" : Normal direction (SEG0 ~ SEG101). TMX="H" : Reverse direction (SEG101 ~ SEG0). Select COM output direction. Refer to "Fig 12".
I
2
TMY
I
TMY="L" : Normal direction (COM0 ~ COM64). TMY="H" : Reverse direction (COM64 ~ COM0).
2
Clock System Input
Pin Name OSC Type I OSC="H" : Use built-in oscillator. Description No. of Pins 1
Power Supply Pins
Pin Name VSS1 VSS2 VDD1 VDD2 Type Power Power Power Power Description Digital ground. Connect to VSS2 by FPC. For pins that are set to be "L", connect them to this power (use VSS1 for "L"). Analog ground. Connect to VSS1 by FPC. Digital power. If VDD1=VDD2, connect to VDD2 by FPC. For pins that are set to be "H", connect them to this power (use VDD1 for "H"). Analog power. If VDD1=VDD2, connect to VDD1 by FPC. No. of Pins 4 6 4 3
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Built-in Power System Pins
Pin Name V0O V0I V0S XV0O XV0I XV0S VGO VGI VGS BR I Power Power Power Type V0 VG > VM > VSS XV0 V0O, V0I & V0S should be separated in ITO layout. V0O, V0I & V0S should be connected together in FPC layout. LCD driving voltage for commons at positive frame. XV0O, XV0I & XV0S should be separated in ITO layout. XV0O, XV0I & XV0S should be connected together in FPC layout. LCD driving voltage for segments. VGO, VGI & VGS should be separated in ITO layout. VGO, VGI & VGS should be connected together in FPC layout. 1.8 VG < VDD2. Bias circuit configuration pin for default setting : "L"=1/7; "H"=1/9. This pin sets the default bias ratio after reset. Description LCD driving voltage for commons at negative frame. No. of Pins 2 4 1 2 4 1 2 4 1 1
Microprocessor Interface Pins
Pin Name Type Description Microprocessor interface select pins. PS2 "L" PS[2:0] I "L" "L" "L" "H" PS1 "L" "L" "H" "H" "L" PS0 "L" "H" "L" "H" "L" Selected Interface 3-Line SPI interface 4-Line SPI interface 6800-series parallel interface 8080-series parallel interface I C Interface
2
No. of Pins
3
Chip select input pin. CSB I Interface access is enabled when CSB is "L". When CSB is non-active (CSB="H"), D[7:0] pins are high impedance. CSB is not used in serial interfaces and should fix to "H" by VDD1. RESB I Reset input pin. When RESB is "L", internal initialization is executed. It determines whether the access is related to data or command. A0 I A0="H" : Indicates that D[7:0] are display data. A0="L" : Indicates that D[7:0] are control data. A0 is not used in serial interfaces and should fix to "H" by VDD1. Read/Write execution control pin. When parallel interface is selected: MPU Type 6800 series RWR I 8080 series /WR RWR R/W R/W="H": read. R/W="L": write. Write enable input pin. Signals on D[7:0] will be latched at the rising edge of /WR signal. RWR is not used in serial interfaces and should fix to "H" by VDD1. 1 Description Read/Write control input pin. 1 1 1
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Pin Name Type Description Read/Write execution control pin. When parallel interface is selected: MPU Type ERD Description Read/Write control input pin. R/W="H": When E is "H", D[7:0] are in an ERD I 6800 series E output status. R/W="L": Signals on D[7:0] are latched at the falling edge of E signal. 8080 series /RD Read enable input pin. When /RD is "L", D[7:0] are in output status. 1 No. of Pins
ERD is not used in serial interfaces and should fix to "H" by VDD1. When using 8-bit parallel interface: 6800 or 8080 mode I/O 8-bit bi-directional data bus. Connect to the data bus of 8-bit microprocessor. When CSB is non-active (CSB="H"), D[7:0] pins are high impedance. When using serial interface: 4-LINE or 3-LINE D7=SCLK : Serial clock input. I D6=SDA : Serial data input. D5=A0 : Command / Data selection (unused in 3-Line SPI; fix to H by VDD1). D4=CSB : Chip select pin. D[7:0] D[3:0] : Not used and should fix to "H" by VDD1. When using I C interface D7=SCLK : Serial clock input. D6=SDA_IN I, O
*1 2
8
: Serial data input.
*1
D[5:3] : SDA_OUT
: Outputs for acknowledge-bit of the I C protocol.
2
D[2]= Not used and should fix to "H" by VDD1. D[1:0]=SA[1:0] : Slave address bits. Must set to "H" by VDD1 or "L" by VSS1. D[6:3] must connect together (SDA).
2 *1
CSB is not used in I C interface and should fix to "H" by VDD1. Note: 1. By connecting SDA_IN and SDA_OUT externally, the SDA line becomes fully I C interface compatible. Separating acknowledge-output from serial data input is advantageous for chip-on-glass (COG) applications. In COG applications, the ITO resistance and the pull-up resistor will form a voltage divider which affects acknowledge-signal level. Larger ITO resistance will raise the acknowledge-signal level and system cannot recognize this level as a valid logic "0" level. By separating SDA_IN from SDA_OUT, the IC can be used in a mode which ignores the acknowledge-bit. For applications which check acknowledge-bit, it is necessary to minimize the ITO resistance of the SDA_OUT trace to guarantee a valid low level. 2. After VDD1 is turned ON, any MPU interface pins cannot be left floating.
2
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OTP Pins
Pin Name VPP XEN Type Power I Programming voltage of OTP. OTP programming control pin. This pin is pulled high internally. XEN="L", programming OPT is enabled. XEN="Floating", programming OPT is disabled. 1 Description No. of Pins 3
Test Pins
Pin Name MODE VMO TA Type Test Test Test Description Do NOT use. Reserved for testing. Must be "L". Connect to VSS1 for pull-low. Output VM for IC testing only. Do NOT use. Reserved for testing. Must be "L". Connect to VSS1 for pull-low. No. of Pins 1 1 1
Recommend ITO Resistance
Pin Name VMO, Reserved VDD1, VDD2, VSS1, VSS2, VPP V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), SDA A0, RWR, ERD, CSB, D[7:0]
*2 *1 *1
ITO Resistance Floating < 100 < 300 < 1K < 5K < 10K
PS[2:0], OSC, BR, TMX, TMY, MODE, TA, XEN RESB Note: 1.
If using I C interface mode, the resistance of SDA signal should be lower than 300 (if the system pull up resistor is 4.7K). If using 3-Line or 4-Line SPI interface with VDD1 less than 2.4V, the SDA signal resistance should be less than 500.
2
2. 3. 4. 5.
To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RESB signal (add a series resistor or increase ITO resistance). The value is different from modules. This table defines the actual ITO resistance. The actual ITO resistance should in these ranges, not the calculated ITO resistance value. The ITO tolerance should be considered. The option setting to be "H" should connect to VDD1. The option setting to be "L" should connect to VSS1.
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7. FUNCTIONS DESCRIPTION
Microprocessor Interface
Chip Select Input
CSB pin is used for chip selection. ST7585 can interface with an MPU when CSB is "L". When CSB is "H", the inputs of A0, ERD and RWR with any combination will be ignored and D[7:0] are high impedance. In 3-Line and 4-Line serial interface, the internal shift register and serial counter are reset when CSB is "H".
Parallel / Serial Interface
ST7585 has types of interface for kinds of MPU. The MPU interface is selected by PS[2:0] pins as shown in table 1.
Table 1. Parallel/Serial Interface Mode
PS2 PS1 PS0 CSB A0 ERD RWR D[7:0] "L" "L" "L" --------Refer to serial interface. "L" "L" "H" "L" "H" "L" E R/W CSB A0 D[7:0] "L" "H" "H" /RD /WR "H" "L" "L" --------Refer to serial interface. * The un-used pins are marked as "---" and should be fixed to "H" by VDD1. MPU Interface 3-Line SPI interface 4-Line SPI interface 6800-series parallel interface 8080-series parallel interface 2 I C Interface
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS0 (fix PS2=L, PS1=H) as shown in table 2. The data transfer type is determined by signals of A0, ERD and RWR as shown in table 3.
Table 2. Microprocessor Selection for Parallel Interface
PS2 "L" "L" PS1 "H" "H" PS0 "L" "H" CSB CSB A0 A0 ERD E /RD RWR R/W /WR D[7:0] D[7:0] MPU Interface 6800-series 8080-series
Table 3. Parallel Data Transfer
Description A0 E (ERD) R/W (RWR) /RD (ERD) /WR (RWR) "H" "H" "H" "L" "H" Display data read out "H" "H" "L" "H" "L" Display data write "L" "H" "H" "L" "H" Internal status read "L" "H" "L" "H" "L" Writes to internal register (instruction) NOTE: In 6800-series interface mode, fixing E (ERD) pin at high can use CSB as enable signal instead. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0 and R/W (RWR) pins as defined in 6800-series mode. Common 6800-series 8080-series
Setting Serial Interface
Interface PS[2:0] CSB, A0, ERD, RWR D[7:0] 3-Line SPI "L, L, L" SCLK, SDA, ---, CSB, ---, ---, ---, ----4-Line SPI "L, L, H" SCLK, SDA, A0, CSB, ---, ---, ---, --2 IC "H, L, L" SCLK, SDA_IN, SDA_OUT, SDA_OUT, SDA_OUT, ---, SA1, SA0 * The un-used pins are marked as "---" and should be fixed to "H" by VDD1. Note: 1. 2. The option setting to be "H" should connect to VDD1. The option setting to be "L" should connect to VSS1.
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4-Line & 3-Line Serial interface
In 4-Line and 3-Line interface, ST7585 is active when CSB is "L", and serial data (SDA) and serial clock (SCLK) inputs are enabled. When CSB is "H", ST7585 is not active, and the internal 8-bit shift register and 3-bit counter are reset. The read feature is not supported in this mode. The DDRAM column address pointer will be increased by one automatically after writing each byte of DDRAM. 4-Line Serial Interface The display data/command indication is controlled by the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0 is low. Serial data (SDA) is latched at the rising edge of serial clock (SCLK). After the 8 serial clock, the serial data will be processed as 8-bit parallel data.
th
Fig 3.
3-Line Serial Interface
4-Line SPI Access
The A0 pin is not available in this mode. Before issuing serial data, an A0 bit is required to indicate the following 8-bit signals are data or instruction. Serial data (SDA) is latched at the rising edge of serial clock (SCLK). After the 9 serial clock, the serial data will be processed as 8-bit parallel data.
th
Fig 4.
3-Line SPI Access
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I2C Interface
The I C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCLK). Both lines must be connected with a pull-up resistor which drives SDA and SCLK to high when the bus is not busy. Data transfer can be initiated only when the bus is not busy. The I C interface of ST7585 supports write access and read of acknowledge-bit. The I C interface receives and executes the commands sent via the I C Interface. It also receives RAM data and sends it to the Display RAM. BIT TRANSFER One data bit is transferred during each clock pulse. The data on SDA line must remain stable during the HIGH period of the clock pulse because changes of SDA line at this time will be interpreted as START or STOP condition. Refer to Fig 5.
2 2 2 2
Fig 5.
START AND STOP CONDITIONS
Bit transfer
Both SDA and SCLK lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of SDA, while SCLK is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCLK is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig 6.
Fig 6.
SYSTEM CONFIGURATION
Definition of START and STOP conditions
The system configuration is illustrated in Fig 7 and some word-definitions are explained below: - Transmitter: the device which sends the data to the bus. - Receiver: the device which receives the data from the bus. - Master: the device, which initiates a transfer, generates clock signals and terminates a transfer. - Slave: the device which is addressed by a master. - Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message. - Arbitration: the procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is allowed to do so and the message is not corrupted. - Synchronization: procedure to synchronize the clock signals of two or more devices.
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Fig 7.
ACKNOWLEDGEMENT
System configuration
Each byte of eight bits is followed by an acknowledge-bit. The acknowledge-bit is a HIGH signal put on SDA by the transmitter during the time when the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge-bit after the reception of each byte. The device that acknowledges must pull-down the SDA line during the acknowledge-clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). Acknowledgement on the I C Interface is illustrated in Fig 8.
2
Fig 8.
I C INTERFACE PROTOCOL
2
Acknowledgement of I C Interface
2
SA1 SA0
A0
R/W
Co
Co=1 A0
Co
Fig 9.
Co 0 1
I C Interface protocol
2
Last control byte. Only a stream of data bytes is allowed to follow. This stream may only be terminated by a STOP or RE-START condition. Another control byte will follow the data byte.
2
ST7585 supports command/data write to addressed slaves on the bus. The I C Interface protocol is illustrated in Fig 9. Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses (0111100, 0111101, 0111110 and 0111111) are reserved for ST7585. The least significant 2 bits of the slave address is set by connecting SA0 and SA1 to either logic 0 (VSS1) or logic 1 (VDD1).
2
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The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After acknowledgement, one or more command words are followed and define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, and a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data byte(s) will follow. The state of the A0 bit defines whether the following data bytes are interpreted as commands or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte either a series of display data bytes or command data bytes may follow (depending on the A0 bit setting). If the A0 bit of the last control byte is set to logic 1, these data bytes (display data bytes) will be stored in the display RAM at the address specified by the internal data pointer. The data pointer is automatically updated and the data is directed to the intended ST7585 device. If the A0 bit of the last control byte is set to logic 0, these data bytes (command data byte) will be decoded and the setting of ST7585 will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the bus master issues a STOP condition (P).
2 2
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Data Transfer
ST7585 uses bus holder and internal data bus for data transfer with MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Fig 10. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Fig 11. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signals A0 /WR D[7:0] Internal signals /WR_INT Bus Holder Column Address N D(N) N D(N+1) D(N+2) N+1 N+2 D(N+3) N+3 ... N D(N) D(N+1) D(N+2) D(N+3)
Write Operation
Fig 10.
Data Transfer : Write
Fig 11.
Data Transfer : Read
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Display Data RAM (DDRAM)
ST7585 contains a 66X102 bit static RAM that stores the display data. The display data RAM (DDRAM) store the dot data for the LCD. It is an addressable array with 102 columns by 66 rows (8-page with 8-bit, 1-page with 1-bit and 1-page with 1-bit). The X-address is directly related to the column output number. Each pixel can be selected when the page and column addresses are specified. The rows are divided into: 8 pages (page 0~7) each with 8 lines (for COM0~63), the 8
th th
page with only 1 line (for COM64) and the 9 page with only 1 line (the 65th row, COMS, for icon). The display data (D7~D0) corresponds to the LCD common-line direction (D7 at top). Those pages with 8 lines can be accessed through D[7:0] directly. When accessing those pages with fewer than 8 lines, the valid bit(s) in D[7:0] should be checked. Refer to Fig 13 for detailed illustration. The microprocessor can write to and read from (only Parallel interfaces) DDRAM by the I/O buffer. Since the LCD controller operates independently, data can be written into DDRAM at the same time as data is being displayed without causing the LCD flicker or data-conflict.
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 9 is a special RAM area for the icons and display data is only 1-bit valid (D7).
Line Address Circuit
This circuit controls each line in DDRAM to transfer 102-bit line data to the display data latch circuit. Therefore, the content in DDRAM can be transferred to the segment drivers, and display the content on the LCD module as shown in Fig 12. At the beginning of each LCD frame, the 102-bit RAM data of Line-0 are transferred to the display data latch circuit. At the next line period, the Line Address is increased by one and the 102-bit RAM data at the next line are transferred to the display data latch circuit. The 102-bit icon data are transferred at the last line period during each frame.
Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the DDRAM. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. TMX and TMY make it possible to invert the relationship between the addresses (Line Address and Column Address) and the outputs (COM/SEG). It is necessary to rewrite the display data into built-in RAM after changing TMX setting. The relation between DDRAM and outputs with different TMX or TMY setting is shown below.
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Column Address (Hex) Page Address D3 D2 D1 D0 Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 PAD No. SEG No.
TMX=H BBB B B BBB B BBB BBB B B B B B BBB BBBBB B B B B B B BBBB B B B B BBBB B B B B B B BBB B B B B B BBB B B BB B B B B B B B B B B B BB B B BBB B B B B B BBB B B B B B B B B B B B B B B B B B B B B B
Setting
TMX=L TMX=H TMY=L
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1 1
0 0
0 0
0 1
Page 8 ICON
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h Setting
TMX=L
TMY=H
COM Output Map PAD COM No. TMY=L TMY=H No. COM0 COM64 216 COM1 COM63 217 COM2 COM62 218 COM3 COM61 219 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 224 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 232 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 240 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 248 COM33 COM31 112 COM34 COM30 111 COM35 COM29 110 COM36 COM28 109 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 105 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 97 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 89 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0 81 COMS (icon) 80 or 215
66th Line always the last line
Fig 12.
Relationship between DDRAM and Outputs
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Addressing
Data is downloaded in bytes into the Display Data RAM matrix of ST7585 as shown below. The Display Data RAM has a matrix of 66 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101), Y 0 to 9 (1001) .Addresses outside these ranges are not allowed. In horizontal addressing mode the X address increments after each byte (see Fig 15). After the last X address (X = 101), X wraps around to 0 and Y increments to address the next row. After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)
Data Structure
Fig 13.
RAM format
Fig 14.
Addressing : Vertical Mode (V=1)
Fig 15.
Addressing : Horizontal Mode (V=0)
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Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. External Power Components The recommended external power components need only 2 capacitors. The detailed values of these two capacitors are determined by the panel size and loading.
Fig 16.
Power Circuit
The referential external component values are listed below (it is determined by the worse condition on 1.4" panel). C1=0.1uF~1uF (Non-Polar/6V, default 1uF) R1=47K~100K (default N.C.) C2=0.1uF~1uF (Non-Polar/16V, default 0.1uF) R2=600K~1M (default 750K) Customer applications are not necessary the same as the values listed above. The value can be determined by customer's LCD module (panel loading and ITO resistance) and application (VDD, V0, bias and etc.).
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8. RESET CIRCUIT
Setting RESB to "L" can initialize internal function. While RESB is "L", no instruction can be accepted. RESB pin must connect to the reset pin of MPU and initialization by RESB pin is essential before operating. When RESB becomes "L", the following procedures will start. Power Down Mode: PD=1 (Analog Power OFF, Oscillator OFF & COM/SEG output at VSS) Page Address: Y[3:0]=0 Column Address: X[6:0]=0 COM Scan Direction: Depends on "TMY" setting SEG Select Direction: Depends on "TMX" setting Display Control: Display OFF: D=E=0 Basic Instruction Set: H=0 Initial V0 Setting: V0[4:0]=0 Bias: Depends on "BR" setting After power-on, RAM data are undefined and the display status is "Display OFF". It's better to initialize whole DDRAM (ex: fill all 00h or write the display pattern) before turning the Display ON.
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9-1. INSTRUCTION TABLE
H=0 or 1 (H-Flag Independent) A0 0 0 1 R/W (RWR) 0 0 0 COMMAND BYTE D7 0 0 D7 D6 0 0 D6 D5 0 1 D5 D4 0 0 D4 D3 0 0 D3 D2 0 PD D2 D1 0 V D1 D0 0 H D0 No operation Power down; entry mode; Select instruction table Write data to RAM DESCRIPTION INSTRUCTION NOP Function Set Write Data H=0 (Basic Instruction) A0 0 0 0 R/W (RWR) 0 0 0 COMMAND BYTE D7 0 0 1 D6 0 1 X6 D5 0 0 X5 D4 0 0 X4 D3 1 Y3 X3 D2 D Y2 X2 D1 0 Y1 X1 D0 E Y0 X0 Sets display configuration Sets Y address of RAM 0Y9 Sets X address of RAM 0X101 DESCRIPTION
INSTRUCTION Display Control Set Y Address of RAM Set X Address of RAM
H=1
(Extended Instruction) A0 0 0 R/W (RWR) 0 0 COMMAND BYTE D7 1 0 D6 V04 0 D5 V03 1 D4 V02 1 D3 V01 0 D2 V00 T1 D1 0 T0 D0 0 Set VOP parameter to register TEN Select test mode DESCRIPTION
INSTRUCTION Set V0 Set Test Mode
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9-2. INSTRUCTION DESCRIPTION
H=0 or 1
A0 0 Flag PD
(H-Flag Independent)
R/W 0 D7 0 D6 0 D5 1 D4 0 Description PD=0: chip is active PD=1: chip is in power down mode All LCD outputs at VSS (display off), bias generator and V0 generator off, VOUT can be disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data can be written. Select addressing mode: V=0 for Horizontal Addressing; V=1 for Vertical Addressing. H=0: Basic Instruction set; H=1: Extended instruction set. Data access can be used in both instruction blocks. Refer to the instruction table. D3 0 D2 PD D1 V D0 H
Function Set
V
H
Read Data
By specify the column address and page address, the display data in DDRAM can be read by MPU (parallel interface). A0 1 R/W 1 D7 D6 D5 D4 D3 D2 D1 D0 Read Data
Write Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 1 R/W 0 D7 D6 D5 D4 D3 D2 D1 D0 Write Data
H=0
(Basic Instruction)
Display Control
This bits D and E selects the display mode. A0 0 Flag D 0 0 1 1 E 0 1 0 1 R/W 0 D7 0 D6 0 D5 0 D4 0 Description The bits D and E select the display mode. Display OFF All display segments on Normal mode Inverse video mode D3 1 D2 D D1 0 D0 E
D,E
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Set Y Address of RAM
Y [3:0] defines the Y address vector address of the display RAM. A0 0 Y3 0 0 0 0 0 0 0 0 1 1 Y2 0 0 0 0 1 1 1 1 0 0 R/W 0 Y1 0 0 1 1 0 0 1 1 0 0 D7 0 Y0 0 1 0 1 0 1 0 1 0 1 D6 1 D5 0 Content Page0 (display RAM) Page1 (display RAM) Page2 (display RAM) Page3 (display RAM) Page4 (display RAM) Page5 (display RAM) Page6 (display RAM) Page7 (display RAM) Page8 (display RAM) Page9 (display RAM) D4 0 D3 Y3 D2 Y2 D1 Y1 D0 Y0 Valid Bit D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7~ D0 D7 D7
Allowed X-Range 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101
Set X Address of RAM
The X address points to the columns. The range of X is 0...101. A0 0 X6 0 0 0 0 : 1 1 1 X5 0 0 0 0 : 1 1 1 R/W 0 X4 0 0 0 0 : 0 0 0 D7 1 X3 0 0 0 0 : 0 0 0 D6 X6 X2 0 0 0 0 : 0 1 1 D5 X5 X1 0 0 1 1 : 1 0 0 D4 X4 X0 0 1 0 1 : 1 0 1 D3 X3 D2 X2 D1 X1 D0 X0
Column address 0 1 2 3 : 99 100 101
H=1
Set V0
A0 0
(Extended Instruction)
R/W 0 D7 1 D6 V04 D5 V03 D4 V02 D3 V01 D2 V00 D1 0 (1) (2) D0 0
The operation voltage V0 can be set by software. The parameters are explained in table 4. V0 = a + Vop[4:0] * b Vop[4:0] = V0[4:0] + V0a[4:0]
Note: The maximum V0 which can be generated depends on VDD2 and the loading of the display module. Table 4 Parameters of V0 Generation Circuit SYMBOL a b VALUE 8.232 0.049 UNIT V V
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V0a[4:0] provides an offset of V0[4:0] which is used to adjust V0 voltage to cover the process tolerance on LCD modules. It can be adjusted by OTP command "V0 Increase" or "V0 Decrease".
* Typically, it is recommended to set Vop[4:0] in 8.5V ~ 9.5V (including temperature effect). So that the application can have some range (<8.5V; >9.5V) for customer to adjust LCD contrast by themselves.
V0
b
a+b
00
01
02
03
04
05
06
.....
1D
1E
1F
Vop[4:0]
Fig 17.
Setting V0 Voltage
The default V0 voltage is shown below (V0a[4:0] is not programmed into OTP by customer): V04 0 0 0 0 : 1 : 1 1 1 1 V03 0 0 0 0 : 0 : 1 1 1 1 V02 0 0 0 0 : 0 : 1 1 1 1 V01 0 0 1 1 : 0 : 1 1 1 1 V00 0 1 0 1 : 0 : 0 0 1 1 0 (default) (without adjustment) V0a[4:0] V0 (V) 8.232 8.281 8.330 8.379 : 9.016 : 9.604 9.653 9.702 9.751
Please note that: V0a [4:0] is 2's complement, so that V0a[4:0] can increase or decrease V0. If customer adjusts V0 by too many "V0 Increase" (or "V0 Decrease") instructions, the purpose to increase V0 (or decrease V0) will become: "lower V0" (or "higher V0").
Set Test Mode
A0 0 Flag T[1:0] TEN Select test mode. Enable test mode. R/W 0 D7 0 D6 0 D5 1 D4 1 Description D3 0 D2 T1 D1 T0 D0 TEN
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9-3. OTP INSTRUCTION TABLE
INSTRUCTION H=1, T=0 or 1 Set Test Mode T[1:0] = (0,0) OSC Enable T[1:0] = (0,1) V0 Increase V0 Decrease T[1:0] = (1,0) OTP Read Enable OTP Control In OTP Control Out OTP Write Enable OTP Write OTP V0 Address T[1:0] = (1,1) Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 XARD 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 Set OTP to be read mode Enable OTP Control Disable OTP Control Enable OTP Write OTP write OTP V0 address 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 V0a[4:0] +1 V0a[4:0] -1 0 0 1 0 1 1 0 OSC 0 0 OSC enable/disable A0 R/W (RWR) 0 COMMAND BYTE D7 0 D6 0 D5 1 D4 1 D3 0 D2 T1 D1 T0 D0 DESCRIPTION
(H-Flag Independent) 0 TEN Test Mode
Reserved Table Do Not Use * * * * * * * * Do not use
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9-4. OTP INSTRUCTION DESCRIPTION
Before using OTP instructions, the TEN flag in "Set Test Mode" must be enabled.
T[1:0]=(0,0)
OSC Enable
A0 0 Flag OSC OSC=1: Enable internal OSC. OSC=0: Disable internal OSC. R/W 0 D7 1 D6 0 D5 1 D4 1 Description D3 0 D2 OSC D1 0 D0 0
T[1:0]=(0,1)
V0 Increase
The V0 will be increased one step by every time executes this command. V0 OTP function include a 5 bits counter circuit V0a[4:0]. The range is (+1) to (+15) when set V0 Increase and the register of counter wil increase automatically. A0 0 R/W 0 D7 0 D6 1 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
V0 Decrease
The V0 will be decreased one step by every time executes this command. V0 OTP function include a 5 bits counter circuit V0a[4:0]. The range is (-1) to (-16) when set V0 Decrease and the register of counter will decrease automatically. A0 0 R/W 0 D7 0 D6 1 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
Software Overflow It is recommended to add a software protection when customer burning OTP to adjust V0. The software protection should prevent the operator issuing too many "V0 Increase" or "V0 Decrease" instructions. The adjustment should be in the range of "+15~+1", 0 and "-1~-16". The adjustment over this range should not trigger any more adjustment.
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T[1:0]=(1,0)
OTP Read Enable
This command sets OTP Auto-Read enable or disable. It should be set before issuing OTP Write. A0 0 Flag XARD 0: Enable OTP Auto-Read. 1: Disable OTP Auto-Read. R/W 0 D7 0 D6 1 D5 0 D4 0 Description D3 XARD D2 0 D1 0 D0 0
OTP Control In
This command should be set before "OTP Write". A0 0 R/W 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
OTP Control Out
This command should be set after finishing OTP operation. A0 0 R/W 0 D7 1 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0
OTP Write Enable
This command will enable OTP write operation. Set this command before OTP Write. A0 0 R/W 0 D7 1 D6 0 D5 0 D4 1 D3 1 D2 1 D1 1 D0 1
OTP Write
This command will burn the data into OTP. A0 0 R/W 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1
OTP V0 Address
This command points OTP function to V0 address. A0 0 R/W 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
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10. COMMAND SEQUENCE
This section introduces some reference operation flows.
Power ON flow and instruction sequence:
Operating Flow
Power ON Keep RESB=L Wait power stable, t>1ms (depends on system power) Set RESB=H Wait reset finished, t>5ms Initial: Power Circuit [Function Set] PD=0,V=0,H=1 [Bias System] [Set V0] [Function Set] PD=0,V=0,H=0 [Set V0 Range] Delay 50ms Initial: DDRAM Write DDRAM [ Display ON ] Normal Operating
Power Sequence 1. 2. 3. tV2ON: VDD2 power ON delay. => 0 tV2ON No Limitation. tRSTL: Reset Low time after VDD1 is stable. => 0 tRSTL 50 ms . tRW: Reset low pulse width. Please refer to RESB timing specification. Note: 1. 2. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. The specification listed here is to prevent abnormal display on LCD module. Be sure the power is stable and the internal reset is finished (refer to RESB timing specification).
*1
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Power OFF Flow and Sequence
By setting PD="1", ST7585 will go into power save mode. The LCD driving outputs are fixed to VSS, built-in power circuits are turned OFF and a discharge process starts.
Instruction Flow After the built-in power circuits are turned OFF and completely discharged, the power (VDD1 and VDD2) can be removed.
An alternate method is to use the RESB signal to set ST7585 into power save mode. After hardware reset, the PD flag is "1" and ST7585 is in power save mode (same as previous case).
Operating Flow After the built-in power circuits are turned OFF and completely discharged, the power (VDD1 and VDD2) can be removed.
Note: 1. 2. 3. tIPOFF: Internal Power discharge time. => 250ms (max). tV2OFF: Period between VDD1 and VDD2 OFF time. => 0 ms (min). It is NOT recommended to turn VDD1 OFF before VDD2. Without VDD1, the internal status cannot be guaranteed and internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and the liquid crystal in panel maybe polarized. 4. 5. 6. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. The timing is dependent on panel loading and the external capacitor(s). The timing in these figures is base on the condition that: LCD Panel Size = 1.4" with C1=1uF, C2=1uF. 30/51 2009/04/14
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7. 8. When turning VDD2 OFF, the falling time should follow the specification: 300ms tPFall 1sec If the power OFF flow cannot meet this specification, it is recommended to use the discharge resistors (R1 & R2 in application circuits).
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Power-Save Flow and Sequence
ENTERING THE POWER SAVE MODE The power save mode is achieved by setting PD bit to be "1". No specified instruction flow required. EXITING THE POWER SAVE MODE
INTERNAL SEQUENCE of EXIT POWER SAVE MODE After receiving "PD=0", the internal circuits (Power) will starts the following procedure.
Note: 1. 2. The power stable time is determined by LCD panel loading. The power stable time in this figure is base on: LCD Panel Size = 1.4" with C1=1uF, C2=1uF.
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OTP Burning Flow
HW Reset Delay 120ms
VPP connect to 6.7V XEN connect to VSS
Initial ST7585 ( OTP Software coding flow) Key Show image and fine tune Vop 41
+ -
42 OTP writing
Adjust Vop Offset
Remove 6.7V from VPP Remove VSS from XEN
Restart ST7585 module Check Display Performance
Note: 1. 2. OTP can be written only 1 time and the written value can "NOT" be read out by MPU interface. After writing OTP, a hardware reset (set RESB="L") will let ST7585 exit the "Test Mode".
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Referential OTP Related Codes void Fine_Tune_VOP(void) { Show_Image(); Write(COMMAND,0x20 ); Write(COMMAND,0x0C); Write(COMMAND,0x21); Write(COMMAND,0x35); Write(COMMAND,0x48); Write(COMMAND,0x31); Write(COMMAND,0xB4); Write(COMMAND,0x33); Write(COMMAND,0x41); Or Write(COMMAND,0x42); Write(COMMAND,0x30); } void OTP_Writing(void) { Write(COMMAND,0x20 ); Write(COMMAND,0x08); Write(COMMAND,0x21); Write(COMMAND,0x35); Write(COMMAND,0x71); Write(COMMAND,0xC2); Write(COMMAND,0x9F); Delay (1500); Write(COMMAND,0xA1); Delay (750); Write(COMMAND,0x88); Write(COMMAND,0x30); }
// Display an image // Function Set PD=0,V=0, H=0 //Normal Display On // Function Set PD=0,V=0, H=1 //OTP Function Set T:10 //OTP auto read disable // OTP Function Set T:00 // OSC enable // OTP Function Set T:01 // VOP offset increase 1 step // VOP offset decrease 1 step // Leave OTP Function mode
// Function Set PD=0,V=0, H=0 // Display Off // Function Set PD=1,V=0, H=1 // OTP Function Set T:10 // OTP control in // set OTP address VOP offset // OTP enable // delay 1.5ms // OTP write //delay 750us //OTP control out // Leave OTP Function mode
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; please refer to notes 1 and 2. Parameter Digital Power Supply Voltage Analog Power supply voltage LCD Power supply voltage LCD Power driving voltage Operating temperature Storage temperature Symbol VDD1 VDD2 V0-XV0 VG, VM TOPR TSTR Conditions -0.3 ~ 3.6 -0.3 ~ 3.6 -0.3~15 -0.3 ~ VDD2 -30 to +85 -65 to +150 Unit V V V V

C C
Notes 1. 2. 3. Stresses above those listed under Limiting Values may cause permanent damage to the device. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Insure the voltage levels of V0, VDD2, VG, VM, VSS and XV0 always match the correct relation: V0 VDD2 > VG > VM > VSS XV0
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12. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices.
13. DC CHARACTERISTICS
VDD1=1.8V to 3.3V, VSS=0V; Tamb = -30 C to +85 C; unless otherwise specified. Item Operating Voltage (1) Operating Voltage (2) Input High-level Voltage Input Low-level Voltage Output High-level Voltage Output Low-level Voltage Input Leakage Current Output Leakage Current Liquid Crystal Driver ON Resistance Frame Frequency Note: 1. Please refer to the "Selection of Application Voltage" section for the recommend application Vop voltage level. Symbol VDD1 VDD2 VIHC VILC VOHC VOLC ILI ILO RON FR Ta=25 C

Condition
Rating Min. 1.7 2.6 0.7 x VDD1 VSS Typ. -- -- -- -- -- -- -- -- 0.5 1.0 72 Max. 3.4 3.4 VDD1 0.3 x VDD1 VDD1 0.2 x VDD1 1.0 3.0 -- -- 77
Unit V V V V V V A A K K Hz
Applicable Pin VDD1 VDD2 MPU Interface MPU Interface D[7:0] D[7:0] MPU Interface MPU Interface COMx SEGx
IOUT=1mA, VDD1=1.8V IOUT=-1mA, VDD1=1.8V
0.8 x VDD1 VSS -1.0 -3.0
Vop=9V, V=0.9V VG=2V, V=0.2V
-- -- 68
1/66 Duty, Ta = 25C
Current consumption: During Display, with internal power system, current consumed by whole IC (bare die). Test Pattern Symbol Condition VDD1=VDD2=3V, Display Pattern: SNOW (Static) ISS Booster X5 V0 = 9.0 V, Bias=1/9 Ta=25 C Power Down ISS VDD1=VDD2=3V, Ta=25 C

Rating Min. Typ. Max.
Unit
Note
--
150
220
A
--
3
15
A
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14. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics (For the 8080 Series MPU)
(VDD1 = 3.3V , Ta =25 C) Item Address setup time Address hold time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Write Data hold time (Write) Data access time (Read) Output disable time (Read) D[7:0] /RD /WR Signal A0 Symbol tAW8 tAH8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 16 pF CL = 16 pF Condition Min. 80 10 350 70 50 120 50 60 10 -- 10 -- -- 70 50
Max. -- -- -- -- -- --
Unit
ns
(VDD1 = 2.8V , Ta =25 C) Item Address setup time Address hold time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Write Data hold time (Write) Data access time (Read) Output disable time (Read) D[7:0] /RD /WR Signal A0 Symbol tAW8 tAH8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 16 pF CL = 16 pF Condition Min. 120 15 450 120 100 120 100 90 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Unit
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(VDD1 = 1.8V , Ta =25 C) Item Address setup time Address hold time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Write Data hold time (Write) Data access time (Read) Output disable time (Read) D[7:0] /RD /WR Signal A0 Symbol tAW8 tAH8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 16 pF CL = 16 pF Condition Min. 150 30 550 170 150 170 150 120 30 -- 10 -- -- 240 200 Max. -- -- -- -- -- -- ns Unit
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD1 as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics (For the 6800 Series MPU)
(VDD1 = 3.3V , Ta =25 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) Write data setup time Write data hold time Read data access time Read data output disable time D[7:0] E Signal A0 Symbol tAW6 tAH6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 16 pF CL = 16 pF Condition Min. 80 10 240 70 50 70 130 60 10 -- 10 -- -- 70 50
Max. -- -- -- -- -- --
Unit
ns
(VDD1 = 2.8V , Ta =25 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) Write data setup time Write data hold time Read data access time Read data output disable time D[7:0] E Signal A0 Symbol tAW6 tAH6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 16 pF CL = 16 pF Condition Min. 100 15 340 120 100 120 100 120 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Unit
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(VDD1 = 1.8V , Ta =25 C) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) Write data setup time Write data hold time Read data access time Read data output disable time D[7:0] E Signal A0 Symbol tAW6 tAH6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 16 pF CL = 16 pF Condition Min. 150 30 440 170 150 170 150 180 30 -- 10 Max. -- -- -- -- -- -- -- -- -- 240 200 ns Unit
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD1 as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being "L" and E.
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SERIAL INTERFACE (4-Line Interface)
First bit
Last bit
(VDD1 = 3.3V , Ta =25 C)
Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time
Signal SCLK
Symbol tSCYC tSHW tSLW
Condition
Min. 120 60 60 20 90 20 10 20 120
Max. -- -- -- -- -- -- -- -- --
Unit
A0
tSAS tSAH tSDS tSDH tCSS tCSH
ns
SDA
CSB
(VDD1 = 2.8V , Ta =25 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time A0 SCLK Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Min. 200 100 100 30 120 30 20 30 150 Max. -- -- -- -- -- -- -- -- -- ns Unit
SDA
CSB
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(VDD1 = 1.8V , Ta =25 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time A0 SCLK Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Min. 280 140 140 50 150 50 50 40 180 Max. -- -- -- -- -- -- -- -- -- ns Unit
SDA
CSB
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard.
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SERIAL INTERFACE (3-Line Interface)
First bit
Last bit
(VDD1 = 3.3V , Ta =25 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Data setup time Data hold time CSB-SCLK time CSB-SCLK time SDA SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Min. 120 60 60 20 10 20 130 Max. -- -- -- -- -- -- --
Unit
ns
CSB
(VDD1 = 2.8V , Ta =25 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Data setup time Data hold time CSB-SCLK time CSB-SCLK time SDA SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Min. 180 90 90 30 20 30 160 Max. -- -- -- -- -- -- --
Unit
ns
CSB
(VDD1 = 1.8V , Ta =25 C) Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Data setup time Data hold time CSB-SCLK time CSB-SCLK time SDA SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Min. 240 120 120 60 50 40 190 Max. -- -- -- -- -- -- -- ns Unit
CSB
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard.
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SERIAL INTERFACE (I2C Interface)
(VDD1 = 3.3V , Ta =25C) Item SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time Setup time for a repeated START condition Start condition hold time Setup time for STOP condition SCL,SDA rise time SCL,SDA fall time Capacitive load represented by each bus line Tolerable spike width on bus Bus free time between a STOP and START condition Note: 1. I C timing will be affected by the external pull-up resistor and the ITO resistance of COG.
2
Signal SCL
Symbol fSCLK tLOW tHIGH
Condition
Min. 1.3 0.6 100 0 0.6 0.6 0.6 20+0.1Cb 20+0.1Cb 1.3
Max. 400 0.9 300 300 400 50
Unit KHz us us ns us us us us ns ns pF ns us
SDA
tSU;Data tHD;Data tSU;SUA
SDA
tHD;STA tSU;STO
SCL SDA
tR tF Cb tSW
SCL
tBUF
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RESET TIMING
tRW
RESB
tR
Internal Status
During Reset ...
Reset Complete
(VDD1 = 3.3V , Ta =25 C) Item Reset time Reset "L" pulse width Symbol tR tRW Condition Min. -- 1.5 Max. 1.5 -- Unit us
(VDD1 = 2.8V , Ta =25 C) Item Reset time Reset "L" pulse width Symbol tR tRW Condition Min. -- 2.0 Max. 2.0 Unit us
(VDD1 = 1.8V , Ta =25 C) Item Reset time Reset "L" pulse width Symbol tR tRW Condition Min. -- 3.0 Max. 3.0 -- Unit us
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APPLICATION NOTE
Application Circuits
The application circuits are for reference only and actual settings are dependent on LCD module characteristics.
6800 Interface
79
78
ITO Side
XV0I XV0I XV0I XV0I XV0S XV0O
72
FPC Side
TP3
System
PS2 : VSS1 PS1 : VDD1 PS0 : VSS1 TA : VSS1 MODE : VSS1 OSC : VDD1 TMX : VSS1 TMY : VSS1 BR : VDD1
65
XV0
C1
XV0O V0O V0O V0S V0I V0I V0I V0I VGI VGI VGI VGI VGS VGO VGO VMO VSS2 VSS2 TP4
V0
112 113
Booster X5 Bias : 1/9 Vop : 9.0V Duty : 1/66
58
VG
C2
VSS2 VSS1
54
VSS2 VSS1 VSS1 Reserve Reserve Reserve Reserve VDD1 OSC D0 D1 D2 D3 D4 D5 D6 D7 A0 ERD RWR CSB RESB VDD2 VDD2
52
D0 D1 D2 D3 D4 D5 D6 D7 A0 E R/W CSB RESB VDD2 VDD1
47 46 45
38
35
30
VDD2 VDD1 VDD1 VSS2 VSS2 VSS2 VSS1 VSS1 Reserve Reserve Reserve Reserve Reserve Reserve
28
23
214 215
16
Reserve TMY TMY TMX TMX PS0 PS1 PS2 BR TA MODE VDD1 XEN VPP VPP TP2 For EEPROM TP1
12
6 5
1
248
VPP
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Selection of Application Voltage
Referential LCD Module Setting VDD1=2.8V, VDD2 =2.8V, Panel Size=1.4", Ta=25C Duty 1/66 1. 2. 3. 4. l Note: l l l l Positive Booster: (VDD2 x 5 x BE) V0 or (VDD2 x5 x BE) Vop; Negative Booster: [-VDD2 x4 x BE] XV0 or [VDD2 x4 x BE] (Vop - VG), where VG = Vop x 2 / N; Vop requirement: [VDD2 x4 x BE] [Vop x (N - 2) / N] or [Vop VDD2 x4 x BE x N / (N - 2)]. BE is the booster efficiency. Referential values are listed below: (assume VDD2 =2.8V) Module Size 1.4": BE=80% (Typical); Module Size = 1.5"~1.8": BE=76% (Typical). Actual BE should be determined by module loading and ITO resistance value. l l l 1.6V VG < VDD2. Recommend VG is: VDD2-VG around 0.5~0.8V. VM=VG/2 and 0.8V VM < VDD2. The worse condition should be considered: Low temperature effect and display on with snow pattern on panel (max: 1.8"). Booster X5 Vop 8.8V 8.6V Bias 1/9 1/7
*1
Adjustment +/- 0.3V +/- 0.2V
*2
Temperature Effect (-30C) + 0.24V + 0.23V
*3
Max. Vop 9.34V 8.93V
*4
The Bias can be used to select suitable Liquid Crystal. It is usually reserved some range for user adjustment (the reserved range depends on customer's system). Be sure that: there is a suitable V0 level can be programmed into the V0 control register (V0[4:0]). The internal Regulator has Temperature Gradient (-0.05%/C). Be sure that: the "Max. Vop" is still available by internal Booster (watch out the Booster Efficiency). Besides, the VG limitation should be followed. The display performance should be checked with customer's LCD modules.
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ITO Layout Reference
[ VDD and VSS Layout ] 1. 2. The VDD and VSS of the internal digital and analog system should be separated on ITO and then short by FPC. This can isolate the operating noise. Try to keep the ITO resistance as small as possible. The recommend resistance priority is: RVSS2 RVDD2 RVDD1 RVSS1
[ LCD Power Layout ] 1. 2. In order to increase voltage accuracy, a layout topology shown below is required. Try to keep the ITO resistance as small as possible. The recommend resistance priority is: (take VG as example) RVGI RVGO RVGS
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REVERSION HISTORY
Version
0.0 0.1 0.2 0.3
Date
2007/10/17 2008/01/17 2008/01/22 2008/03/19 Preliminary 1. 2. Add PAD information Modify description
Description
Add application circuits: 6800, 8080, SPI-3 & SPI-4 1. 2. 3. 1. 2. 3. 4. 1. 2. Update Chip Size. Add OTP operation information. Add 3 VSS2 pads for new version. Modify OTP command table Add I C timing spec modify power on flow reset wait time modify DC characteristics Add I C application circuit. Modify P18 typo. Timing TBD remove RON value modify Add selection of VOP Update VDD2 Operation Range: Typical=2.7V~3.3V, Minimum=2.6V. Add precautions to: OTP Burning Flow, I C interface timing. Modify Vop range in "Selection of Application Voltage". Reserve Pin 48. Fix Fig 11 and redraw Fig 10.
2 2 2
0.4
2008/08/04
1.0
2008/12/10
3. 4. 5. 1.
1.0b
2008/12/31
2. 3. 1. 2.
1.0c
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