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| Cover MVPG15x/MVPG16 Field Programmable DSP SwitcherTM 1 MHz, 1.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology Datasheet Doc. No. MV-S102809-00, Rev. G April 14, 2008 Marvell. Moving Forward Faster Document Classification: Proprietary MVPG15x/MVPG16 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: 2.00 Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 2008. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners. Doc. No. MV-S102809-00 Rev. G Page 2 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 MVPG15x/MVPG16 1 MHz, 1.5A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology Datasheet PRODUCT OVERVIEW The Marvell(R) MVPG15x/MVPG16 is an intelligent digital synchronous step-down (Buck) switching regulator housed in a 4 mm x 3 mm DFN-12 package. The MVPG15x has an additional on-chip Low-Drop-Out (LDO) regulator controller. Internally self-compensated, the step-down regulator requires no external compensation and work with low-ESR output capacitors to simplify the design, minimize the board space, and reduce the amount of external components. The switching frequency for the step-down regulator is 1 MHz, allowing the use of low profile surface mount inductors and low value capacitors. The step-down regulator includes programmable output voltage to provide the user the ability to easily set the output voltage with external resistors, logic control, or serial data interface. The output voltage range is 0.72V to 3.63V. The LDO regulator controller with an external P-Channel MOSFET forms a low dropout regulator capable of driving 800 mA output current. The output voltage of the LDO regulator is fixed. The MVPG15x/MVPG16 operate from an input voltage range of 3.0V to 5.5V, making the device well-suited for portable applications. Other key features of the MVPG15x/MVPG16 include an internal current limit for the step-down regulator, an Under Voltage Lockout (UVLO), and thermal shutdown. Features Tiny 4 mm x 3 mm DFN-12 package 1 MHz switching frequency Small and low profile inductors Stable with ceramic output capacitors No external compensation required Minimum amount of external components Over 95% efficiency High peak switch current limit: 1.5A Input voltage range: 3.0V to 5.5V Serial/Logic programmability AnyVoltageTM Technology provides 64 output voltage selections to provide flexibility Programmable output voltage range: 0.72V to 3.63V P-Channel LDO regulator controller with programmable current limit (MVPG15x) Lead-free packages Built-in under voltage lockout Over voltage protection Thermal shutdown protection Output voltage margining capability Application Portable computing Point of load power supplies DSP power supplies Disk drive power supplies Figure 1: Typical High Efficiency 5.0V to 0.8V/3.0A Step-Down Regulator with 3.3V LDO Regulator R1 R2 10 C2 10uF/6.3V 7 8 C1 0.1uF R3 11K 11 12 10 4 47 mohm U1 PVIN SVIN LFB VSET PSET PGND SHDN SGND MVPG15B SW SFB 6 4.7uH 5 C4 10uF/6.3V 2 ILIM 3 1 L1 VIN +3.0V to + 5.5V FDC642P C3 10uF/6.3V VOUT1 3.3V/up to 0.8A LDR VOUT2 0.8V/1A Caution This is a very high frequency device and proper PCB layout is required. Refer to Section 6, Applications Information, on page 49 for further information. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary EP Doc. No. MV-S102809-00 Rev. G Page 3 MVPG15x/MVPG16 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102809-00 Rev. G Page 4 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Table of Contents Table of Contents Product Overview ....................................................................................................................................... 3 Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables ............................................................................................................................................ 11 1 1.1 1.2 1.3 Signal Description ....................................................................................................................... 13 Pin Configuration.............................................................................................................................................13 Pin Type Definitions .......................................................................................................................................15 Pin Description ................................................................................................................................................15 2 2.1 2.2 2.3 2.4 2.5 Electrical Specifications ............................................................................................................. 17 Absolute Maximum Ratings ............................................................................................................................17 Recommended Operating Conditions .............................................................................................................18 Electrical Characteristics ................................................................................................................................19 Switching Step-down Regulator ......................................................................................................................20 LDO Regulator Controller................................................................................................................................21 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Functional Description................................................................................................................ 23 Regulation and Startup ...................................................................................................................................24 3.1.1 Digital Soft Start ................................................................................................................................24 Output Voltage--AnyVoltageTM Technology ...................................................................................................26 Programmable Current Limit for the LDO Regulator Controller ......................................................................28 3.3.1 Maximum LDO Output Current .........................................................................................................29 Under Voltage Lockout....................................................................................................................................29 Over Voltage Protection ..................................................................................................................................29 Thermal Shutdown ..........................................................................................................................................30 Adaptive Transient Response .........................................................................................................................31 4 4.1 4.2 4.3 Functional Characteristics ......................................................................................................... 33 Startup Waveforms .........................................................................................................................................33 Switching Waveforms......................................................................................................................................36 Load Transient Waveforms .............................................................................................................................37 4.3.1 Step-Down Regulator .......................................................................................................................37 4.3.2 LDO Regulator ..................................................................................................................................38 5 5.1 5.2 Typical Characteristics ............................................................................................................... 39 Efficiency Graphs ............................................................................................................................................39 Load Regulation ..............................................................................................................................................40 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 5 MVPG15x/MVPG16 Datasheet 5.3 5.4 5.5 5.6 Dropout Voltage ..............................................................................................................................................40 RDS (ON) Resistance .....................................................................................................................................41 IC Case and Inductor Temperature.................................................................................................................42 Input Voltage Graph ........................................................................................................................................43 5.6.1 Step-Down Regulator .......................................................................................................................43 5.6.2 LDO Regulator ..................................................................................................................................45 Temperature Graphs .......................................................................................................................................46 5.7.1 Step-Down Regulator .......................................................................................................................46 5.7.2 LDO Regulator ..................................................................................................................................48 5.7 6 6.1 6.2 Applications Information ............................................................................................................ 49 PC Board Layout Considerations and Guidelines ..........................................................................................49 6.1.1 PC Board Layout Examples for MVPG30x/MVPG31 .......................................................................51 Bill of Materials ................................................................................................................................................54 7 7.1 7.2 7.3 Mechanical Drawing .................................................................................................................... 57 Mechanical Drawing ........................................................................................................................................57 Dimensions .....................................................................................................................................................58 Typical Pad Layout Dimensions ......................................................................................................................59 7.3.1 Recommended Solder Pad Layout ...................................................................................................59 8 8.1 8.2 Part Order Numbering/Package Marking .................................................................................. 61 Part Order Numbering .....................................................................................................................................61 Package Marking ............................................................................................................................................62 A Revision History .......................................................................................................................... 65 Doc. No. MV-S102809-00 Rev. G Page 6 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 List of Figures List of Figures Product Overview ....................................................................................................................................... 3 Figure 1: Typical High Efficiency 5.0V to 0.8V/2.0A Step-Down Regulator with 3.3V LDO Regulator ..............3 1 Signal Description ........................................................................................................................... 13 Figure 2: Figure 3: 12-Pin DFN Pin Diagram--MVPG30x Top View ..............................................................................13 12-Pin DFN Pin Diagram--MVPG31 Top View ................................................................................14 2 3 Electrical Specifications ................................................................................................................. 17 Functional Description.................................................................................................................... 23 Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: MVPG30x/MVPG31 Block Diagram .................................................................................................23 Output Voltage Window ....................................................................................................................24 Inductor Current Steps at Startup .....................................................................................................25 Soft Startup (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) ......................................................................................25 Soft Startup.......................................................................................................................................25 Startup Sequence ............................................................................................................................27 VSET = 2.5V and PSET = -5% ............................................................................................................27 Maximum Output Current for the FDS642P P-Channel MOSFET....................................................29 UVLO and OVP Waveforms .............................................................................................................30 Adaptive Transient Response ..........................................................................................................31 4 Functional Characteristics.............................................................................................................. 33 Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Startup Using the Shutdown Pin ......................................................................................................33 Turn Off Using the Shutdown Pin .....................................................................................................33 Enable Threshold at VIN = 3.5V ........................................................................................................33 Enable Threshold at VIN = 5.0V ........................................................................................................33 Input Voltage Soft Start.....................................................................................................................34 Input Voltage Hot Plug ......................................................................................................................34 Step-Down Output Rise Time ...........................................................................................................34 Soft Start Current Limit Steps ...........................................................................................................34 UVLO and OVP Thresholds..............................................................................................................35 Switching Waveforms-- PWM Mode ...............................................................................................36 Switching Waveforms-- DCM Mode.................................................................................................36 PWM Output Ripple Voltage .............................................................................................................36 Switching Waveforms-- DCM Mode-Zoom ......................................................................................36 Load Transient Response ................................................................................................................37 Double-Pulsed Load Response ........................................................................................................37 Load Transient Response ................................................................................................................37 Double-Pulsed Load Response ........................................................................................................37 Load Transient Response ................................................................................................................38 Double-Pulsed Load Response ........................................................................................................38 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 7 MVPG15x/MVPG16 Datasheet Figure 33: Load Transient Response ................................................................................................................38 5 Typical Characteristics ................................................................................................................... 39 Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: Figure 57: Figure 58: Figure 59: Efficiency Graphs..............................................................................................................................39 Load Regulation................................................................................................................................40 Dropout Voltage ................................................................................................................................40 RDS (ON) Resistance.......................................................................................................................41 IC Case and Inductor Temperature ..................................................................................................42 Supply Current vs. Input Voltage ......................................................................................................43 Output Voltage vs. Input Voltage ......................................................................................................43 Efficiency vs. Input Voltage...............................................................................................................43 Load Regulation vs. Input Voltage ....................................................................................................44 Frequency vs. Input Voltage .............................................................................................................44 Average Output Current Limit vs. Input Voltage ...............................................................................44 Output Voltage vs. Input Voltage ......................................................................................................45 LDO Load Regulation vs. Input Voltage ...........................................................................................45 Average Output Current Limit vs. Input Voltage ...............................................................................45 Supply Current vs. Temperature.......................................................................................................46 UVLO vs. Temperature .....................................................................................................................46 Output Voltage vs. Temperature.......................................................................................................46 Efficiency vs. Temperature ...............................................................................................................46 Load Regulation vs. Temperature ....................................................................................................47 Line Regulation vs. Temperature......................................................................................................47 Average Output Current Limit vs. Temperature ................................................................................47 Frequency vs. Temperature..............................................................................................................47 Output Voltage vs. Temperature.......................................................................................................48 Load Regulation vs. Temperature ....................................................................................................48 Line Regulation vs. Temperature......................................................................................................48 Average Output Current Limit vs. Temperature ................................................................................48 6 Applications Information ................................................................................................................ 49 Figure 60: Figure 61: Figure 62: Figure 63: Figure 64: Figure 65: Figure 66: Figure 67: MVPG30x PCB Layout Schematic ...................................................................................................50 MVPG31 PCB Layout Schematic .....................................................................................................50 Top Silk-Screen (Not to scale)--MVPG30x ......................................................................................51 Top Silk-Screen (Not to scale)--MVPG31........................................................................................51 Top Traces, Vias, and Copper (Not to scale)--MVPG30x................................................................52 Top Traces, Vias, and Copper (Not to scale)--MVPG31 .................................................................52 Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale)--MVPG30x ...............53 Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale)--MVPG31 .................53 7 Mechanical Drawing ........................................................................................................................ 57 Figure 68: Figure 69: Mechanical Drawing .........................................................................................................................57 Recommended Solder Pad Layout ...................................................................................................59 8 Part Order Numbering/Package Marking....................................................................................... 61 Doc. No. MV-S102809-00 Rev. G Page 8 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 List of Figures Figure 70: Figure 71: Figure 72: Sample Part Order Number ..............................................................................................................61 MVPG30x Package Marking.............................................................................................................62 MVPG31 Package Marking ..............................................................................................................63 A Revision History ............................................................................................................................... 65 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 9 MVPG15x/MVPG16 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102809-00 Rev. G Page 10 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 List of Tables List of Tables 1 Signal Description ............................................................................................................................ 13 Table 1: Table 2: Pin Type Definitions ..........................................................................................................................15 Pin Description..................................................................................................................................15 2 Electrical Specifications .................................................................................................................. 17 Table 3: Table 4: Table 5: Table 6: Table 7: Absolute Maximum Ratings ..............................................................................................................17 Recommended Operating Conditions...............................................................................................18 Electrical Characteristics ..................................................................................................................19 Switching Step-down Regulator........................................................................................................20 LDO Regulator Controller .................................................................................................................21 3 Functional Description..................................................................................................................... 23 Table 8: Table 9: Table 10: AnyVoltageTM Programming Table for 1% Resistors .......................................................................26 Output Voltage Option Steps ............................................................................................................27 P-Channel MOSFET Selection .........................................................................................................28 4 5 6 Functional Characteristics............................................................................................................... 33 Typical Characteristics .................................................................................................................... 39 Applications Information ................................................................................................................. 49 Table 11: Table 12: MVPG30x BOM ................................................................................................................................54 MVPG31 BOM ..................................................................................................................................55 7 8 A Mechanical Drawing ......................................................................................................................... 57 Table 13: Dimensions .......................................................................................................................................58 Part Order Numbering/Package Marking........................................................................................ 61 Table 14: Part Order Options............................................................................................................................61 Revision History ............................................................................................................................... 65 Table 15: Revision History ................................................................................................................................65 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 11 MVPG15x/MVPG16 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102809-00 Rev. G Page 12 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Signal Description Pin Configuration 1 1.1 Signal Description Pin Configuration Figure 2: 12-Pin DFN Pin Diagram--MVPG15x Top View LFB 1 12 PSET ILIM 2 11 VSET LDR 3 10 SHDN MVPG15x 9 NC SGND 4 SFB 5 PGND 8 SVIN SW 6 7 PVIN Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 13 MVPG15x/MVPG16 Datasheet Figure 3: 12-Pin DFN Pin Diagram--MVPG16 Top View NC 1 12 PSET NC 2 11 VSET NC 3 10 SHDN MVPG16 9 NC SGND 4 SFB 5 PGND 8 SVIN SW 6 7 PVIN Doc. No. MV-S102809-00 Rev. G Page 14 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Signal Description Pin Type Definitions 1.2 Table 1: Pi n Typ e I O S NC GND Pin Type Definitions Pin Type Definitions Defi ni ti o ns Input only Output only Supply Not Connected Ground 1.3 Pin Description Table 2 provides pin descriptions for the MVPG15x/MVPG16. Table 2: MVPG15x Pi n # 1 Pin Description MVPG16 Pi n # -P in N a m e P i n Ty p e Pi n F u nc t io n LFB I LDO Regulator Controller Feedback Senses the output voltage of the LDO regulator. Connect to the drain of the P-channel MOSFET. When the LDO controller is not used, float the LDR pin. Connect the LFB to SGND, and connect ILIM to SVIN. Current-Limit Sense Pin for the LDO Regulator A built-in offset of 50 mV (typical) between VIN and ILIM in conjunction with the sense resistor is used to set the current-limit threshold for the LDO regulator controller. Connecting this pin to VIN disables the internal current limit circuitry. When the LDO controller is not used, float the LDR pin. Connect the LFB to SGND, and connect ILIM to SVIN. LDO Regulator Controller Driver Connect to the gate of an external P-channel MOSFET. The external P-Channel MOSFET needs to have a threshold of -2.5V or lower and input capacitance (Ciss) of less than 1000 pF. When the LDO controller is not used, float the LDR pin. Connect the LFB to SGND, and connect ILIM to SVIN. Signal Ground This pin must connect to the power ground. Switching Regulator Feedback Senses the output voltage of the switching regulator. Switch Node Internal power MOSFET drain. This pin must connect to an external inductor. 2 -- ILIM I 3 -- LDR O 4 4 SGND O 5 5 SFB I 6 6 SW O Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 15 MVPG15x/MVPG16 Datasheet Table 2: MVPG15x Pi n # 7 Pin Description (Continued) MVPG16 Pi n # 7 P in N a m e P i n Ty p e Pi n F u nc t io n PVIN I Power Input Voltage Internal power MOSFET source. Connect the decoupling 10 F capacitors between PVIN and PGND and position it as close as possible to the IC. Signal Input Voltage Input voltage is 3.0V to 5.5V for internal circuitry. Connect a 0.1 F decoupling capacitor between SVIN and SGND and position it as close as possible to the IC. No Connect This pin is left floating. Do not connect this pin. Shutdown Logic low (0.8V) enables the step-down switching regulator and the LDO regulator controller. Logic high (2.0V) disables the step-down switching regulator and the LDO regulator controller. The high signal duration has to be at least 20 s to disable both regulators. Voltage Set 1. Connect an external resistor to ground to set the output voltage of the step-down switching regulator. See Table 5, Electrical Characteristics, on page 19 for resistor values and output voltage options. 2. The total capacitance across this pin and SGND should not be greater than 25 pF. Shorting this pin to signal ground, floating this pin, or using 619 k< RVSET or RVSET<7.68 k disables the step-down switching regulator and sets the SFB pin to high impedance. Use resistor value with tolerance better than 2%. Percent Set 1. Connect an external resistor to ground to set the output voltage of the step-down switching regulator. See Table 5, Electrical Characteristics, on page 19 for resistor values and output voltage options. 2. The total capacitance across this pin and SGND should not be greater than 25 pF. Shorting this pin to signal ground, floating this pin, or using 619 k< RPSET or RPSET<7.68 k does not affect the set voltage. Use resistor value with tolerance better than 2%. Although this pin can be left floating when it is not used, it is recommended to connect this pin to ground. Power Ground The power ground must connect to the negative terminal of the input and output capacitors. 8 8 SVIN I 9 1, 2, 3, 9 NC O 10 10 SHDN I 11 12 VSET I 12 12 PSET I Exposed Pad Exposed Pad PGND GND Doc. No. MV-S102809-00 Rev. G Page 16 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Electrical Specifications Absolute Maximum Ratings 2 2.1 Table 3: Electrical Specifications Absolute Maximum Ratings Absolute Maximum Ratings1 NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter PVIN to PGND PVIN to SVIN PGND to SGND VSW to PGND2 VSFB to SGND VVSET, VPSET to SGND VILIM, VLDR, VLFB to SGND VSHDN to SGND Operating Ambient Temperature Range3 Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s) ESD Rating4 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 --65 --Ty p -----------300 2.0 Max 6.0 +0.3 +0.3 (PVIN +0.3) (SVIN +0.3) (SVIN +0.3) (SVIN +0.3) (SVIN +0.3) 85 150 150 --U n i ts V V V V V V V V C C C C kV 1. Exceeding the absolute maximum rating may damage the device. 2. Capable of -1.0V for less than 50 ns. 3. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. 4. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5 k, in series with 100 pF. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 17 MVPG15x/MVPG16 Datasheet 2.2 Table 4: Sy m b o l SVIN PVIN JA JC TJMAX Recommended Operating Conditions Recommended Operating Conditions1 P a r a m e te r Signal Input Voltage Power Input Voltage Package Thermal Resistance2 Min 3.0 3.0 --Maximum Operating Junction Temperature -Ty p --48.1 4.4 -Max 5.5 5.5 --125 U n i ts V V C/W C/W C 1. This device is not guaranteed to function outside the specified operating range. 2. Tested on 4-layer (JESD51-7) and vias (JESD51-5) boards. Doc. No. MV-S102809-00 Rev. G Page 18 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Electrical Specifications Electrical Characteristics 2.3 Table 5: Electrical Characteristics Electrical Characteristics NOTE: The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VSHDN = SGND = PGND, L(BUCK) = 4.7 H, COUT(BUCK) = 10 F (Ceramic), PFET = FDC642P, COUT(LDO) = 10 F (Ceramic), TA = 25C. Bold values indicate -40C < TA < 85C. Sy m b o l SVIN P a r a m e te r Input Voltage Range Total Quiescent Current ISVIN VUVLO Shutdown Supply Current Under Voltage Lockout C o nd i ti on s SVIN = PVIN No load, VOUT = TBD VSHDN = SVIN = 5.5V High threshold, SVIN increasing, ILOAD = 10mA Low threshold, SVIN decreasing, ILOAD = 10mA VOVP Over Voltage Protection High threshold, SVIN increasing, ILOAD = 10mA Low threshold, SVIN decreasing, ILOAD = 10mA VSHDN Shutdown Input Voltage Logic Enable regulators Disable regulators ISHDN TOTS Shutdown Input Current VSHDN = SGND = PGND or 5.5V TJ increasing (Disable regulators) TJ decreasing (Enable regulators) Min 3.0 ---Ty p e -1.3 1.0 2.65 Max 5.5 -10 2.85 U n its V mA A V 2.35 2.50 -- V -- 5.7 TBD V TBD 5.6 -- V -2.0 -- ---- 0.8 -1.0 V A Over-temperature Thermal Shutdown -- 150 -- C -- 120 -- C Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 19 MVPG15x/MVPG16 Datasheet 2.4 Table 6: Switching Step-down Regulator Switching Step-down Regulator NOTE: The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VPSET = VSHDN = SGND = PGND, RVSET = 11 k, L = 4.7 H, COUT = 10 F (Ceramic), TA = 25 C. Bold values indicate -40C < TA < 85C. Sy m b o l P a r a m e te r Output Voltage Conditions RVSET = 11K, PWM mode RVSET = 18.7K, PWM mode RVSET = 31.6K, PWM mode RVSET = 53.6K, PWM mode RVSET = 97.6K, PWM mode RVSET = 165K, PWM mode RVSET = 280K, PWM mode RVSET = 475K, PWM mode Percentage Set RPSET = 11K RPSET = 18.7K RPSET = 31.6K RPSET = 53.6K RPSET = 97.6K RPSET = 165K RPSET = 280K RPSET = 475K VLNREG Output Voltage Line Regulation SVIN = PVIN = 3.0V to 5.0V VOUT = 1.5V ILOAD = 250 mA SVIN = PVIN = 5.0V VOUT = 1.5V ILOAD = 250 mA to 1.0A PWM mode SVIN = 3.0V, ISW = 100 mA SVIN = 5.0V, ISW = 100 mA RNFET RDS(ON) = of N-Channel FET Minimum Peak Switch Current Limit SVIN = 3.0V, ISW = 100 mA SVIN = 5.0V, ISW = 100 mA ILIM M in -----------------Ty p 0.8 1.0 1.2 1.5 1.8 2.5 3.0 3.3 -10 -7.5 -5.0 -2.5 2.5 5.0 7.5 10 0.08 Max -----------------% % U ni ts V VLDREG Output Voltage Load Regulation -- 0.05 -- % fSW RPFET Switching Frequency RDS(ON) = of P-Channel FET ------- 1.0 150 120 90 70 1.5 ------- MHz m m A Doc. No. MV-S102809-00 Rev. G Page 20 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Electrical Specifications LDO Regulator Controller Table 6: Switching Step-down Regulator (Continued) NOTE: The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VPSET = VSHDN = SGND = PGND, RVSET = 11 k, L = 4.7 H, COUT = 10 F (Ceramic), TA = 25 C. Bold values indicate -40C < TA < 85C. Sy m b o l ILSW P a r a m e te r Switch Leakage Current Conditions SVIN = PVIN = VSHDN = 5.5V VSW = PGND or 5.5V M in -Ty p 1 Max 50 U ni ts A 2.5 Table 7: LDO Regulator Controller LDO Regulator Controller NOTE: The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VSHDN = SGND = PGND, PFET= FDC642P, COUT = 10 F, TA = 25 C. Bold values indicate -40C < TA < 85C. Sy m b o l P a r a m e te r Output Voltage Accuracy C o nd i ti on s Room Temp, ILOAD = 10 mA Over Temp, ILOAD = 10 mA VLNREG Line Regulation SVIN = PVIN = 3.5V to 5.0V, VOUT = 3.3V, ILOAD = 10 mA SVIN = PVIN = 5.0V, VOUT = 3.3V, ILOAD = 10 mA to 800 mA SVIN-VILIM M in -Ty pe 1 Max -U ni ts % -- 2 -- -- 0.08 -- % VLDREG Load Regulation -- 0.05 -- % VILTH Current-Limit Threshold -- 50 -- mV Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 21 MVPG15x/MVPG16 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102809-00 Rev. G Page 22 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Functional Description 3 Functional Description Figure 4: MVPG15x/MVPG16 Block Diagram VIN +3.0V - 5.5V PVIN C2 Q1 RSENSE C1 VOUT1 C3 R1 SVIN INTERNAL CIRCUITRY POWER SUPPLY ILIM LDR OSCILLATOR CURRENT LIMIT LDO CONTROLLER LFB ENABLE_LDO ANALOGDIGITAL CONVERTER DSP PWM CONTROL L1 DRIVER SW PGND VOUT2 C4 FAULT ENABLE_LDO RESISTOR NETWORK UNDERVOLTAGE LOCK-OUT SFB UVLO_LDO BAND-GAPVOLTAGE REFERENCE FAULT THERMAL SHUT-DOWN RESISTOR SENSING CIRCUITRY SGND ON SHDN OFF VSET R2 PSET R3 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 23 MVPG15x/MVPG16 Datasheet 3.1 Regulation and Startup The step-down switching regulator uses Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) modes to regulate the output voltage using digital control. The mode of operation depends on the level of output current and the output voltage. In steady states, the step-down switching regulator monitors the current flowing through the inductor to determine if the regulator is handling heavy or light load applications. For heavy load applications, the step-down regulator operates in the PWM mode (B and C) to minimize the ripple current for optimum efficiency and to minimize the ripple output voltage. The step-down regulator operates in the PFM and Discontinuous Conduction Mode (DCM) (A and D) to limit the switching actions for optimum efficiency in light load applications. In this mode, the average output voltage is slightly higher than the average output voltage for heavy transient load applications. Figure 5: Output Voltage Window Typical VOUT A B C D PFM Mode PWM Mode PFM Mode 3.1.1 Digital Soft Start During startup, the MVPG15x/MVPG16 provides a soft start function. Soft start reduces surge currents from the input voltage and provides well-controlled output voltage rise characteristics. The rate of the output voltage startup is limited by the value of the output capacitor and the internal current limit circuitry. This combination forces the output voltage to ramp up slowly, providing a soft start characteristic. During soft start, the MVPG15x/MVPG16 feeds a constant current to the output capacitor in several steps. Figure 6 shows the inductor current waveform during startup. The current limit is ramped up in seven steps beginning at approximately 40% of the current limit rating and ending at 100% at 25 s per step. The buck regulator behaves like a current source during this time as the output ramps up slowly. Figure 7 shows that the rise time for a MVPG15x/MVPG16 increases from 20 s at for a 0.8V output to 70 s for a 3.3V output with a 20 mA load. From Figure 8, the rise time can be estimated by assuming an average charging current of 0.75A. Rise time with a 3.3V output is calculated using the following equation. Cout * Vout RiseTime = -----------------------------I 22F * 3.3V = ------------------------------ = 96.8s 0.75A Doc. No. MV-S102809-00 Rev. G Page 24 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Functional Description Regulation and Startup Figure 6: Inductor Current Steps at Startup Figure 7: Soft Startup (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) 1V/DIV VBUCK VBUCK 500 mV/DIV IIND 500 mA/DIV 50 s/DIV COUT = 22 F 10 s/DIV ILOAD = 20 mA Figure 8: Soft Startup VOUT 1V/DIV IOUT 1A/DIV 50 s/DIV VOUT = 3.3V ILOAD = 3.3 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 25 MVPG15x/MVPG16 Datasheet 3.2 Output Voltage--AnyVoltageTM Technology The output voltage of the step-down switching regulator is programmed by using Table 8 to select resistor values for VSET and PSET pin. The VSET pin sets the output voltage and the PSET pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 165 k resistor is selected for the VSET pin, and an 11 k resistor is selected for the PSET pin. The 165 k resistor sets the output voltage to 2.5V and the 11 k resistor trims the set voltage by -10%. Using the VSET resistor's value greater than 619 k or less than 7.68 k disables the step-down switching regulator and sets the SW pin to high impedance. If the VSET resistor's value is outside the 2% tolerance, the output can be either higher or lower than the set voltage. Using resistor values greater than 619 k or less than 7.68 k for the PSET pin does not affect the set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor, the percent value can be either higher or lower if the PSET resistor's value is outside the 2% tolerance. Table 8: AnyVoltageTM Programming Table for 1% Resistors P SE T - 1 0 .0 % 11 k - 7 .5 % 1 8 .7 k Hi-Z 0.740 0.925 1.110 1.388 1.665 2.313 2.775 3.053 Hi-Z -5.0% 31.6k Hi-Z 0.760 0.950 1.140 1.425 1.710 2.375 2.850 3.135 Hi-Z - 2 .5 % 5 3 .6 k Hi-Z 0.780 0.975 1.170 1.463 1.755 2.438 2.925 3.218 Hi-Z 0% GND Hi-Z 0.800 1.000 1.200 1.500 1.800 2.500 3.000 3.300 Hi-Z 2.5% 97.6k Hi-Z 0.820 1.025 1.230 1.538 1.845 2.563 3.075 3.383 Hi-Z 5. 0 % 16 5 k Hi-Z 0.840 1.050 1.260 1.575 1.890 2.625 3.150 3.465 Hi-Z 7 .5 % 280k Hi-Z 0.860 1.075 1.290 1.613 1.935 2.688 3.225 3.548 Hi-Z 1 0 . 0% 475k Hi-Z 0.880 1.100 1.320 1.650 1.980 2.750 3.300 3.630 Hi-Z GND 11 k 1 8 .7 k 3 1 .6 k VS E T 5 3 .6 k 9 7 .6 k 165k 280k 475k Open Hi-Z 0.720 0.900 1.080 1.350 1.620 2.250 2.700 2.970 Hi-Z The VSET and PSET resistors are read once during startup before the output voltage is turned on. The output voltage cannot be changed on-the-fly. To configure the output to a different voltage, power has to recycle or the MVPG15x/MVPG16 has to turn OFF and back ON using the shutdown pin. Figure 9 shows the startup waveforms of the MVPG15x/MVPG16. Once the input voltage (VIN) is above the Under Voltage Lockout (UVLO) Upper Threshold (UTH), the VSET and PSET pin become active. Current is first sourced out of PSET pin and then the VSET pin, in exponentially increasing steps. After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET voltage is below internal reference voltage, the current source proceeds to the next step. Once the VSET voltage is above the internal reference voltage the sequence stops and the output voltage (VOUT) is allowed to turn on. Figure 10 shows the VSET waveform for VSET = 2.5V and PSET = -5% output. The MVPG15x/MVPG16 keeps track of how many steps are Doc. No. MV-S102809-00 Rev. G Page 26 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Functional Description Output Voltage--AnyVoltageTM Technology required to determine the appropriate output voltage. Table 9 provides the number of steps necessary for each output voltage option. Using a VSET resistor of 165 k requires the current source to step four times, and a PSET resistor of 31.6 k requires seven steps. Figure 9: Startup Sequence Figure 10: VSET = 2.5V and PSET = -5% VIN VOUT VSET PSET 2V/DIV VSET 500mV/DIV 1V/DIV 20m 500mV/DIV PSET 1V/DIV 500 1V/DIV 2.0 ms/DIV 200 s/DIV Table 9: Ste p Output Voltage Option Steps VOUT (V ) 0 3.3 3.0 2.5 1.8 1.5 1.2 1.0 0.8 R VSET (k ) 0 475 280 165 97.6 53.6 31.6 18.7 11 St ep P SE T (%) 0 +10 +7.5 +5.0 +2.5 -2.5 -5.0 -7.5 -10 R PSET (k ) 0 475 280 165 97.6 53.6 31.6 18.7 11 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 The MVPG15x/MVPG16 provides an innovative technique to set the output voltage. During startup it reads the value of external resistors, which are located outside the regulator's feedback loop to program the output voltage. By placing the output voltage programming resistor outside the regulator's feedback loop, its tolerance does not affect the accuracy of the output voltage. Normally, adjustable regulators use 1% resistors to set the output voltage. However, these resistors are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. Whereas, the MVPG15x/MVPG16 initial accuracy is 2% for any of the eight output voltages. The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The output voltage can potentially be programmed to the lower output voltage if there is contamination, which introduces excessive leakage current on the VSET and PSET pin, especially for the 3.3V output or +10%. The parasitic resistance on these nodes must be greater than 3 M and the stray capacitance must be less than 25 pF; otherwise, a 3.3V output can potentially end up at 3V. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 27 MVPG15x/MVPG16 Datasheet 3.3 Programmable Current Limit for the LDO Regulator Controller A sense resistor is placed between SVIN and ILIM pin to program the current limit of the LDO regulator controller. The following equation is used to determine the value of the sense resistor. 50mV ( Typical ) I LIM = --------------------------------------R SENSE ( m ) When the LDO regulator controller is in current limit, the internal current-limit circuitry turns off the LDO regulator controller and holds the LDO regulator controller in the off state for 3 ms (typical hold time). After the hold-time is expired, the LDO regulator controller is enabled. The current-limit circuitry continues to disable and enable the regulator until the current limit is removed. The LDO regulator P-channel MOSFET can be selected from the following list based on the required current and ambient temperature. Table 10: P-Channel MOSFET Selection P ac k a g e Super SOT-6 Vi sh a y F a ir c h i ld FDC642P FDC634P FDN340P FDN302P Si4433DY FDS9431A FDJ127P FDP4020P Si3443DV FDG330P Si2333DS Si5473DC Si1039X Si1012R/X Super SOT-3 / micro 3 SO-8 SC75-6 FLMP TO-263AB (D2-Pack) TSOP-6 SC70-6 SOT-23 1206-8 Chip FET SC-89 (6-lead) SC75A/SC-89 (3-lead) Doc. No. MV-S102809-00 Rev. G Page 28 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Functional Description Under Voltage Lockout 3.3.1 Maximum LDO Output Current The FDS642P is design to provide up to 800 mA of continuous output current. However, the tiny Super SOT-6 package can dissipate up to 0.7W. If the input and output voltage are close, then the full 800 mA is achieved (see Figure 11). As the input voltage increases, the IC dissipates more power, limiting the maximum output current. The output current has to decrease in order to keep the power dissipation under its 0.7W limit. Figure 11: Maximum Output Current for the FDS642P P-Channel MOSFET Maximum LDO Output Current vs. Input Voltage 1.0 0.8 0.6 0.4 0.2 0.0 3 3.5 4 Input Voltage (V) 4.5 5 3.4 Under Voltage Lockout At startup, the MVPG15x/MVPG16 incorporates Under Voltage Lockout (UVLO) circuitry to enable the step-down switching regulator and the LDO controller when the input voltage is above 2.60V (typical). After the MVPG15x/MVPG16 is enabled and the input voltage is lowered, the highest value of the minimum input voltage for both regulators to remain enabled is 2.50V (typical). 3.5 Over Voltage Protection The MVPG15x/MVPG16 incorporates an Over Voltage Protection (OVP) circuitry to disable the step-down switching regulator and LDO controller when the input voltage is above 5.7V (typical). The step-down switching regulator and LDO controller are enabled when the input voltage is below 5.6V (typical). Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Load Current (A) Doc. No. MV-S102809-00 Rev. G Page 29 MVPG15x/MVPG16 Datasheet Figure 12: UVLO and OVP Waveforms VOVP_HTH VOVP-LTH VUVLO-HTH VUVLO-LTH VIN BUCK Output Enable BUCK Output Disable LDO Output Enable LDO Output Disable Undefined Undefined 3.6 Thermal Shutdown When the junction temperature of the MVPG15x/MVPG16 exceeds 150C (typical), the thermal shutdown circuitry disables the step-down regulator. The step-down switching regulator is enabled when the junction temperature is decreased to 120C (typical). Doc. No. MV-S102809-00 Rev. G Page 30 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Functional Description Adaptive Transient Response 3.7 Adaptive Transient Response The MVPG15x/MVPG16 device's Smart Technology allows the step-down switching regulator to quickly respond to the multiple step loads and maintain stability over a wide range of applications. Figure 13shows an example of a second step-load applied while the output voltage of the step-down switching regulator increased due to the inductive kick from the first step-load. Condition: VIN = 5.0V, RSVIN = 10, CSVIN = 0.1 F, CPVIN = 10 F, L = 4.7 H, COUT(BUCK) = 10 F, ILOAD = 200 mA to 1.0A. Figure 13: Adaptive Transient Response VBUCK 100mV/DIV ILOAD 1A/DIV 20 s/DIV The overshoot (VSOAR) during a full-load to light-load transient due to stored inductor energy (Figure 13) can be calculated as: I LOAD ( MAX ) * L = -------------------------------------------2 * C OUT * V OUT 2 V SOAR Although the VSOAR cannot be eliminated, its amplitude can be controlled based on the COUT capacitor value. The appropriate COUT value can easily be calculated for the acceptable VSOAR level for each specific application. I LOAD ( MAX ) * L = -------------------------------------------2 * V SOAR * V OUT 2 C OUT Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 31 MVPG15x/MVPG16 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102809-00 Rev. G Page 32 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Functional Characteristics Startup Waveforms 4 4.1 Functional Characteristics The following applies unless otherwise noted: TA = 25C, RSVIN = 10, CSVIN = 0.1 F, CPVIN = 10 F, L = 4.7 H, COUT (BUCK) = 10 F, PFET = FDC642P, COUT (LDO) = 10 F. Startup Waveforms NOTE: There is a delay (3.5 ms typ.) before the output voltage turns on. Figure 14: Startup Using the Shutdown Pin Figure 15: Turn Off Using the Shutdown Pin VLDO 2V/DIV VLDO VBUCK 2V/DIV VBUCK VSHDN 500 mV/DIV 500 mV/DIV VSHDN 2V/DIV 2V/DIV 1.0 ms/DIV VIN = 5.0V VLDO= 3.3V VBUCK= 1.2V ILOAD = No Load tDLY~ 3.5 ms VIN = 5.0V VLDO= 3.3V VBUCK= 1.2V 1.0 ms/DIV ILOAD = No Load Figure 16: Enable Threshold at VIN = 3.5V Figure 17: Enable Threshold at VIN = 5.0V 2V/DIV VLDO VBUCK VSHDN 1V/DIV 1V/DIV VLDO VBUCK VSHDN 2V/DIV 1V/DIV 1V/DIV 100 ms/DIV VIN = 5.0V VLDO= 3.3V VBUCK= 1.2V ILOAD = 10 mA VTH = 0.96V (Note) VIN = 5.0V VLDO= 3.3V VBUCK= 1.2V 100 ms/DIV ILOAD = 10 mA VTH = 1.12V (Note) Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 33 MVPG15x/MVPG16 Datasheet Figure 18: Input Voltage Soft Start Figure 19: Input Voltage Hot Plug VIN VLDO 5V/DIV VIN VLDO 5V/DIV 2V/DIV 2V/DIV VBUCK 1V/DIV VBUCK 1V/DIV 2.0 ms/DIV VIN = 5.0V VLDO= 3.3V VBUCK= 1.2V ILOAD = No Load VIN = 5.0V VLDO= 3.3V 1.0 ms/DIV VBUCK= 1.2V ILOAD = No Load Figure 20: Step-Down Output Rise Time Figure 21: Soft Start Current Limit Steps VBUCK 500 mV/DIV IIND 500 mA/DIV IIND 500 mA/DIV 10 s/DIV VIN = 5.0V VBUCK= 1.2V ILOAD = 500 mA VIN = 5.0V VBUCK= 3.3V 50 s/DIV Doc. No. MV-S102809-00 Rev. G Page 34 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Functional Characteristics Startup Waveforms Figure 22: UVLO and OVP Thresholds 2V/DIV VIN VLDO VBUCK 2V/DIV 2V/DIV 100 ms/DIV VIN = 0 to 6.0V VLDO = 3.3V VBUCK = 1.5V ILOAD(BUCK) = 50 VUVLO(HTH) = 2.60V VUVLO(LTH) = 2.50V VOVP(HTH) = 5.8V VOVP(LTH) = 5.7V Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 35 MVPG15x/MVPG16 Datasheet 4.2 Switching Waveforms NOTE: For repeatability of measuring output ripple (VBUCK (P-P)) for the BUCK regulator, the standard test procedure limits the scope bandwidth to 20 MHz and uses a coax cable with very short leads terminated into 50. The coax leads must be routed away from the switching node as much as possible. Figure 23: Switching Waveforms-- PWM Mode VSW 5V/DIV VSW IIND 200 mA/DIV VBUCK VBUCK 5 mV/DIV IIND VIN 100 mV/DIV Figure 24: Switching Waveforms-- DCM Mode 5V/DIV 10 mV/DIV 500 mV/DIV 500 ns/DIV VIN = 5.0V VBUCK = 1.2V IOUT = 1.0A VOUT(P-P) = 4.9 mV (Note) VIN(P-P) = 200 mV IIND(P-P) = 231 mA IIND(PK) = 1.1A Freq = 910 kHz VIN = 5.0V VBUCK = 1.2V IOUT = 50 mA 1.0 s/DIV IIND(PK) = 248 mA Freq = 313 kHz VOUT(P-P) = 13 mV (Note) Figure 25: PWM Output Ripple Voltage Figure 26: Switching Waveforms-- DCM Mode-Zoom VSW VBUCK 10 mV/DIV VBUCK 5V/DIV 10 mV/DIV 200 mA/DIV IIND 100 ms/DIV VIN = 5.0V VBUCK = 1.2V IOUT = 1.0A VOUT(P-P) = 8.6 mV (Note) VIN = 5.0V VBUCK = 1.2V 500 ns/DIV IOUT = 24 mA Ringing Freq = 6.0 MHz Doc. No. MV-S102809-00 Rev. G Page 36 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Functional Characteristics Load Transient Waveforms 4.3 Load Transient Waveforms 4.3.1 Step-Down Regulator Figure 27: Load Transient Response Figure 28: Double-Pulsed Load Response VBUCK 100 mV/DIV VBUCK 100 mV/DIV ILOAD 1A/DIV ILOAD 1A/DIV 20 s/DIV VIN = 5.0V VBUCK = 1.2V COUT = 10 F ILOAD = 200 mA to 1.0A tRISE = 7.0A/s tFALL = 74A/s VIN = 5.0V VBUCK = 1.2V COUT = 10 F 20 s/DIV ILOAD = 200 mA to 1.0A tRISE = 7.0A/s tFALL = 74A/s Figure 29: Load Transient Response Figure 30: Double-Pulsed Load Response VBUCK 100 mV/DIV VBUCK 1A/DIV 100 mV/DIV ILOAD ILOAD 1A/DIV 20 s/DIV VIN = 5.0V VBUCK = 1.2V COUT = 2x10 F IOUT = 200 mA to 1.0A tRISE = 7.0A/s tFALL = 74A/s VIN = 5.0V VBUCK = 1.2V COUT = 2x10 F 20 s/DIV IOUT = 200 mA to 1.0A tRISE = 7.0A/s tFALL = 74A/s Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 37 MVPG15x/MVPG16 Datasheet Figure 31: Load Transient Response Figure 32: Double-Pulsed Load Response VBUCK 100 mV/DIV VBUCK 1A/DIV 100 mV/DIV ILOAD ILOAD 1A/DIV 20 s/DIV VIN = 5.0V VBUCK = 1.2V COUT = 4x10 F ILOAD = 200 mA to 1.0A tRISE = 7.0A/s tFALL = 74A/s VIN = 5.0V VBUCK = 1.2V COUT = 4x10 F 20 s/DIV ILOAD = 200 mA to 1.0A tRISE = 7.0A/s tFALL = 74A/s 4.3.2 LDO Regulator Figure 33: Load Transient Response VLDO 50 mV/DIV ILOAD 1A/DIV 20 s/DIV VIN = 5.0V VLDO = 3.3V COUT = 10 F ILOAD = 0.2 mA to 0.8A Doc. No. MV-S102809-00 Rev. G Page 38 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Typical Characteristics Efficiency Graphs 5 5.1 Typical Characteristics Efficiency Graphs Figure 34: Efficiency Graphs Efficiency vs. Output Current Vin = 5.0V 100 90 Efficiency (% ) 80 70 60 50 0 0.2 0.4 0.6 Output Current (A) 0.8 1 Efficiency (%) 100 90 80 70 60 50 0.01 Efficiency vs. Output Current Vin = 5.0V 3.3V 2.5V 1.8V 1.2V 1.0V 0.8V 3.3V 2.5V 1.8V 1.2V 1.0V 0.8V 0.1 Output Current (A) 1 Efficiency vs. Output Current Vin = 3.3V 100 90 Efficiency vs. Output Current Vin = 3.3V 100 90 Efficiency (%) 80 70 60 50 0.01 Efficiency (%) 80 70 60 50 0 0.2 0.4 0.6 Output Current (A) 0.8 1 3.3V 2.5V 1.8V 1.2V 1.0V 0.8V 2.5V 1.8V 1.2V 1.0V 0.8V 0.1 Output Current (A) 1 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 39 MVPG15x/MVPG16 Datasheet 5.2 Load Regulation Figure 35: Load Regulation Step-Down Regulator Step-Down Regulator Output Volatgevs. Output Current Output Voltage vs. Output Current Vout = 1.5V Vout = 1.5V 1.60 Output Voltage (V) Output Volatge (V) 1.55 1.50 1.45 1.40 0 0.2 0.4 0.6 Output Current (A) 0.8 1 3.3V 5.0V 5.3 Dropout Voltage Figure 36: Dropout Voltage Step-Down Regulator Dropout vs. Load Current Vin = 3.2V, Vout = 3.3V 0.3 TA=85C TA=25C TA=-40C LDO Regulator Dropout vs. Load Current Vin = 3.3V, Vout = 3.3V 0.20 TA=85C TA=25C TA=-40C 0.15 Dropout (V) Dropout (V) 0.2 0.10 0.1 0.05 0.0 0 0.2 0.4 0.6 Output Current (A) 0.8 1 0.00 0 0.2 0.4 Output Current (A) 0.6 0.8 Doc. No. MV-S102809-00 Rev. G Page 40 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Typical Characteristics RDS (ON) Resistance 5.4 RDS (ON) Resistance Figure 37: RDS (ON) Resistance Top FET Rds_On vs. Temperature 0.20 0.15 Rds_On () Rds_On () 0.10 0.05 0.00 -40 -20 0 20 40 60 80 Temperature (C) 3V 4V 5V 0.12 0.10 0.08 0.06 0.04 -40 -20 Bottom FET Rds_On vs. Temperature 3V 4V 5V 0 20 40 60 80 Temperature (C) Top FET Rds_On vs. Input Voltage 0.20 0.15 Rds_On () 0.10 0.05 TA = 25C 0.00 3.0 3.5 4.0 Input Voltage (V) 4.5 5.0 0.04 3.0 Rds_On () 0.12 0.10 0.08 0.06 Bottom FET Rds_On vs. Input Voltage TA = 25C 3.5 4.0 Input Voltage(V) 4.5 5.0 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 41 MVPG15x/MVPG16 Datasheet 5.5 IC Case and Inductor Temperature The following data was taken using a 0.625 square inch and L = 4.7 H. Actual results depend upon the size of the PCB proximity to other heat emitting components. Figure 38: IC Case and Inductor Temperature Input Current vs. Output Current Vin = 5V, TA = 25C 1.00 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 1.00 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V Input Current vs. Output Current Vin = 3.3V, TA = 25C Input Current (A) 0.50 Input Current (A) 0.75 0.75 0.50 0.25 0.25 0.00 0 0.2 0.4 0.6 Output Current (A) 0.8 1 0.00 0 0.2 0.4 0.6 Output Current (A) 0.8 1 IC Case Temperature vs. Output Current Vin = 5V, TA = 25C 40 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 40 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V IC Case Temperature vs. Output Current Vin = 3.3V, TA = 25C IC Temperature (C) 32 IC Temperature (C) 36 36 32 28 28 24 0 0.2 0.4 0.6 Output Current (A) 0.8 1 24 0 0.2 0.4 0.6 Output Current (A) 0.8 1 Inductor Temperature vs. Output Current Vin = 5V, TA = 25C 36 Inductor Temperature vs. Output Current Vin = 3.3V, TA = 25C 36 L Temperature (C) L Temperature (C) 32 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 0 0.2 0.4 0.6 Output Current (A) 0.8 1 32 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 0 0.2 0.4 0.6 Output Current (A) 0.8 1 28 28 24 24 20 20 Doc. No. MV-S102809-00 Rev. G Page 42 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Typical Characteristics Input Voltage Graph 5.6 Input Voltage Graph Figure 39: Supply Current vs. Input Voltage Supply Current vs. Input Voltage 4.0 Supply Current (mA) 3.0 2.0 1.0 0.0 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 Load = No Load 5.6.1 Step-Down Regulator Figure 41: Efficiency vs. Input Voltage Efficiency vs. Input Voltage 100% Figure 40: Output Voltage vs. Input Voltage Output Voltage vs. Input Voltage 1.60 Output Voltage (V) 1.55 Efficiency (%) 95% 1.50 90% 1.45 85% 1.40 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 80% 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 IOUT(BUCK) = 250 mA VIN = 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 500 mA Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 43 MVPG15x/MVPG16 Datasheet Figure 42: Load Regulation vs. Input Voltage Load Regulation vs. Input Voltage 0.20% Figure 43: Frequency vs. Input Voltage Frequency vs. Input Voltage 2000 Load Regulation (%) Frequency (kHz) 0.10% 1500 0.00% 1000 -0.10% 500 -0.20% 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 0 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 VIN = 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 250 mA to 1.0A IOUT(BUCK) = 500 mA Figure 44: Average Output Current Limit vs. Input Voltage Anerage Output Current Limit vs. Input Voltage Average Output Current Limit vs. Input Voltage 4.0 Current Limit (A) 3.0 2.0 1.0 0.0 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 Doc. No. MV-S102809-00 Rev. G Page 44 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Typical Characteristics Input Voltage Graph 5.6.2 LDO Regulator Figure 46: LDO Load Regulation vs. Input Voltage LDO Load Regulation vs. Input Voltage 0.40% Figure 45: Output Voltage vs. Input Voltage Output Voltage vs. Input Voltage 3.60 Output Voltage (V) 3.40 Load Regulation (%) 0.30% 3.20 0.20% 3.00 0.10% 2.80 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 0.00% 4.0 4.5 5.0 Input Voltage (V) 5.5 IOUT(LDO) = 10 mA VOUT(LDO) = 3.3V IOUT(LDO) = 10 mA to 800 mA Figure 47: Average Output Current Limit vs. Input Voltage Average Output Current Limit vs. Input Voltage 2.0 Current Limit (A) 1.5 1.0 0.5 0.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 45 MVPG15x/MVPG16 Datasheet 5.7 Temperature Graphs Figure 49: UVLO vs. Temperature UVLO vs. Temperature 3.0 Figure 48: Supply Current vs. Temperature Supply Current vs. Temperature 4.0 Supply Current (mA) 3.0 UVLO (V) 2.9 2.0 2.8 1.0 2.7 0.0 -40 -20 0 20 40 Temperature (C) 60 80 2.6 -40 -20 0 20 40 60 80 Temperature (C) IOUT(BUCK) = No Load IOUT(LDO) = No Load IOUT(BUCK) = 10 mA 5.7.1 Step-Down Regulator Figure 51: Efficiency vs. Temperature Efficiency vs. Temperature 100% Figure 50: Output Voltage vs. Temperature Output Voltage vs. Temperature 1.60 Output Voltage (V) 1.55 95% Efficiency (%) -40 -20 0 20 40 Temperature (C) 60 80 1.50 90% 1.45 85% 1.40 80% -40 -20 0 20 40 Temperature (C) 60 80 VIN = 5.0V IOUT(BUCK) = 250 mA VIN = 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 500 mA Doc. No. MV-S102809-00 Rev. G Page 46 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Typical Characteristics Temperature Graphs Figure 52: Load Regulation vs. Temperature Load Regulation vs. Temperature See Test Conditions 0.60% 0.50% 0.40% 0.30% 0.20% 0.10% 0.00% -40 Figure 53: Line Regulation vs. Temperature Line Regulation vs. Temperature See Test Conditions 0.20% 0.10% 0.00% -0.10% -20 0 20 40 60 80 Temperature (C) -0.20% -40 -20 0 20 40 60 80 Temperature (C) VIN = 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 250 mA to 1.0A VIN = 3.0V to 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 250 mA Figure 54: Average Output Current Limit vs. Temperature Average Output Current Limit vs. Temperature 3 Figure 55: Frequency vs. Temperature Frequency vs. Temperature 2000 Current Limit (A) 2 Frequency (kHz) 1500 1000 1 500 0 0 -40 -20 0 20 40 Temperature (C) 60 80 -40 -20 0 20 40 Temperature (C) 60 80 VIN = 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 500 mA Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 47 MVPG15x/MVPG16 Datasheet 5.7.2 LDO Regulator Figure 57: Load Regulation vs. Temperature Load Regulation vs. Temperature 0.20% Figure 56: Output Voltage vs. Temperature Output Voltage vs. Temperature 3.40 Output Voltage (V) 3.35 Load Regulation (%) -40 -20 0 20 40 Temperature (C) 60 80 0.15% 3.30 0.10% 3.25 0.05% 3.20 0.00% -40 -20 0 20 40 Temperature (C) 60 80 VIN = 5.0V IOUT(LDO) = 10 mA VIN = 5.0V VOUT(LDO) = 3.3V IOUT(LDO) = 10 mA to 800 mA Figure 58: Line Regulation vs. Temperature Line Regulation vs. Temperature See Test Conditions 0.20% 0.10% 0.00% -0.10% -0.20% -40 Figure 59: Average Output Current Limit vs. Temperature Average Ouput Current Limit vs. Temperature 2.0 Current Limit (A) -20 0 20 40 60 80 Temperature (C) 1.5 1.0 0.5 0.0 -40 -20 0 20 40 Temperature (C) 60 80 VIN = 3.5V to 5.0V VOUT(LDO) = 3.3V IOUT(LDO) = 10 mA VIN = 5.0V Doc. No. MV-S102809-00 Rev. G Page 48 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines 6 6.1 Applications Information PC Board Layout Considerations and Guidelines To avoid noise and abnormal operating behavior, follow these layout recommendations. Warning This is a 2-layer board with one ground plane and one routing layer. Copy the routing layer in Figure 64 or Figure 65 as much as possible and place it on the top layer. The ground plane in Figure 66 or Figure 67 can be placed on any other layer. Use the recommend BOM in Table 11 or Table 12. Contact the factory where substitutions are made. 3. Review the recommended solder pad layout and notes in Section 7.3, Typical Pad Layout Dimensions, on page 59. 4. Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor in placed next to the IC. If Tantalum input capacitor is used, it must be rated for switching regulator applications and the operating voltage be derated by 50%. 5. Use either X7R or X5R type ceramic capacitors. If Y5V or Z5U type capacitor are used, then you must double the recommended capacitance value. 6. Any type of capacitor can be placed in parallel with the output capacitor. 7. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide the lowest noise and smallest foot print solution. 8. Use planes for the ground, input and outputs power to maintain good voltage filtering and to keep power losses low. 9. If there is not enough space for a power plane for the input supply, then the input supply trace must be at least 3/8 inch wide. 10. If there is not enough space for a power plane for the output supplies, then place the output as close to the load as possible with a trace of at least 3/8 inch wide. 11. Do not lay out the inductor first. The input capacitor placement is the most critical for proper operation. The AC current circulating through the input capacitor and loop 1 (LP1) are square wave with rise and fall times of 8 ns and slew rates as high as 300 A/s (see Figure 60). At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3.0V per inch of PCB trace, VIND = L * di/dt. Therefore, the Ceramic input capacitor must be place as close as possible to the PVIN and PGND pins with as short and wide trace as possible. Also, the PVIN and PGND traces must be placed on the top layer. This will isolate the fast AC currents from interfering with the analog ground plane. 12. The MVPG15x/MVPG16 has two internal grounds, analog (SGND) and power (PGND). The analog ground ties to all the noise sensitive signals (PSET, VSET, and SVIN) while the power ground ties to the higher current power paths. Noise on an analog ground can cause problems with the IC's internal control and bias signals. For this reason, separate analog and power ground traces are recommended. The signal ground is connected to the power ground at one point, which is the (-) terminal of the output capacitor. 1. 2. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 49 MVPG15x/MVPG16 Datasheet 13. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as shown in Figure 60 or Figure 61, is recommended for best results. 14. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle. 15. Try not to route analog or digital lines in close proximity to the power supply especially the VSW node. If this can't be avoided, shield these lines with a power plane placed between the VSW node and the signal lines. 16. The type of solder paste recommended for QFN packages is "No clean", due to the difficulty of cleaning flux residues from beneath the QFN package. Figure 60: MVPG15x PCB Layout Schematic VIN R1 47m ohm MVPG15 1 2 3 FDC642P 4 5 6 U2 3 5 2 6 1 L1 4.7uH C2 BUC K_OUT 10uF/6.3V 4 LFB ILIM LDR SGND SFB SW U1 PGN D PSET VSET 12 11 10 9 8 7 R3 10ohm C4 0.1uF R2 R4 MVPG15 SHDN NC SVIN PVIN EP LP1 C3 LDO_OU T 10uF/6.3V C1 10uF/6.3V VIN Figure 61: MVPG16 PCB Layout Schematic U1 1 2 3 4 5 6 L1 4.7uH C2 BUC K__OU T 10uF/6.3V NC NC NC SGND SFB SW MVPG16 PSET VSET 12 11 10 9 8 7 R2 R3 MVPG16 SHDN NC PGN D SVIN PVIN C3 0.1uF R1 10 ohm EP LP1 C1 10uF/6.3V Doc. No. MV-S102809-00 Rev. G Page 50 Document Classification: Proprietary VIN Copyright (c) 2008 Marvell April 14, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines 6.1.1 PC Board Layout Examples for MVPG15x/MVPG16 For the MVPG15x: Actual board size = 565 mil x 945 mil; Area = 0.534 Sq. Inches. Total copper layers = 2 (Top and Bottom) All the components are on the top layer For the MVPG16: Actual board size = 420 mil x 725 mil; Area = 0.305 Sq. Inches. Total copper layers = 2 (Top and Bottom) All the components are on the top layer Figure 62: Top Silk-Screen (Not to scale)--MVPG15x Figure 63: Top Silk-Screen (Not to scale)--MVPG16 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 51 MVPG15x/MVPG16 Datasheet Figure 64: Top Traces, Vias, and Copper (Not to scale)--MVPG15x Connect the input voltage plane to this point. Connect the LDO regulator output voltage at this point. Connect the ground plane of the board to this point. Connect the Buck regulator output voltage at this point. Connect the ground plane of the board to this point. Figure 65: Top Traces, Vias, and Copper (Not to scale)--MVPG16 Do not connect this signal ground to the board ground on the top layer. Do not connect this signal ground to the board ground on the top layer. Connect BUCK_OUT trace at this point. Connect the ground plane of the board to this point. Connect VIN trace at this point. Doc. No. MV-S102809-00 Rev. G Page 52 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines Figure 66: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale)--MVPG15x Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board. Figure 67: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale)--MVPG16 Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 53 MVPG15x/MVPG16 Datasheet 6.2 Bill of Materials The following tables list the components used with the MVPG15x/MVPG16. Table 11: MVPG15x BOM It e m Qty Ref Manufacturer Part No. MVPG15B Manufacturer D e s c r ip t i o n 1 1 U1 Marvell Semiconductor Fairchild Taiyo-Yuden 1 MHz, 1.5A Peak Current-Limit Step-Down Regulator with LDO regulator controller P-FET, 2.5V, SuperSOT-6 package 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic 4.7 H, 1.59A (typ.), 55 m (typ.), H = 2mm, L = 6.2 mm, W = 6.3 mm 0.047, 1/4W, 5%, 0805 Case Size See Section 3.2, Output Voltage--AnyVoltageTM Technology, on page 26. 2 3 1 1 U2 C1 FDC642P CE JMK212 BJ106MG-T 4 C2012X5R0J106MT TDK 5 1 C2 CE JMK212 BJ106MG-T Taiyo-Yuden 6 C2012X5R0J106MT TDK 7 1 C3 CE JMK212 BJ106MG-T Taiyo-Yuden 8 C2012X5R0J106MT TDK 9 1 C4 RM LMK105 BJ104KV-F Taiyo-Yuden 10 C1005X5R1A104K TDK 11 1 L1 A918CY-4R7M=P3 Toko 12 13 1 1 R1 R2 RL1220T-R047-J Susumu Co. Ltd. 14 15 1 1 R3 R4 ERJ-2RKF10R0X Panasonic-ECG 10, 1/16W, 1%, 0402 Case Size See Section 3.2, Output Voltage--AnyVoltageTM Technology, on page 26. Doc. No. MV-S102809-00 Rev. G Page 54 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Applications Information Bill of Materials Table 12: MVPG16 BOM It e m Qty Ref Manufacturer Part No. MVPG16 Manufacturer D e s c r ip t i o n 1 1 U1 Marvell Semiconductor Taiyo-Yuden 1 MHz, 1.5A Peak Current-Limit Step-Down Regulator 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic 4.7 H, 1.59A (typ.), 55 m (typ.), H = 2mm, L = 6.2 mm, W = 6.3 mm 10, 1/16W, 1%, 0402 Case Size See Section 3.2, Output Voltage--AnyVoltageTM Technology, on page 26. See Section 3.2, Output Voltage--AnyVoltageTM Technology, on page 26. 2 1 C1 CE JMK212 BJ106MG-T 3 C2012X5R0J106MT TDK 4 1 C2 CE JMK212 BJ106MG-T Taiyo-Yuden 5 C2012X5R0J106MT TDK 6 1 C3 CE JMK212 BJ106MG-T Taiyo-Yuden 7 C2012X5R0J106MT TDK 8 1 C4 RM LMK105 BJ104KV-F Taiyo-Yuden 9 C1005X5R1A104K TDK 10 1 L1 A918CY-4R7M=P3 Toko 11 12 1 1 R1 R2 ERJ-2RKF10R0X Panasonic-ECG 13 1 R4 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 55 MVPG15x/MVPG16 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102809-00 Rev. G Page 56 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Mechanical Drawing Mechanical Drawing 7 7.1 Mechanical Drawing Mechanical Drawing Figure 68: Mechanical Drawing Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 57 MVPG15x/MVPG16 Datasheet 7.2 Sy m b o l Dimensions D i m e n s io ns i n m m MIN NOM 0.90 0.02 0.20 REF 0.18 0.51 2.90 1.60 3.90 3.40 0.23 0.56 3.00 1.70 4.00 3.50 0.50 BSC 0.30 ---0.40 ---0.50 0.15 0.10 0.10 0.012 ---0.28 0.61 3.10 1.80 4.10 3.60 0.007 0.020 0.114 0.063 0.153 0.134 MAX 1.00 0.05 D i m e n s io n s i n in c h MIN 0.031 0.000 NOM 0.035 0.001 0.008 REF 0.009 0.022 0.118 0.067 0.157 0.138 0.020 BSC 0.016 ---0.020 0.006 0.004 0.004 0.011 0.024 0.122 0.071 0.161 0.142 MAX 0.039 0.002 Table 13: Dimensions A A1 A2 b1 b2 D D1 E E1 e L aaa bbb ccc 0.80 0.00 Doc. No. MV-S102809-00 Rev. G Page 58 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Mechanical Drawing Typical Pad Layout Dimensions 7.3 7.3.1 Typical Pad Layout Dimensions Recommended Solder Pad Layout Figure 69: Recommended Solder Pad Layout Package Outline 0.55 0.23 0.50 0.075 4.00 3.50 0.56 1.75 0.67 0.83 1.60 2.20 3.30 4x3 DFN-12 Land Pattern (mm) 0.50 mm 0.23 mm Pad SM Pad SM 0.27 mm Pad 0.051 mm 0.168 mm DFN Lead with Non-Solder Mask Defined Terminal Note Top view Drawing not to scale Dimensions are in millimeters Exposed pad shall be copper plated Oversize solder mask by 0.102 mm (4 mils) over pad size (0.051 mm annular ring) 0.168 mm solder mask (sm) between pads Tolerance 0.05 mm Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 59 MVPG15x/MVPG16 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102809-00 Rev. G Page 60 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Part Order Numbering/Package Marking Part Order Numbering 8 8.1 Part Order Numbering/Package Marking Part Order Numbering Figure 70 shows the part order numbering scheme for the MVPG15x/MVPG16. Refer to Marvell Field Applications Engineers (FAEs) or representatives for further information when ordering parts. Figure 70: Sample Part Order Number MVPG1x x-xx-xxx1C000-xxxx Part Numbers MVPG15 MVPG16 LDO Output Voltage Options B = 3.3V E = 2.5V Custom Code Custom Code (optional) Custom Code Temperature Code C = Commercial I = Industrial Package Code NAE = 12-pin DFN Environmental Code + = RoHS 0/6 - = RoHS 5/6 1 = RoHS 6/6 Table 14: Part Order Options P a c k a g e Ty p e M a r k in g LDO Ambient Te m p e r a t u r e Range -40C to 85C -40C to 85C -40C to 85C Part Order Number 4 mm x 3 mm 12-pin DFN 4 mm x 3 mm 12-pin DFN 4 mm x 3 mm 12-pin DFN B0 E0 00 3.3V 2.5V -- MVPG15B-XX-NAE1C000 MVPG15E-xx-NAE1C000 MVPG16-xx-NAE1C000 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 61 MVPG15x/MVPG16 Datasheet 8.2 Package Marking This section show the sample package markings and pin 1 location. Figure 71: MVPG15x Package Marking Marvell logo Part number, LDO options, custom code, assembly house code G15 = Part number B0 = LDO output voltage options (B or E) A2 = Custom code R = Assembly house code Date code, traceability lot code YWW = Date code (Y = year, WW = Work Week) AA = Traceability lot code G15 B0A2R YWWAA Pin 1 Note: The above drawing is not drawn to scale. Location of markings is approximate. Doc. No. MV-S102809-00 Rev. G Page 62 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 Part Order Numbering/Package Marking Package Marking Figure 72: MVPG16 Package Marking Marvell logo Part number, LDO option, custom code, assembly house code G16 = Part number 00 = No LDO output voltage option A2 = Custom code R = Assembly house code Date code, traceability lot code YWW = Date code (Y = year, WW = Work Week) AA = Traceability lot code G16 00A2R YWWAA Pin 1 Note: The above drawing is not drawn to scale. Location of markings is approximate. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 63 MVPG15x/MVPG16 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102809-00 Rev. G Page 64 Document Classification: Proprietary Copyright (c) 2008 Marvell April 14, 2008, 2.00 A Release Revision History Table 15: Revision History D o c um en t Ty p e D o c u m e n t R e v i s io n Rev.G Electrical Specifications Updated VUVLO values in Table 5, Electrical Characteristics, on page 19 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Document Classification: Proprietary Doc. No. MV-S102809-00 Rev. G Page 65 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster |
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