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19-4626; Rev 0; 5/09
KIT ATION EVALU ABLE AVAIL
Low-Jitter, Precision Clock Generator with Three Outputs
General Description Features
Crystal Oscillator Interface: 24.8MHz to 27MHz CMOS Input: Up to 320MHz Output Frequencies Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz 10G Fibre Channel: 159.375MHz, 318.75MHz Low Jitter 0.14psRMS (1.875MHz to 20MHz) 0.36psRMS (12kHz to 20MHz) Excellent Power-Supply Noise Rejection No External Loop Filter Capacitor Required
MAX3625A
The MAX3625A is a low-jitter, precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet, 10G Fibre Channel, and other networking applications. Maxim's proprietary PLL design features ultra-low jitter and excellent power-supply noise rejection, minimizing design risk for network equipment. The MAX3625A has three LVPECL outputs. Selectable output dividers and a selectable feedback divider allow a range of output frequencies.
Applications
Ethernet Networking Equipment Fibre Channel Storage Area Network
Pin Configuration and Typical Application Circuit appear at end of data sheet.
PART MAX3625ACUG+
Ordering Information
TEMP RANGE 0C to +70C PIN-PACKAGE 24 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Block Diagram
IN_SEL MR BYPASS SELA[1:0]
SELA[1:0] SELB[1:0] FB_SEL BYPASS
QA_OE RESET LOGIC/POR RESET DIVIDER NA LVPECL BUFFER QA QA
RESET LVCMOS REF_IN 27pF X_IN CRYSTAL OSCILLATOR X_OUT 33pF DIVIDERS: M = 24, 25 NA = 10, 2, 4, 5 NB = 10, 2, 4, 5 LVPECL BUFFER QB0 QB0 DIVIDER M DIVIDER NB 1 0 PFD FILTER RESET 620MHz TO 648MHz VCO 1 RESET LVPECL BUFFER QB1 QB1 QB_OE 0
MAX3625A
FB_SEL
SELB[1:0]
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Jitter, Precision Clock Generator with Three Outputs MAX3625A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range VCC, VCCA, VCCO_A, VCCO_B ..............................................-0.3V to +4.0V Voltage Range at REF_IN, IN_SEL, FB_SEL, SELA[1:0], SELB[1:0], QA_OE, QB_OE, MR, BYPASS ..............-0.3V to (VCC + 0.3V) Voltage Range at X_IN Pin ...................................-0.3V to +1.2V Voltage Range at X_OUT Pin ......................-0.3V to (VCC - 0.6V) Current into QA, QA, QB0, QB0, QB1, QB1 .....................-56mA Continuous Power Dissipation (TA = +70C) 24-Pin TSSOP (derate 13.9mW/C above +70C) .....1111mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-65C to +160C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER Power-Supply Current (Note 4) SYMBOL ICC IN_SEL = high IN_SEL = low CONDITIONS MIN TYP 72 74 MAX 98 UNITS mA
CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR, BYPASS Pins) Input Capacitance Input Pulldown Resistor Input Logic Bias Resistor Input Pullup Resistor CIN RPULLDOWN Pins MR, FB_SEL RBIAS RPULLUP Pins SELA[1:0], SELB[1:0] Pins QA_OE, QB_OE, IN_SEL, BYPASS VCC 1.13 VCC 1.85 (Note 2) 20% to 80% (Note 2) PLL enabled PLL bypassed (Note 5) 0.6 200 48 45 2 75 50 75 VCC 0.98 VCC 1.7 0.72 350 50 50 VCC 0.83 VCC 1.55 0.9 600 52 55 pF k k k
LVPECL OUTPUTS (QA, QA, QB0, QB0, QB1, QB1 Pins) Output High Voltage Output Low Voltage Peak-to-Peak Output-Voltage Swing (Single-Ended) Clock Output Rise/Fall Time Output Duty-Cycle Distortion VOH VOL V V VP-P ps %
LVCMOS/LVTTL INPUTS (SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR, BYPASS Pins) Input-Voltage High Input-Voltage Low Input High Current Input Low Current VIH VIL I IH I IL VIN = VCC VIN = 0V -80 2.0 0.8 80 V V A A
2
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Low-Jitter, Precision Clock Generator with Three Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL PLL enabled PLL bypassed VIH VIL I IH I IL VIN = VCC VIN = 0V PLL enabled -240 30 2.5 620 RJRMS 12kHz to 20MHz 1.875MHz to 20MHz (Notes 6, 7, and 8) (Notes 6, 8, and 9) 0.36 0.14 5.6 -54 -70 Between any output pair f = 1kHz Clock Output SSB Phase Noise at 125MHz (Note 10) f = 10kHz f = 100kHz f = 1MHz f > 10MHz 5 -124 -127 -131 -145 -153 dBc/Hz 648 1.0 70 2.0 0.8 240 CONDITIONS MIN 24.8 TYP MAX 27.0 320 UNITS
MAX3625A
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled) Reference Clock Frequency Input-Voltage High Input-Voltage Low Input High Current Input Low Current Reference Clock Duty Cycle Input Capacitance CLOCK OUTPUT AC SPECIFICATIONS VCO Frequency Range Random Jitter (Note 6) Deterministic Jitter Induced by Power-Supply Noise Spurs Induced by Power-Supply Noise Nonharmonic and Subharmonic Spurs Output Skew MHz psRMS psP-P dBc dBc ps MHz V V A A % pF
A series resistor of up to 10.5 is allowed between VCC and VCCA for filtering supply noise when system power-supply tolerance is VCC = 3.3V 5%. See Figure 1. Note 2: LVPECL outputs guaranteed up to 320MHz. Note 3: Measured using setup shown in Figure 1. Note 4: All outputs enabled and unloaded. Note 5: Measured with a crystal (see Table 4) or an AC-coupled, 50% duty-cycle signal on REF_IN. Note 6: Measured with crystal source, see Table 4. Note 7: Measured with Agilent DSO81304A 40GS/s real-time oscilloscope. Note 8: Measured with 40mVP-P, 100kHz sinusoidal signal on the supply. Note 9: Measured at 156.25MHz output. Note 10: Measured with 25MHz crystal or 25MHz reference clock at REF_IN with a slew rate of 0.5V/ns or greater. Note 1:
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Low-Jitter, Precision Clock Generator with Three Outputs MAX3625A
Typical Operating Characteristics
(Typical values are at VCC = +3.3V, TA = +25C, crystal frequency = 25MHz.)
SUPPLY CURRENT vs. TEMPERATURE
225 200 SUPPLY CURRENT (mA) 175 150 125 100 75 50 25 0 0 10 20 30 40 50 60 70 1ns/div AMBIENT TEMPERATURE (C) ALL OUTPUTS ACTIVE AND UNTERMINATED ALL OUTPUTS ACTIVE AND TERMINATED
MAX3625A toc01
DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz
MAX3625A toc02
PHASE NOISE AT 312.5MHz CLOCK FREQUENCY
-90 -100 -110 -120 -130 -140 -150 -160 0.1 1 10 100 1000 10,000 100,000 OFFSET FREQUENCY (kHz)
MAX3625A toc03
250
-80 NOISE POWER DENSITY (dBc/Hz)
AMPLITUDE (200mv/div)
PHASE NOISE AT 125MHz CLOCK FREQUENCY
MAX3625A toc04
PHASE NOISE AT 156.25MHz CLOCK FREQUENCY
-90 NOISE POWER DENSITY (dBc/Hz) -100
MAX3625A toc05
JITTER HISTOGRAM (312.5MHz OUTPUT, 40mVP-P SUPPLY NOISE AT 100kHz)
MAX3625A toc06
-80 NOISE POWER DENSITY (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 0.1 1 10 100
-80
DJ = 5.6psP-P -110 -120 -130 -140 -150 -160 DJ + RJ = 14psP-P 0.1 1 10 100 1000 10,000 100,000 5ps/div
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY
-10 -20 SPUR POWER (dBc) -30 -40 -50 -60 -70 -80 -90 10 100 1000 10,000 NOISE FREQUENCY (kHz) fC = 312.5MHz NOISE AMPLITUDE = 40mVP-P
MAX3625A toc07
0
4
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Low-Jitter, Precision Clock Generator with Three Outputs
Pin Description
PIN 1, 24 NAME SELB0, SELB1 BYPASS FUNCTION LVCMOS/LVTTL Inputs. Control NB divider setting. Has 50k information. input impedance. See Table 2 for more
MAX3625A
2
LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high or leave open for normal operation. When in bypass mode the output dividers are set to divide by 1. Has internal 75k pullup to VCC. LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1s to reset all dividers. Has internal 75k pulldown to GND. Not required for normal operation. Power Supply for QA Clock Output. Connect to +3.3V. Noninverting Clock Output, LVPECL Inverting Clock Output, LVPECL LVCMOS/LVTTL Input. Enables/disables QB clock outputs. Connect pin high or leave open to enable LVPECL clock outputs QB0 and QB1. Connect low to set QB0 and QB1 to a logic 0. Has internal 75k pullup to VCC. LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high or leave open to enable the LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75k pullup to VCC. LVCMOS/LVTTL Input. Controls M divider setting. See Table 3 for more information. Has internal 75k pulldown to GND. Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can connect to VCC through 10.5 as shown in Figure 1 (requires VCC = 3.3V 5%). Core Power Supply. Connect to +3.3V. LVCMOS/LVTTL Inputs. Control NA divider setting. See Table 2 for more information. 50k impedance. Supply Ground Crystal Oscillator Output Crystal Oscillator Input LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling. LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN. Has internal 75k pullup to VCC. LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output Power Supply for QB0 and QB1 Clock Output. Connect to +3.3V. input
3 4 5 6 7
MR VCCO_A QA QA QB_OE
8
QA_OE
9 10 11 12, 13 14 15 16 17 18 19 20 21 22 23
FB_SEL VCCA VCC SELA0, SELA1 GND X_OUT X_IN REF_IN IN_SEL QB1 QB1 QB0 QB0 VCCO_B
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Low-Jitter, Precision Clock Generator with Three Outputs MAX3625A
Detailed Description
The MAX3625A is a low-jitter clock generator designed to operate at Ethernet and Fibre Channel frequencies. It consists of an on-chip crystal oscillator, PLL, programmable dividers, and LVPECL output buffers. Using a low-frequency clock (crystal or CMOS input) as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance.
Applications Information
Power-Supply Filtering
The MAX3625A is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. In addition to excellent on-chip power-supply noise rejection, the MAX3625A provides a separate powersupply pin, VCCA, for the VCO circuitry. Figure 1 illustrates the recommended power-supply filter network for V CCA . The purpose of this design technique is to ensure a clean power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. This network requires that the power supply is +3.3V 5%. Decoupling capacitors should be used on all supply pins for best performance.
Crystal Oscillator
An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between X_IN and X_OUT. The crystal frequency is 24.8MHz to 27MHz.
REF_IN Buffer
An LVCMOS-compatible clock source can be connected to REF_IN to serve as the reference clock. The LVCMOS REF_IN buffer is internally biased to the threshold voltage (1.4V typ) to allow AC- or DC-coupling, and is designed to operate up to 320MHz.
Output Divider Configuration
Table 2 shows the input settings required to set the output dividers. Note that when the MAX3625A is in bypass mode (BYPASS set low), the output dividers are automatically set to divide by 1.
PLL
The PLL takes the signal from the crystal oscillator or reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO) with a 620MHz to 648MHz operating range. The VCO is connected to the PFD input through a feedback divider. See Table 3 for divider values. The PFD compares the reference frequency to the divided-down VCO output (fVCO/M) and generates a control signal that keeps the VCO locked to the reference clock. The high-frequency VCO output clock is sent to the output dividers. To minimize noise-induced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies.
PLL Divider Configuration
Table 3 shows the input settings required to set the PLL feedback divider.
Crystal Selection
The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 4 for recommended crystal specifications. See Figure 3 for external capacitance connection.
Crystal Input Layout
The crystal, trace, and two external capacitors should be placed on the board as close as possible to the MAX3625A's X_IN and X_OUT pins to reduce crosstalk of active signals into the oscillator. The example layout shown in Figure 2 gives approximately 3pF of trace plus footprint capacitance per side of the crystal. The dielectric material is FR-4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C10 = 27pF and C9 = 33pF, the measured output frequency accuracy is -14ppm at +25C ambient temperature.
+3.3V 5% VCC 0.01F 10.5 VCCA 0.01F 10F
Output Dividers
The output dividers are programmable to allow a range of output frequencies. See Table 2 for the divider input settings. The output dividers are automatically set to divide by 1 when the MAX3625A is in bypass mode (BYPASS = 0).
LVPECL Drivers
The high-frequency outputs--QA, QB0, and QB1--are differential PECL buffers designed to drive transmission lines terminated with 50 to VCC - 2.0V. The maximum operating frequency is specified up to 320MHz. The outputs can be disabled, if not used. The outputs go to a logic 0 when disabled.
Reset Logic/POR
During power-on, a power-on reset (POR) signal is generated to synchronize all dividers. An external master reset (MR) signal is not required.
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Figure 1. Analog Supply Filtering
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Low-Jitter, Precision Clock Generator with Three Outputs MAX3625A
Table 1. Output Frequency Determination
CRYSTAL OR CMOS INPUT FREQUENCY (MHz) FEEDBACK DIVIDER, M VCO FREQUENCY (MHz) OUTPUT DIVIDER, NA AND NB 2 25 25 625 4 5 10 25.78125 25 644.53125 4 2 26.04166 24 625 4 5 10 26.5625 24 637.5 2 4 OUTPUT FREQUENCY (MHz) 312.5 156.25 125 62.5 161.132812 312.5 156.25 125 62.5 318.75 159.375 10G Fibre Channel Ethernet 10Gbps Ethernet Ethernet APPLICATIONS
Table 2. Output Divider Configuration
INPUT SELA1/SELB1 0 0 1 1 SELA0/SELB0 0 1 0 1 NA/NB DIVIDER /10 /2 /4 /5
Table 3. PLL Divider Configuration
FB_SEL INPUT 0 1 M DIVIDER /25 /24
Figure 2. Crystal Layout
Table 4. Crystal Selection Parameters
PARAMETER Crystal Oscillation Frequency Shunt Capacitance Load Capacitance Equivalent Series Resistance (ESR) Maximum Crystal Drive Level SYMBOL f OSC CO CL RS MIN 24.8 2.0 18 50 300 W TYP MAX 27 7.0 UNITS MHz pF pF
33pF CRYSTAL (CL = 18pF) X_OUT 27pF X_IN
Figure 3. Crystal, Capacitors Connection
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Low-Jitter, Precision Clock Generator with Three Outputs MAX3625A
+3.3V VB = 1.4V 130 130 VCC Z0 = 50 Z0 = 50 82 82 HIGH IMPEDANCE VB VCC
MAX3625A Qx
Qx
14.5k REF_IN VB
Figure 4. Thevenin Equivalent of Standard PECL Termination
ESD STRUCTURES 0.1F Qx Z0 = 50 100 0.1F Qx 150 150 Z0 = 50 HIGH IMPEDANCE VCC
Figure 6. Simplified REF_IN Pin Circuit Schematic
MAX3625A
NOTE: AC-COUPLING IS OPTIONAL.
Qx
Figure 5. AC-Coupled PECL Termination
Qx
Interfacing with LVPECL Outputs
The equivalent LVPECL output circuit is given in Figure 7. These outputs are designed to drive a pair of 50 transmission lines terminated with 50 to VTT = VCC - 2V. If a separate termination voltage (VTT) is not available, other terminations methods can be used such as shown in Figures 4 and 5. Unused outputs should be disabled and may be left open. For more information on LVPECL terminations and how to interface with other logic families, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML.
ESD STRUCTURES
Figure 7. Simplified LVPECL Output Circuit Schematic
Interface Models
Figures 6 and 7 show examples of interface models.
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Low-Jitter, Precision Clock Generator with Three Outputs
Layout Considerations
The inputs and outputs are critical paths for the MAX3625A, and care should be taken to minimize discontinuities on these transmission lines. Here are some suggestions for maximizing the MAX3625A's performance: * An uninterrupted ground plane should be positioned beneath the clock I/Os. * Supply and ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3625A and the receive devices. * Supply decoupling capacitors should be placed close to the MAX3625A supply pins. * Maintain 100 differential (or 50 single-ended) transmission line impedance out of the MAX3625A. * Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3625A Evaluation Kit for more information.
Pin Configuration
TOP VIEW
SELB0 1 BYPASS 2 MR 3 VCCO_A 4 QA 5 QA 6 QB_OE 7 QA_OE 8 FB_SEL 9 VCCA 10 VCC 11 SELA0 12 24 SELB1 23 VCCO_B 22 QB0 21 QB0 20 QB1 19 QB1
MAX3625A
MAX3625A
18 IN_SEL 17 REF_IN 16 X_IN 15 X_OUT 14 GND 13 SELA1
TSSOP
Chip Information
TRANSISTOR COUNT: 10,840 PROCESS: BiCMOS
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Low-Jitter, Precision Clock Generator with Three Outputs MAX3625A
Typical Application Circuit
+3.3V 5% 10.5 0.01F 0.1F
10F
VCC VCCA 0.01F REF_IN
VCCO_A
VCCO_B QA QA 312.5MHz 150 Z0 = 50
0.1F ASIC Z0 = 50 0.1F 150
IN_SEL FB_SEL QA_OE VCC QB_OE BYPASS SELA0 SELB1 SELB0 SELA1 MR X_OUT X_IN GND QB1 QB1 Z0 = 50 QB0 Z0 = 50
0.1F
MAX3625A
ASIC QB0 Z0 = 50 156.25MHz 150 0.1F 150
0.1F ASIC Z0 = 50 156.25MHz 150 0.1F 150
26.0416MHz (CL = 18pF) 33pF 27pF
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 24 TSSOP PACKAGE CODE U24-1 DOCUMENT NO. 21-0066
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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