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19-2828; Rev 4; 10/07
Programmable DC-Balanced 21-Bit Serializers
General Description
The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializer and deserializer using AC-coupling. The DC balance circuits on each channel code the data, limiting the imbalance of transmitted ones and zeros to a defined range. The companion MAX9210/MAX9214 deserializers decode the data. When DC balance is not programmed, the serializers are compatible with non-DC-balanced, 21-bit serializers such as the DS90CR215 and DS90CR217. Two frequency ranges and two DC-balance default conditions are available for maximum replacement flexibility and compatibility with existing non-DC-balanced serializers. The MAX9209/MAX9213 are available in TSSOP and space-saving thin QFN packages.
Features
Programmable DC-Balanced or Non-DC-Balanced Operation DC Balance Allows AC-Coupling for Ground-Shift Tolerance As Low as 8MHz Operation Pin Compatible with DS90CR215 and DS90CR217 in Non-DC-Balanced Mode Integrated 110 (DC-Balanced) and 410 (NonDC-Balanced) Output Resistors 5V Tolerant LVTTL/LVCMOS Data Inputs PLL Requires No External Components Up to 1.785Gbps Throughput LVDS Outputs Meet IEC 61000-4-2 and ISO 10605 Requirements LVDS Outputs Conform to ANSI TIA/EIA-644 LVDS Standard Low-Profile 48-Lead TSSOP and Space-Saving QFN Packages -40C to +85C Operating Temperature Range +3.3V Supply
MAX9209/MAX9213
Applications
Automotive Navigation Systems Automotive DVD Entertainment Systems Digital Copiers Laser Printers
Functional Diagram
PART MAX9209ETM*
MAX9209 MAX9213
TxIN 0 - 20 TIMING CONTROL 21 PARALLEL-TOSERIAL CONVERTER AND DC-BALANCE LOGIC TxOUT0LVDS DRIVER 1 TxOUT1+ TxOUT1LVDS DRIVER 2 TxOUT2+ TxOUT2LVDS CLK TxCLK OUT+ TxCLK IN PLL 7X OR 9X CLOCK GENERATOR TxCLK OUT-
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C -40C to +105C -40C to +85C -40C to +85C PIN-PACKAGE 48 Thin QFN-EP** 48 TSSOP 48 TSSOP 48 Thin QFN-EP** 48 TSSOP
MAX9209EUM
LVDS DRIVER 0 TxOUT0+
MAX9209GUM MAX9213ETM MAX9213EUM
*Future product--contact factory for availability. **EP = Exposed pad.
DCB/NC
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.5V to +4.0V LVDS Outputs (TxOUT_, TxCLK OUT_) to GND ...-0.5V to +4.0V 5V Tolerant LVTTL/LVCMOS Inputs (TxIN_, TxCLK IN, PWRDWN) to GND ..............-0.5V to +6.0V (DCB/NC) to GND ......................................-0.5V to (VCC + 0.5V) LVDS Outputs (TxOUT_, TxCLK OUT_) Short to GND and Differential Short .......................Continuous Continuous Power Dissipation (TA = +70C) 48-Pin TSSOP (derate 16mW/C above +70C) ....... 1282mW 48-Lead QFN (derate 26.3mW/C above +70C) ......2105mW Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) All Pins to GND..............................................................2kV IEC 61000-4-2 (RD = 330, CS = 150pF) Contact Discharge (TxOUT_, TxCLK OUT_) to GND ....8kV Air Gap Discharge (TxOUT_, TxCLK OUT_) to GND ..15kV ISO 10605 (RD = 2k, CS = 330pF) Contact Discharge (TxOUT_, TxCLK OUT_) to GND ....8kV Air Gap Discharge (TxOUT_, TxCLK OUT_) to GND ..25kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS TxIN_, TxCLK IN, PWRDWN High-Level Input Voltage Low-Level Input Voltage Input Current Input Clamp Voltage Differential Output Voltage Change in VOD Between Complementary Output States Output Offset Voltage Change in VOS Between Complementary Output States VIH VIL IIN VCL VOD VOD VOS VOS VIN = high or low, PWRDWN = high or low ICL = -18mA Figure 1 Figure 1 Figure 1 Figure 1 VOUT+ or VOUT- = 0V or VCC, non-DC-balanced mode VOUT+ or VOUT- = 0V or VCC, DC-balanced mode VOD = 0V, non-DC-balanced mode (Note 3) VOD = 0V, DC-balanced mode (Note 3) DC-balanced mode Differential Output Resistance RO Non-DC-balanced mode 78 -40C to +105C -40C to +105C 78 292 292 -10 -15 1.125 250 DCB/NC MIN 2.0 2.0 -0.3 -20 -0.9 350 2 1.25 10 5.7 8.2 5.7 8.2 110 110 410 410 TYP MAX 5.5 VCC + 0.3 +0.8 +20 -1.5 450 25 1.375 30 +10 mA +15 10 15 147 150 547 564 V V A V mV mV V mV UNITS
SINGLE-ENDED INPUTS (TxIN_, TxCLK IN, PWRDWN, DCB/NC)
LVDS OUTPUTS (TxOUT_, TxCLK OUT)
Output Short-Circuit Current
IOS
Magnitude of Differential Output Short-Circuit Current
IOSD
mA
2
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Programmable DC-Balanced 21-Bit Serializers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100 1%, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 1, 2)
PARAMETER Output High-Impedance Current SYMBOL IOZ CONDITIONS PWRDWN = low or VCC = 0V, VOUT+ = 0V or 3.6V, VOUT- = 0V or 3.6V 8MHz MAX9209 16MHz MAX9209 DC-balanced mode, worst-case pattern, CL = 5pF, Figure 2 34MHz MAX9209 16MHz MAX9213 34MHz MAX9213 66MHz MAX9213 10MHz MAX9209 Worst-Case Supply Current ICCW 20MHz MAX9209 33MHz MAX9209 Non-DC-balanced mode, worst-case pattern, CL = 5pF, Figure 2 40MHz MAX9209 20MHz MAX9213 33MHz MAX9213 40MHz MAX9213 66MHz MAX9213 85MHz MAX9213 Power-Down Supply Current ICCZ PWRDWN = low MIN -0.5 TYP 0.1 40 48 71 46 59 94 30 37 49 56 36 45 49 68 83 17 MAX +0.5 54 68 90 64 87 108 39 53 70 75 49 62 70 89 100 50 A mA UNITS A
MAX9209/MAX9213
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Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, CL = 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 4, 5)
PARAMETER LVDS Low-to-High Transition Time LVDS High-to-Low Transition Time TxCLK IN Transition Time SYMBOL LLHT LHLT TCIT Figure 3 Figure 3 Figure 4 10MHz MAX9209 20MHz MAX9209 N = 0, 1, 2, 3, 4, 5, 6 non-DCbalanced mode, Figure 5 (Note 6) 40MHz MAX9209 20MHz MAX9213 40MHz MAX9213 85MHz MAX9213 Output Pulse Position TPPosN 8MHz MAX9209 16MHz MAX9209 N = 0, 1, 2, 3, 4, 5, 6, 7, 8 DC-balanced mode, Figure 6 (Note 6) 34MHz MAX9209 16MHz MAX9213 34MHz MAX9213 66MHz MAX9213 N/9 x TCIP N/9 x TCIP N/9 x TCIP + 0.25 - 0.25 N/9 x TCIP N/9 x TCIP N/9 x TCIP + 0.15 - 0.15 N/9 x TCIP N/9 x TCIP N/9 x TCIP + 0.1 - 0.1 N/9 x TCIP N/9 x TCIP N/9 x TCIP + 0.25 - 0.25 N/9 x TCIP N/9 x TCIP N/9 x TCIP + 0.15 - 0.15 N/9 x TCIP N/9 x TCIP N/9 x TCIP - 0.1 + 0.1 CONDITIONS MAX9209 MAX9213 MAX9209 MAX9213 MIN 150 150 150 150 TYP 280 260 280 260 MAX 400 350 400 350 4 N/7 x TCIP N/7 x TCIP N/7 x TCIP - 0.25 + 0.25 N/7 x TCIP N/7 x TCIP N/7 x TCIP - 0.15 + 0.15 N/7 x TCIP N/7 x TCIP N/7 x TCIP - 0.1 + 0.1 N/7 x TCIP N/7 x TCIP N/7 x TCIP - 0.25 + 0.25 N/7 x TCIP N/7 x TCIP N/7 x TCIP - 0.15 + 0.15 N/7 x TCIP N/7 x TCIP N/7 x TCIP + 0.1 - 0.1 ns UNITS ps ps ns
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Programmable DC-Balanced 21-Bit Serializers
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100 1%, CL = 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Notes 4, 5)
PARAMETER TxCLK IN High Time TxCLK IN Low Time TxIN to TxCLK IN Setup TxIN to TxCLK IN Hold TxCLK IN to TxCLK OUT Delay Serializer Phase-Locked Loop Set Serializer Power-Down Delay TxCLK IN Cycle-to-Cycle Jitter (Input Clock Requirement) Magnitude of Differential Output Voltage SYMBOL TCIH TCIL TSTC THTC TCCD TPLLS TPDD TJIT VOD 595Mbps data rate, worst-case pattern 250 CONDITIONS Figure 7 Figure 7 Figure 7 Figure 7 Non-DC-balanced mode, Figure 8 DC-balanced mode, Figure 8 Figure 9 Figure 10 14 MIN 0.3 x TCIP 0.3 x TCIP 2.2 0 3.5 4.7 4.5 5.9 6.0 7.2 32800 x TCIP 50 2 TYP MAX UNITS 0.7 x TCIP ns 0.7 x TCIP ns ns ns ns ns ns ns mV
MAX9209/MAX9213
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VOD , VOD, and VOS. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: Guaranteed by design. Note 4: TCIP is the period of TxCLK IN. Note 5: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma. Note 6: Pulse position TPPosN is characterized using 27 - 1 PRBS data.
Typical Operating Characteristics
(VCC = +3.3V, RL = 100 1%, CL = 5pF, PWRDWN = high, TA = +25C, unless otherwise noted.)
WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY
MAX9209 toc01
WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY
MAX9209 toc02
WORST-CASE AND PRBS SUPPLY CURRENT vs. FREQUENCY
MAX9213 NON-DC-BALANCED MODE
MAX9209 toc03
100
MAX9209 DC-BALANCED MODE
100
120
MAX9209 NON-DC-BALANCED MODE
SUPPLY CURRENT (mA)
WORST-CASE PATTERN 60
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
80
100
80 WORST-CASE PATTERN
80
60
WORST-CASE PATTERN
60 27 - 1 PRBS
40
27 - 1 PRBS
40
27 - 1 PRBS
40
20 0 10 20 30 40 50 FREQUENCY (MHz)
20 0 10 20 30 40 50 60 FREQUENCY (MHz)
20 15 30 45 60 75 90 FREQUENCY (MHz)
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Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100 1%, CL = 5pF, PWRDWN = high, TA = +25C, unless otherwise noted.)
WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY
MAX9209 toc04
MAX9213 EYE DIAGRAM--NON-DC-BALANCED MODE
MAX9209 TOC05
MAX9213 EYE DIAGRAM--NON-DC-BALANCED MODE
TxCLK IN = 85MHz DC-COUPLED 5m OF CAT-5 UTP CABLE
MAX9209 TOC06
120
MAX9213 DC-BALANCED MODE
TxCLK IN = 85MHz DC-COUPLED
2m OF CAT-5 UTP CABLE
100 SUPPLY CURRENT (mA) WORST-CASE PATTERN
80
100mV/div 60 27 - 1 PRBS 40 ALL-CHANNELS SWITCHING 15 30 45 FREQUENCY (MHz) 60 75 27 - 1 PRBS PATTERN 100 TERMINATION 300ps/div 0V DIFFERENTIAL
100mV/div 0V DIFFERENTIAL
20
ALL-CHANNELS SWITCHING
27 - 1 PRBS PATTERN 100 TERMINATION 300ps/div
MAX9213 EYE DIAGRAM--NON-DC-BALANCED MODE
MAX9209 TOC07
MAX9213 EYE DIAGRAM--DC-BALANCED MODE
TxCLK IN = 66MHz AC-COUPLED USING 0.1F CAPACITORS 2m OF CAT-5 UTP CABLE
MAX9209 TOC08 MAX9209 TOC10
TxCLK IN = 85MHz DC-COUPLED
10m OF CAT-5 UTP CABLE
100mV/div
0V DIFFERENTIAL
100mV/div
0V DIFFERENTIAL
ALL-CHANNELS SWITCHING
27 - 1 PRBS PATTERN 100 TERMINATION 300ps/div
ALL-CHANNELS SWITCHING
27 - 1 PRBS PATTERN 100 TERMINATION 300ps/div
MAX9213 EYE DIAGRAM--DC-BALANCED MODE
MAX9209 TOC09
MAX9213 EYE DIAGRAM--DC-BALANCED MODE
TxCLK IN = 66MHz AC-COUPLED USING 0.1F CAPACITORS 10m OF CAT-5 UTP CABLE
TxCLK IN = 66MHz AC-COUPLED USING 0.1F CAPACITORS
5m OF CAT-5 UTP CABLE
100mV/div 0V DIFFERENTIAL
100mV/div
0V DIFFERENTIAL
ALL-CHANNELS SWITCHING
27 - 1 PRBS PATTERN 100 TERMINATION 300ps/div
ALL-CHANNELS SWITCHING
27 - 1 PRBS PATTERN 100 TERMINATION 300ps/div
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Programmable DC-Balanced 21-Bit Serializers
Pin Description
PIN TSSOP 1, 3, 4, 44, 45, 47, 48, 2, 8, 14, 21 5, 11, 17, 24, 46 6, 7, 9, 10, 12, 13, 15 16, 18, 19, 20, 22, 23, 25 26 QFN 38, 39, 41, 42, 43, 45, 46 2, 8, 15, 44 5, 11, 18, 40, 47 1, 3, 4, 6, 7, 9, 48 10, 12, 13, 14, 16, 17, 19 20 NAME TxIN0-TxIN6 VCC GND TxIN7-TxIN13 TxIN14-TxIN20 TxCLK IN FUNCTION 5V Tolerant LVTTL/LVCMOS Channel 0 Data Inputs. Internally pulled down to GND. Digital Supply Voltage Ground 5V Tolerant LVTTL/LVCMOS Channel 1 Data Inputs. Internally pulled down to GND. 5V Tolerant LVTTL/LVCMOS Channel 2 Data Inputs. Internally pulled down to GND. 5V Tolerant LVTTL/LVCMOS Parallel Rate Clock Input. Internally pulled down to GND. 5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs are high impedance when PWRDWN = low or open. PLL Ground PLL Supply Voltage LVDS Ground Noninverting LVDS Parallel Rate Clock Output Inverting LVDS Parallel Rate Clock Output Noninverting Channel 2 LVDS Serial Data Output Inverting Channel 2 LVDS Serial Data Output LVDS Supply Voltage Noninverting Channel 1 LVDS Serial Data Output Inverting Channel 1 LVDS Serial Data Output Noninverting Channel 0 LVDS Serial Data Output Inverting Channel 0 LVDS Serial Data Output LVTTL/LVCMOS DC-Balance Programming Input: MAX9209: pulled up to VCC MAX9213: pulled up to VCC See Table 1. Exposed Paddle. Solder to ground.
MAX9209/MAX9213
27 28, 30 29 31, 36, 42 32 33 34 35 37 38 39 40 41
21 22, 24 23 25, 30, 36 26 27 28 29 31 32 33 34 35
PWRDWN PLL GND PLL VCC LVDS GND TxCLK OUT+ TxCLK OUTTxOUT2+ TxOUT2LVDS VCC TxOUT1+ TxOUT1TxOUT0+ TxOUT0-
43
37
DCB/NC
--
EP
EP
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Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
TxOUT_- OR TxCLK OUTTxOUT_+ OR TxCLK OUT+ VOS = |VOS(+) - VOS(-)| VOD(+) VOD(-) (TxOUT_+) - (TxOUT_-) OR (TxCLK OUT+) - (TxCLK OUT-) VOD = |VOD(+) - VOD(-)| 0V VOD(-) VOS(-) VOS(+) VOS(-)
Figure 1. LVDS Output DC Parameters
TCIP TxCLK IN
ODD TxIN EVEN TxIN
Figure 2. Worst-Case Test Pattern
TxOUT_+ OR TxCLK OUT+
80% RL (TxOUT_+) - (TxOUT_-) OR (TxCLK OUT+) - (TxCLK OUT-) 20% LLHT
80%
20% LHLT
TxOUT_- OR TxCLK OUT-
CL
CL
Figure 3. LVDS Output Load and Transition Times
VIH 90% 90%
10% TxCLK IN TCIT TCIT
10%
VIL
Figure 4. Clock Transition Time Waveform 8 _______________________________________________________________________________________
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
TxCLK OUT (DIFFERENTIAL) CYCLE N - 1 CYCLE N
TxOUT2 (SINGLE ENDED)
TxIN15
TxIN14
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxOUT1 (SINGLE ENDED)
TxIN8
TxIN7
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxOUT0 (SINGLE ENDED)
TxIN1
TxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6
Figure 5. Non-DC-Balanced Mode LVDS Output Pulse Position Measurement
Detailed Description
The MAX9209 operates at a parallel clock frequency of 8MHz to 34MHz in DC-balanced mode and 10MHz to 40MHz in non-DC-balanced mode. The MAX9213 operates at a parallel clock frequency of 16MHz to 66MHz in DC-balanced mode and 20MHz to 85MHz in nonDC-balanced mode. DC-balanced or non-DC-balanced operation is controlled by the DCB/NC pin (see Table 1). In non-DCbalanced mode, each channel serializes 7 bits every cycle of the parallel clock. In DC-balanced mode, 9 bits are serialized every clock cycle (7 data bits + 2 DC-balance bits). The highest data rate in DC-balanced mode for the MAX9213 is 66MHz x 9 = 594Mbps. In non-DCbalanced mode, the maximum data rate is 85MHz x 7 = 595Mbps. A bit time is 1 divided by the data rate, for example, 1 / 595Mbps = 1.68ns.
Table 1. DC-Balance Programming
DEVICE DCB/NC High or open MAX9209 Low High or open MAX9213 Low OPERATING MODE DC balanced Non-DC balanced DC balanced Non-DC balanced OPERATING FREQUENCY (MHz) 8 to 34 10 to 40 16 to 66 20 to 85
DC Balance
Through data coding, the DC-balance circuits limit the imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary one transmitted
and -1 is assigned to each binary zero transmitted, the variation in the running sum of assigned values is called the digital sum variation (DSV). The maximum DSV for the MAX9209/MAX9213 data channels is 10. At most, 10 more zeros than ones, or 10 more ones than zeros, are transmitted. The maximum DSV for the clock channel is 5. Limiting the DSV and choosing the correct coupling capacitors maintain differential signal amplitude and reduce jitter due to droop on AC-coupled links.
9
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Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
TxCLK OUT (DIFFERENTIAL) CYCLE N - 1 CYCLE N
TxOUT2 (SINGLE ENDED)
DCA2
DCB2
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
DCA2
DCB2
TxOUT1 (SINGLE ENDED)
DCA1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA1
DCB1
TxOUT0 (SINGLE ENDED)
DCA0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
DCA0
DCB0
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos7 TPPos8
Figure 6. DC-Balanced Mode LVDS Output Pulse Position Measurement
TCIP
TxCLK IN TCIH TCIL TSTC TxIN 0:20 1.5V SETUP THTC HOLD 1.5V
2.0V
1.5V
0.8V
Figure 7. Setup and Hold, High and Low Times
1.5V TxCLK IN TxCLK OUT+ TxCLK OUTTCCD DIFFERENTIAL 0
Figure 8. Clock-In to Clock-Out Delay 10 ______________________________________________________________________________________
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
2.0V PWRDWN 3.0V VCC TPPLS 3.6V
TxCLK IN TxOUT_, TxCLK OUT HIGH-Z VOD = 0 DIFFERENTIAL 0
Figure 9. PLL Set Time
PWRDWN 0.8V
TxCLK IN TPDD TxOUT_, TxCLK OUT HIGH-Z
Figure 10. Power-Down Delay
TxCLK OUT+
TxCLK OUTCYCLE N - 1 DCA2 TxOUT2 DCB2 TxIN20 TxIN19 TxIN18 CYCLE N TxIN17 TxIN16 TxIN15 TxIN14 DCA2 DCB2 TxIN20 TxIN19 TxIN18 CYCLE N + 1 TxIN17 TxIN16 TxIN15 TxIN14
DCA1 TxOUT1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA0 TxOUT0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
DCA0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs
To obtain DC balance on the data channels, the parallel input data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9210/ MAX9214 deserializers whether the data bits are inverted (Figure 11). The deserializer restores the original
state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9, which maintains DC balance. Figure 12 shows the non-DC-balanced mode inputs mapped to LVDS outputs.
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11
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
TxCLK OUT+
TxCLK OUTCYCLE N - 1 TxIN15 TxOUT2 TxIN8 TxOUT1 TxIN1 TxOUT0 TxIN0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 TxIN7 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN14 TxIN20 TxIN19 TxIN18 CYCLE N TxIN17 TxIN16 TxIN15 TxIN14 TxIN20 TxIN19 CYCLE N + 1 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs
MAX9209 MAX9213
TxOUT 7 7:1 RO
TRANSMISSION LINE RxIN
MAX9210 MAX9214
RT = 100
7 1:7
7 TxIN 7:1 RO RT = 100 1:7
7 RxOUT
7 7:1 RO
RT = 100
7 1:7
PWRDWN PLL TxCLK IN TxCLK OUT 21:3 SERIALIZER RO
RT = 100
PWRDWN PLL RxCLK OUT
RxCLK IN 3:21 DESERIALIZER
Figure 13. DC-Coupled Link, Non-DC-Balanced Mode
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be eliminated by increasing the receiver common-mode voltage range by AC-coupling. AC-coupling increases the common-mode voltage range of an LVDS receiver to nearly the voltage rating of the capacitor. The typical LVDS driver output is 350mV centered on an offset volt12
age of 1.25V, making single-ended output voltages of 1.425V and 1.075V. An LVDS receiver accepts signals from 0V to 2.4V, allowing approximately 1V commonmode difference between the driver and receiver on a DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V 0V = 1.075V). Figure 13 shows the DC-coupled link, non-DC-balanced mode.
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Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
HIGH-FREQUENCY CERAMIC SURFACE-MOUNT CAPACITORS CAN ALSO BE PLACED AT SERIALIZER INSTEAD OF DESERIALIZER. TxOUT RxIN
MAX9209 MAX9213
MAX9210 MAX9214
7 (7 + 2):1 RO
RT = 100
7 1:(9 - 2)
7 TxIN (7 + 2):1 RO
RT = 100
7 1:(9 - 2) RxOUT
7 (7 + 2):1 RO
RT = 100
7 1:(9 - 2)
PWRDWN PLL TxCLK IN RO
RT = 100
PWRDWN PLL RxCLK OUT
TxCLK OUT 21:3 SERIALIZER
RxCLK IN 3:21 DESERIALIZER
Figure 14. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
Common-mode voltage differences may be due to ground potential variation or common-mode noise. If there is more than 1V of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. AC-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. A common-mode voltage difference up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. DC-balanced coding of the data is required to maintain the differential signal amplitude and limit jitter on an AC-coupled link. A capacitor in series with each output of the LVDS driver is sufficient for AC-coupling. However,
two capacitors--one at the serializer output and one at the deserializer input--provide protection in case either end of the cable is shorted to a high voltage.
5V Tolerant Inputs
All signal and control inputs except DCB/NC are 5V tolerant and are internally pulled down to GND. The DCB/NC pin has a pullup on the MAX9209/MAX9213.
DCB/NC Pin Default Conditions
The MAX9209/MAX9213 have programmable DC balance/non-DC balance. See Table 1 for DCB/NC default settings and operating modes.
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Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
HIGH-FREQUENCY CERAMIC SURFACE-MOUNT CAPACITORS
MAX9209 MAX9213
MAX9210 MAX9214
RxIN
TxOUT
7 (7 + 2):1 RO
RT = 100
7 1:(9 - 2)
7 TxIN (7 + 2):1 RO
RT = 100
7 1:(9 - 2) RxOUT
7 (7 + 2):1 RO
RT = 100
7 1:(9 - 2)
PWRDWN PLL TxCLK IN RO
RT = 100
PWRDWN PLL RxCLK OUT
TxCLK OUT 21:3 SERIALIZER
RxCLK IN 3:21 DESERIALIZER
Figure 15. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (RT), the LVDS driver output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value series capacitors is (C x (RT + RO)) / 2 (Figure 14). The RC time constant for four equal-value series capacitors is (C x (RT + RO)) / 4 (Figure 15).
14
RT is required to match the transmission line impedance (usually 100) and RO is determined by the LVDS driver design, with a minimum value of 78 (see the DC Electrical Characteristics table). This leaves the capacitor selection to change the system time constant. In the following example, the capacitor value for a droop of 2% is calculated. Jitter due to this droop is then calculated assuming a 1ns transition time: C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1) where: C = AC-coupling capacitor (F) tB = bit time (s) DSV = digital sum variation (integer) ln = natural log D = droop (% of signal amplitude) RT = termination resistor ()
______________________________________________________________________________________
Programmable DC-Balanced 21-Bit Serializers
RO = output resistance () Equation 1 is for two series capacitors (Figure 14). The bit time (tB) is the period of the parallel clock divided by 9. The DSV is 10. See equation 3 for four series capacitors (Figure 15). The capacitor for 2% maximum droop at 8MHz parallel rate clock is: C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO)) C = -(2 x 13.9ns x 10) / (ln (1 - .02) x (100 + 78)) C = 0.0773F Jitter due to droop is proportional to the droop and transition time: tJ = tT x D (Eq 2) where: tJ = jitter (s) tT = transition time (s) (0% to 100%) D = droop (% of signal amplitude) Jitter due to 2% droop and assumed 1ns transition time is: tJ = 1ns x 0.02 tJ = 20ps The transition time in a real system depends on the frequency response of the cable driven by the serializer. The capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. Use high-frequency, surface-mount ceramic capacitors. Equation 1 altered for four series capacitors (Figure 15) is: C = -(4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3) to 50A or less. Driving PWRDWN high starts the PLL lock to the input clock and switches in the output termination resistors. The LVDS outputs are not driven until the PLL locks. The differential output resistance pulls the outputs together and the LVDS outputs are high impedance to ground. If the power supply is turned off, the output resistors are switched out and the LVDS outputs are high impedance.
MAX9209/MAX9213
PLL Lock Time
The PLL lock time is set by an internal counter. The maximum time to lock is 32,800 clock periods. Power and clock should be stable to meet the lock-time specification. When the PLL is locking, the LVDS outputs are not active and have a differential output resistance of RO.
Power-Supply Bypassing
There are separate power domains for LVDS, PLL, and digital circuits. Bypass each LVDS VCC, PLL VCC, and VCC pin with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVDS Outputs
The LVDS outputs are current sources. The voltage swing is proportional to the load impedance. The outputs are rated for a differential load of 100 1%.
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Integrated Termination
The MAX9209/MAX9213 have an integrated output termination resistor across each of the four LVDS outputs. These resistors damp reflections from induced noise and mismatches between the transmission line impedance and termination resistor at the deserializer input. In DCbalanced mode, the differential output resistance is part of the RC time constant. In non-DC-balanced mode, the output termination is increased to 410 (typ) to reduce power. In power-down mode (PWRDWN = low) or when the power supply is off, the output resistor is switched out and the LVDS outputs are high impedance.
Board Layout
Keep the LVTTL/LVCMOS input and LVDS output signals separated to prevent crosstalk. A four-layer PCB with separate layers for power, ground, LVDS outputs, and digital signals is recommended.
PWRDWN and Power-Off
Driving PWRDWN low stops the PLL, switches out the integrated output termination resistors, puts the LVDS outputs in high impedance, and reduces supply current
______________________________________________________________________________________
15
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
ESD Protection
The MAX9209/MAX9213 ESD tolerance is rated for IEC 61000-4-2, Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330 (Figure 16). For IEC 61000-4-2, the LVDS outputs are rated for 8kV contact and 15kV air discharge. The Human Body Model discharge components are CS = 100pF and RD = 1.5k (Figure 17). For the Human Body Model, all pins are rated for 2kV contact discharge. The ISO 10605 discharge components are CS = 330pF and RD = 2k (Figure 18). For ISO 10605, the LVDS outputs are rated for 8kV contact and 25kV air discharge.
50 TO 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 150pF
RD 330 DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE
1M CHARGE-CURRENTLIMIT RESISTOR CS 100pF
RD 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 17. Human Body ESD Test Circuit
50 TO 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 330pF
RD 2k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Figure 18. ISO 10605 Contact Discharge ESD Test Circuit
16
______________________________________________________________________________________
Programmable DC-Balanced 21-Bit Serializers
Pin Configurations
TOP VIEW
MAX9209/MAX9213
TxIN4 1 VCC 2 TxIN5 3 TxIN6 4 GND 5 TxIN7 6 TxIN8 7 VCC 8 TxIN9 9 TxIN10 10 GND 11 TxIN11 12 TxIN12 13 VCC 14 TxIN13 TxIN14 15 16
48 47 46 45 44 43 42 41
TxIN3 TxIN2 GND TxIN1 TxIN0 GND TxIN6 TxIN5 VCC DCB/NC
37 36 35 34 33 32 31 30 29 28 27
DCB/NC TxIN7 TxIN4 TxIN3 TxIN2 GND
43 42 41 40
LVDS GND TxOUT0TxOUT0+ TxOUT1TxOUT1+ LVDS VCC LVDS GND TxOUT2TxOUT2+ TxCLK OUTTxCLK OUT+ LVDS GND TxIN8 VCC TxIN9 TxIN10 GND TxIN11 TxIN12 VCC TxIN13 TxIN14 GND TxIN15
1 2 3 4 5 6 7 8 9 10 11 12
48
47
46
45
44
39
MAX9209 MAX9213
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
38
TxIN1 TxIN0
LVDS GND TxOUT0TxOUT0+ TxOUT1TxOUT1+ LVDS VCC LVDS GND TxOUT2TxOUT2+ TxCLK OUTTxCLK OUT+ LVDS GND
MAX9209 MAX9213
GND 17 TxIN15 18 TxIN16 19 TxIN17 20 VCC 21
EXPOSED PAD
26 25
13
14
15
16
17
18
19
20
21
22
23
PLL GND PLL VCC PLL GND PWRDWN TxCLK IN TxIN20
TxIN18 22 TxIN19 23
THIN QFN
GND 24
TSSOP
Chip Information
MAX9209 TRANSISTOR COUNT: 9458 MAX9213 TRANSISTOR COUNT: 9458 PROCESS: CMOS
______________________________________________________________________________________
TxCLK IN PWRDN PLL GND PLL VCC PLL GND
TxIN16
TxIN17 VCC TxIN18
TxIN19 GND TxIN20
24
17
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
48L TSSOP.EPS
E H
N
MARKING
AAA A
123
TOP VIEW
BOTTOM VIEW
SEE DETAIL A
b A1 A2 e D
SEATING PLANE
A
C L
c
END VIEW
SIDE VIEW
( )
PARTING LINE
b b1
WITH PLATING
0.25 L
DETAIL A
c1
BASE METAL
c
NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE. 3. CONTROLLING DIMENSION: MILLIMETERS. 4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED (48L), EE (56L). 5. "N" REFERS TO NUMBER OF LEADS. 6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE FROM (-C-) IN THE DIRECTION INDICATED. 7. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 8. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
SECTION C-C
PACKAGE OUTLINE, 48 & 56L TSSOP, 6.1mm BODY
21-0155
C
1 1
18
______________________________________________________________________________________
Programmable DC-Balanced 21-Bit Serializers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX9209/MAX9213
E E/2
DETAIL A
(NE-1) X e
k e D/2
D
(ND-1) X e
C L
D2
D2/2
b L E2/2 k
C L
E2
C L
C L
L e e
L
A1
A2
A
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
1
2
______________________________________________________________________________________
32, 44, 48L QFN.EPS
19
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
2
2
20
______________________________________________________________________________________
Programmable DC-Balanced 21-Bit Serializers MAX9209/MAX9213
REVISION NUMBER 3 4 REVISION DATE 6/07 10/07 -- Removed all references to MAX9211 and MAX9215. DESCRIPTION PAGES CHANGED 1-5, 9, 14, 15, 18, 19, 20 1-20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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