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SS8021 Stereo Headphone Power Amplifier FEATURES High performance Class AB amplifier High signal-to-noise ratio Low distortion Low power consumption Large output voltage swing Excellent power supply ripple rejection Supply voltage range of 3.0V to 6.5V Surface-mount package - SO-8 DESCRIPTION The SS8021 is an output-rail-to-rail stereo audio power amplifier housed in an 8-pin SOP package capable of delivering 125mW of continuous power into 16 loads and 75mW into 32 loads with THD <0.1% per channel. The gain of the amplifiers can be easily set with two external resistors - R I (input resistor) and RF (feedback resistor). The SS8021 is a dual channel, low voltage, low power, high performance amplifier. The quiescent current is typically 3mA at 5V. With excellent AC performance (small THD), it can be designed into a wide range of headphone driving applications. APPLICATIONS CD-ROM DVD-ROM CD-R/W MP3 Portable Stereo ORDERING INFORMATION SS8021(G)XX Packing: TR Tape and reel : TB Tubes This device is normally supplied with Pb-free lead finish (second-level interconnect) as SS8021G, but can be supplied with a traditional lead finish (SS8021) upon request. PIN CONFIGURATION SS8021 OUTA INA(neg) INA(pos) VSS 1 2 3 4 8 7 6 5 VDD OUTB INB(neg) INB(pos) SYMBOL OUTA INA(neg) INA(pos) VSS INB(pos) INB(neg) OUTB VDD PIN 1 2 3 4 5 6 7 8 DESCRIPTION output A inverting input A non-inverting input A negative supply non-inverting input B inverting input B output B positive supply 8/21/2004 Rev.2.01 www.SiliconStandard.com 1 of 8 SS8021 BLOCK DIAGRAM SS8021 OUTA INA(neg) INA(pos) 1 2 3 8 VDD _ _ 7 _ OUTB INB(neg) INB(pos) + + + 6 5 VSS 4 ABSOLUTE MAXIMUM RATINGS (Note1) SYMBOL VDD Tstg Tamb ESD PARAMETER Supply voltage Storage temperature Operating ambient temperature ESD voltage HBM CONDITION MIN 0 -65 -40 - MAX 7.0 +150 +85 2 UNIT V C C KV Notes: 1. Absolute Maximum Ratings are limits beyond which damage to the device may occur. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER Thermal resistance from junction to ambient in free air SO8 VALUE 240 UNIT C/W TEST AND APPLICATION INFORMATION VDD 3.9k 220F + RL 100k VOUTA 2.2F VINA 3.9k 1 2 3 _ + 8 + SS8021 VINB 2.2F 3.9k 6 _ _ 7 4 + + 3.9k 220F + 5 C6 100F 1F 100k VOUTB RL Fig.1 Measurement circuit for inverting application 8/21/2004 Rev.2.01 www.SiliconStandard.com 2 of 8 SS8021 ELECTRICAL CHARACTERISTICS VDD = 5V; VSS= 0V; TA = 25C; f I= 1kHz; RL = 32 connected to VDD/2; unless otherwise specified. SYMBOL Supplies VDD Supply voltage Single Dual VSS IDD Negative supply voltage Supply current no load no load 3.0 3.0 1.5 -1.5 -50 RL = 5k THD+N <0.1% closed-loop Sourcing current = 100mA Sinking current = 100mA fi = 1kHz; Vripple(rms) = 100mVrms RL=32 ,Cb=1F, PO=70mW note 2 open-loop; RL = 5k note 1; RL = 16 ; f=1kHz note 1; RL = 32 ; f=1kHz 0 60 5.0 5.0 2.5 -2.5 3.0 15 90 70 0.1 0.4 0.5 70 65 < 0.1 5 125 75 6.5 6.5 3.25 -3.25 5.0 25 50 3.5 1 1 V V V V mA mW mV V dB mA V V dB dB % MHz mW mW PARAMETER CONDITION MIN TYP MAX UNIT Ptot Total power dissipation DC Characteristics VI(OS) VCM GV IO RO VDD-VOH VOL-VSS PSRR Input offset voltage Common mode voltage Open-loop voltage gain Maximum output current Output resistance Output Voltage Swing High Output Voltage Swing Low Power supply rejection ratio CS Channel separation AC Characteristics THD fG PO Total harmonic distortion Unity gain frequency Maximum output power Notes: 1. Values are proportional to VDD; THD+N < 0.1% 2. VDD = 5.0V; VO(P-P) = 4.0V (at 0 dB) 8/21/2004 Rev.2.01 www.SiliconStandard.com 3 of 8 SS8021 Electrical Characteristics CIN=2.2F, COUT=330F, Cb=1F, Av=1, Ri=18k , Rf=18k ; Av=-2, Ri=18k , Rf=36k ; Av=-4, Ri=9k ,Rf=36k ,TA=25C THD+N vs Output Power 10 10 5 THD+N vs Frequency 5 2 VDD=5V RL=32 Av=-1 2 VDD=5V RL=32 Po=50mW Av=-4V/V Av=-2V/V 1 1 0.5 % 0.2 0.5 20kHz 0.1 % 0.2 0.1 0.05 1kHz 20Hz 2m 5m 10m W 20m 50m 100m 200m 0.05 0.02 0.02 Av=-1V/V 50 100 200 500 Hz 1k 2k 5k 10k 20k 0.01 1m 0.01 20 THD+N vs Frequency 10 10 5 5 THD+N vs Output Power VDD=5V RL=16 Av=-1 2 VDD=5V RL=32 Av=-1 2 1 1 0.5 % 0.2 % 0.5 20kHz 1kHz 0.2 0.1 Po=70mW 0.1 0.05 0.05 20Hz 0.02 Po=60mW 50 100 200 500 Hz 1k 2k 5k 10k 20k 0.02 0.01 20 0.01 2m 5m 10m 20m W 50m 100m 200m THD+N vs Frequency 10 10 5 THD+N vs Output Power 5 2 VDD=5V RL=16 Po=50mW Av=-4V/V Av=-2V/V % 2 VDD=3.3V RL=32 Av=-1 1 1 0.5 % 0.2 0.5 20kHz 0.2 0.1 0.1 1kHz 0.05 0.05 0.02 Av=-1V/V 50 100 200 500 Hz 1k 2k 5k 10k 20k 0.02 20Hz 2m 5m 10m W 20m 50m 100m 0.01 20 0.01 1m 8/21/2004 Rev.2.01 www.SiliconStandard.com 4 of 8 SS8021 ELECTRICAL CHARACTERISTICS (continued) THD+N vs Frequency 10 10 5 5 THD+N vs Output Power VDD=3.3V RL=16 Av=-1 20kHz 20Hz 2 VDD=3.3V RL=32 Po=25mW Av=-4V/V % 2 1 1 0.5 % 0.2 0.5 Av=-2V/V 0.2 0.1 0.1 0.05 0.05 1kHz 0.02 Av=-1V/V 50 100 200 500 Hz 1k 2k 5k 10k 20k 0.02 0.01 20 0.01 2m 3m 4m 5m 6m 7m 10m W 20m 30m 40m 50m 70m 100m THD+N vs Frequency 10 100u 90u 5 Output Noise 80u 70u 60u 50u 2 VDD=3.3V RL=16 Po=25mW Av=-4V/V Av=-2V/V V 1 VDD=5V RL=32 Av=-1 Cb=1F BW=20kHz , No filters 40u 0.5 % 0.2 30u 0.1 20u 0.05 A- Weighting Av=-1V/V 0.02 0.01 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 10u 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Channel Separation -20 -25 -30 -35 -40 -45 -50 -55 d B -60 -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k -110 -120 20 +0 -10 -20 -30 -40 Power Supply Rejection Ratio VDD=5V RL=32 Av=-1 Vripple=100mVrms Cb=1F Vpin 3,5=2.5V FORCED VDD=5V RL=32 Av=-1 Po=70mW Cb=1F Channel A to B d B -50 -60 -70 -80 -90 -100 Channel B to A 50 100 200 500 Hz 1k 2k 5k 10k 20k 8/21/2004 Rev.2.01 www.SiliconStandard.com 5 of 8 SS8021 ELECTRICAL CHARACTERISTICS (continued) Open Loop Frequency Response 8/21/2004 Rev.2.01 www.SiliconStandard.com 6 of 8 SS8021 ELECTRICAL CHARACTERISTICS (continued) Supply Current vs.Supply Voltage 2.6 2.4 Supply Current (mA) 2.2 2 1.8 1.6 1.4 1.2 1 2.5 3.5 4.5 5.5 Supply Voltage(V) 6.5 Supply Current (mA) Supply Current vs. Temperature 2.4 2.2 VDD=5V 2 1.8 1.6 1.4 1.2 1 -50 -25 0 25 50 75 Temperature (C) 100 125 VDD=3V Offset Voltage vs. Supply Voltage 5 4.8 Offset Voltage (mV) 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.5 3.5 4.5 5.5 Supply Voltage (V) 6.5 2 Offset Voltage (mV) 4.6 4.5 4 3.5 5 Offset Voltage vs.Temperature VDD=3V VDD=5V 3 2.5 -50 -25 0 25 50 75 Temperature (C) 100 125 Sinking Current vs. Vo-Vss 350 300 Sinking Current(mA) 250 200 150 100 50 0 0 0.5 1 1.5 2 VO-Vss(V) 2.5 3 VDD=3V VDD=5V Sourcing Current(mA) 350 300 Sourcing Current vs. VDD-Vo VDD=5V 250 200 VDD=3V 150 100 50 0 0 0.5 1 1.5 2 VDD - VO(V) 2.5 3 8/21/2004 Rev.2.01 www.SiliconStandard.com 7 of 8 SS8021 PHYSICAL DIMENSIONS C E H L D 7 (4X) 7 Taping Specification A2 A y A1 e B Feed Direction Typical SOP Package Orientation 1. Package body sizes exclude mold flash and gate burrs 2. Dimension L is measured in gage plane 3. Tolerance 0.10mm unless otherwise specified 4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact. SYMBOL A A1 A2 B C D E e H L y MIN. 1.35 0.10 ----0.33 0.19 4.80 3.80 ----5.80 0.40 ----0 DIMENSION IN MM NOM. 1.60 ----1.45 ----------------1.27 ----------------- MAX. 1.75 0.25 ----0.51 0.25 5.00 4.00 ----6.20 1.27 0.10 8 MIN. 0.053 0.004 ----0.013 0.007 0.189 0.150 ----0.228 0.016 ----0 DIMENSION IN INCH NOM. 0.063 ----0.057 ----------------0.050 ----------------- MAX. 0.069 0.010 ----0.020 0.010 0.197 0.157 ----0.244 0.050 0.004 8 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 8/21/2004 Rev.2.01 www.SiliconStandard.com 8 of 8 |
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