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A4986 DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Features and Benefits
Low RDS(ON) outputs Internal mixed current decay mode Synchronous rectification for low power dissipation Internal UVLO Crossover-current protection 3.3 and 5 V compatible logic supply Thin profile QFN and TSSOP packages Thermal shutdown circuitry Short-to-ground protection Shorted load protection Low current Sleep mode, < 10 A
Description
The A4986 is a dual DMOS full-bridge stepper motor driver with parallel input communication and overcurrent protection. Each full-bridge output is rated up to 35 V and 2 A. The A4986 includes fixed off-time pulse width modulation (PWM) current regulators, along with 2- bit nonlinear DACs (digital-to-analog converters) that allow stepper motors to be controlled in full, half, and quarter steps. The PWM current regulator uses the Allegro(R) patented mixed decay mode for reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation.
Package:
The outputs are protected from shorted load and short-toground events, which protect the driver and associated circuitry from thermal damage or flare-ups. Other protection features include thermal shutdown with hysteresis, undervoltage lockout (UVLO) and crossover current protection. Special power-up sequencing is not required. The A4986 is supplied in a 24-pin TSSOP (LP) with exposed thermal pad for enhanced thermal performance. It has a 0.65 pitch and an overall package height of 1.2 mm. It is lead (Pb) free, with 100% matte tin leadframe plating.
Approximate size
24-pin TSSOP with exposed thermal pad (LP Package)
Typical Application Diagram
VDD 0.22 F VREG ROSC VDD Microcontroller or Controller Logic CP1 CP2 VCP VBB1 VBB2 OUT1A SLEEP IN01 IN02 PH1 IN11 IN12 PH2 VREF GND GND OUT2A OUT2B SENSE2 100 F
0.1 F
0.1 F
0.22 F
A4986
OUT1B SENSE1
4986-DS
A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Selection Guide
Part Number A4986SLPTR-T Package 24-pin TSSOP with exposed thermal pad Packing 4000 pieces per 13-in. reel
Absolute Maximum Ratings
Characteristic Load Supply Voltage Output Current Logic Input Voltage Logic Supply Voltage VBBx to OUTx Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature VSENSE VREF TA TJ(max) Tstg Range S Symbol VBB IOUT VIN VDD Notes Rating 35 2 -0.3 to 5.5 -0.3 to 5.5 35 0.5 5.5 -20 to 85 150 -55 to 150 Units V A V V V V V C C C
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Functional Block Diagram
0.1 F
Rosc
VREG 0.22 F
REGULATOR OSC
CHARGE PUMP
VCP
CP1
CP2
0.1 F
DMOS FULL-BRIDGE 1
VBB1 Sense2
To VBB2
-
DAC
OSC
OCP +
OUT1A PWM Latch BLANKING Mixed Decay
VREF
OUT1B
VDD IN01 IN02 PH1 IN11 IN12 PH2 SLEEP CONTROL LOGIC
GATE DRIVE
SENSE1
DMOS FULL-BRIDGE 2
VBB2
OCP
OUT2A
PWM Latch BLANKING Mixed Decay
OSC
VCP VREG
VREG
OUT2B
REF
VREF Sense2 Sense2 GND GND SENSE2
-
+
VREF
DAC
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Symbol Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT = -1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = -1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled Sleep Mode fPWM < 50 kHz Outputs off Sleep Mode Min. 8 0 3.0 - - - - - - - - - - VDD0.7 VIN = VDD0.7 - -20 -20 - As a % of VDD OSC = VDD or GND ROSC = 25 k - 5 0.7 20 23 0 -3 - - - 100 2.1 - - 2.7 - Typ.2 - - - 320 320 - - - - - - - - - - <1.0 <1.0 100 50 11 1 30 30 - 0 - - - 475 - 165 15 2.8 90 Max. 35 35 5.5 430 430 1.3 1.3 4 2 10 8 5 10 - VDD0.3 20 20 - - 19 1.3 40 37 4 3 15 5 5 800 - - - 2.9 - Units V V V m m V V mA mA A mA mA A V V A A k k % s s s V A % % % ns A C C V mV
ELECTRICAL CHARACTERISTICS1 at TA = 25C, VBB = 35 V (unless otherwise noted)
Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage
VBB VDD RDSON VF IBB
Motor Supply Current
Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Logic Input Pull-down Logic Input Hysteresis Blank Time Fixed Off-Time Reference Input Voltage Range Reference Input Current Current Trip-Level Error3 Crossover Dead Time Protection Overcurrent Protection Threshold Thermal Shutdown Temperature Thermal Shutdown Hysteresis VDD Undervoltage Lockout VDD Undervoltage Hysteresis
1For 2Typical
IDD
VIN(1) VIN(0) IIN(1) IIN(0) RIN02 RIN12 VHYS(IN) tBLANK tOFF VREF IREF
errI
VIN = VDD0.3
VREF = 2 V, %ITripMAX = 33.3% VREF = 2 V, %ITripMAX = 66.7% VREF = 2 V, %ITripMAX = 100.00%
tDT IOCPST TTSD TTSDHYS VDDUVLO VDDUVLOHYS
VDD rising
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF/8) - VSENSE] / (VREF/8).
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic Package Thermal Resistance Symbol RJA Test Conditions* LP package; on 4-layer PCB, based on JEDEC standard Value Units 28 C/W
*In still air. Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, PD(max)
5.5 5.0 4.5 4.0
Power Dissipation, PD (W)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
(R
J
A
=
28
C
/W
)
20
40
60
80 100 120 Temperature (C)
140
160
180
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Functional Description
Device Operation. The A4986 is designed to operate one
stepper motor in full, half, or quarter step mode. The currents in each of the output full-bridges, all N-channel DMOS, are regulated with fixed off-time pulse width modulated (PWM) control circuitry. Each full-bridge peak current is set by the value of an external current sense resistor, RSx , and a reference voltage, VREFx . Percentages of the peak current are set using a 2-bit nonlinear DAC that programs 33%, 66%, or 100% of the peak current, or disables the outputs.
ROSC terminal. The ROSC terminal has two settings: ROSC tied to VDD or ground -- off-time internally set to 30 s ROSC through a resistor to ground -- off-time is determined by the following formula tOFF ROSC 825 Where tOFF is in s.
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (s), is approximately tBLANK 1 s
Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink FET outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off the sink and source FETs. The maximum value of current limiting is set by the selection of RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by ITripMAX = VREF / ( 8
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is shorted to ground, the driver will protect itself by sensing the overcurrent event and disabling the driver that is shorted, protecting the device from damage. In the case of a short-to-ground, the LEEP device will remain disabled (latched) until the S input goes high or VDD power is removed. A short-to-ground overcurrent event is shown in figure 1. When the two outputs are shorted together, the current path is through the sense resistor. After the blanking time (1 s) expires, the sense resistor voltage is exceeding its trip value, due to the overcurrent condition that exists. This causes the driver to go into a fixed off-time cycle. After the fixed off-time expires the driver turns on again and the process repeats. In this condition the driver is completely protected against overcurrent events, but the short is repetitive with a period equal to the fixed off-time of the driver. This condition is shown in figure 2. If the driver is operating in Mixed decay mode, it is normal for the positive current to spike, due to the bridge going in the forward direction and also in the negative direction, as a result of the direction change implemented by the Mixed decay feature. This is shown in figure 3. In both instances the overcurrent circuitry is protecting the driver and prevents damage to the device.
RS)
where RS is the resistance of the sense resistor () and VREF is the input voltage on the REF pin (V). The 2-bit DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX / 100)
x ITripMAX
It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The off-time, tOFF, is determined by the
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
5 A / div.
source-side FET gates. A 0.1 F ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 F ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side FET gates. Capacitor values should be Class 2 dielectric 15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications.
Fault latched
VREG (VREG). This internally-generated voltage is used to operate the sink-side FET outputs. The VREG pin must be decoupled with a 0.22 F ceramic capacitor to ground. VREG is internally monitored. In the case of a fault condition, the FET outputs of the A4986 are disabled. Capacitor values should be Class 2 dielectric 15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications.
t
Figure 1. Short-to-ground event
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the FET outputs of the A4986 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state.
5 A / div. Fixed off-time
Sleep Mode ( ). To minimize power consumption SLEEP when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A4986 into Sleep mode. When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a logic command.
t
Figure 2. Shorted load (OUTxA OUTxB) in Slow decay mode
Mixed Decay Operation. The bridge operates in Mixed
Decay mode, as shown in figures 5 through 7. As the trip point is reached, the A4986 initially goes into a fast decay mode for 31.25% of the off-time, tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. A timing diagram for this feature appears in figure 4.
5 A / div. Fixed off-time
Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed-off time cycle, load current recirculates in Mixed Decay mode. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET RDS(ON). This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Synchronous rectification turns off when the load current approaches zero (0 A), preventing reversal of the load current.
Fast decay portion (direction change) t
Figure 3. Shorted load (OUTxA OUTxB) in Mixed decay mode
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
7
A4986
VSTEP
100.00 70.71
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
See Enlargement A
IOUT
0
-70.71 -100.00
Enlargement A
toff IPEAK tFD tSD
Slow Decay
IOUT
Mixed Decay
Fa
st
De
ca
y
t
Symbol toff IPEAK tSD tFD IOUT Device fixed off-time Maximum output current Slow decay interval Fast decay interval Device output current Characteristic
Figure 4. Current Decay Modes Timing Chart
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Application Layout
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A4986 must be soldered directly onto the board. On the underside of the A4986 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the pad and the ground plane directly under the A4986, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal.
The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor (CIN2). This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. The sense resistors, RSx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. The SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits.
A4986
Solder Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.)
PCB Thermal Vias
OUT2B C3 U1 GND C5 ROSC C1 C4 C6 GND OUT2A R4 R5 OUT1A GND
GND
C3 C4 C5
CP1 CP2 VCP VREG INO2 IN12 IN11
A4986
GND PH2 OUT2B VBB2
PAD
SENSE2 OUT2A OUT1A SENSE1 VBB1 OUT1B PH1 GND
C6 R4
ROSC
BULK GND GND GND CAPACITANCE C2 VDD VBB GND OUT1B
ROSC SLEEP VDD IN01 REF
R5
C1
C2 VBB
VDD
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Pin Circuit Diagrams
VDD
VBB
VBB 40 V
VCP
CP1
CP2
8V GND GND
GND PGND GND 8V GND GND GND
VBB VREG SENSE DMOS Parasitic GND VREG
10 V GND
IN01 IN02 IN11 IN12 PH1 PH2 VREF ROSC SLEEP
VBB OUT DMOS Parasitic DMOS Parasitic GND GND
8V GND
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Step Sequencing Diagrams
100.0 66.7
100.0
66.7
Phase 1 (%)
0
Phase 1 (%)
0
-66.7 -66.7 -100.0 -100.0
100.0 66.7
100.0
66.7
Phase 2 (%)
0
Phase 2 (%)
0
-66.7 -66.7 -100.0 -100.0
Full step 2 phase Modified full step 2 phase
Half step 2 phase Modified half step 2 phase
Figure 5. Step Sequencing for Full-Step Increments.
Figure 6. Step Sequencing for Half-Step Increments.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4986
100.0
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
66.7
33.3
Phase 1 (%)
0
-33.3
-66.7
-100.0
100.0
66.7
33.3
Phase 2 (%)
0
-33.3
-66.7
-100.0
Figure 7. Step Sequence for Quarter-Step Increments
Step Sequencing Settings
Full 1/2 1 1/4 Phase 1 (%ITripMax) 0 33 100/66* 100 100 100 100/66* 33 0 33 100/66* 100 100 100 100/66* 33 I0x H L L/H* L L L L/H* L H L L/H* L L L L/H* L I1x H H L L L L L H H H L L L L L H PHASE x 1 1 1 1 1 1 1 x 0 0 0 0 0 0 0 Phase 2 (%ITripMax) 100 100 100/66* 33 0 33 100/66* 100 100 100 100/66* 33 0 33 100/66* 100 I0x L L L/H* L H L L/H* L L L L/H* L H L L/H* L I1x L L L H H H L L L L L H H H L L PHASE 1 1 1 1 X 0 0 0 0 0 0 0 X 1 1 1 1 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 8 15 16 * Denotes modified step mode
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
12
A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
Pin-out Diagrams
LP Package
CP1 1 CP2 2 VCP 3 VREG 4 IN02 5 IN12 6 IN11 7 ROSC 8 SLEEP 9 VDD 10 IN01 11 REF 12 PAD 24 GND 23 PH2 22 OUT2B 21 VBB2 20 SENSE2 19 OUT2A 18 OUT1A 17 SENSE1 16 VBB1 15 OUT1B 14 PH1 13 GND
Terminal List Table
Name CP1 CP2 PH1 PH2 GND IN02 IN12 NC OUT1A OUT1B OUT2A OUT2B REF IN11 ROSC SENSE1 SENSE2 SLEEP IN01 VBB1 VBB2 VCP VDD VREG PAD Number LP 1 2 14 23 13, 24 5 6 - 18 15 19 22 12 7 8 17 20 9 11 16 21 3 10 4 - Charge pump capacitor terminal Charge pump capacitor terminal Logic input Logic input Ground* Logic input Logic input No connection DMOS Full Bridge 1 Output A DMOS Full Bridge 1 Output B DMOS Full Bridge 2 Output A DMOS Full Bridge 2 Output B Gm reference voltage input Logic input Timing set Sense resistor terminal for Bridge 1 Sense resistor terminal for Bridge 2 Logic input Logic input Load supply Load supply Reservoir capacitor terminal Logic supply Regulator decoupling terminal Exposed pad for enhanced thermal dissipation* Description
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
13
A4986
DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protection
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
7.80 0.10 24 4 4 +0.05 0.15 -0.06
0.45
0.65
B 3.00 A 4.40 0.10 6.40 0.20 0.60 0.15 (1.00) 3.00 6.10
1
2 4.32 0.25 SEATING PLANE 0.65 1.20 MAX 0.15 MAX C SEATING PLANE GAUGE PLANE 1.65 C
4.32 PCB Layout Reference View
24X 0.10 C +0.05 0.25 -0.06
For reference only (reference JEDEC MO-153 ADT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright (c)2009-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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