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Rev 1; 4/09
5.0V 8-Bit Programmable Timing Element
General Description
The DS1124 is an 8-bit programmable timing element similar in function to the DS1021-25. The 256-delay intervals are programmed by using a 3-wire serial interface. With a 0.25ns step size, the DS1124 can provide a delay time from 20ns up to 84ns with an integral nonlinearity of 3ns. 0.25ns Step Size Leading- and Trailing-Edge Accuracy CMOS/TTL Compatible Can Delay Signals by a Full Period or More 3-Wire Serial Programming Interface Single 5.0V Power Supply 10-pin SOP Package
Features
DS1124
Applications
LCD Televisions Telecommunications Digital Test Equipment Digital Video Projection Signal Generators and Analyzers
Pin Configuration
TOP VIEW +
IN 1 E Q GND GND 2 3 4 5 10 VCC 9 VCC D CLK OUT
Ordering Information
PART DS1124U-25+ DS1124U-25+T TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 10 SOP 10 SOP
DS1124
8 7 6
+Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.
SOP
Typical Operating Circuit
VCC SYSTEM CLOCK IN E OPTIONAL MICROPROCESSOR CLK D GND Q VCC OUT
DS1124
VARIABLE DELAY
________________________________________________________________ Maxim Integrated Products
1
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5.0V 8-Bit Programmable Timing Element DS1124
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Pin Relative to Ground .....-0.5V to +6.0V Voltage Range on IN, E, D, and CLK Relative to Ground* ................................-0.5V to (VCC + 0.5V) Operating Temperature Range ...........................-40C to +85C *Not to exceed +6.0V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Storage Temperature Range .............................-55C to +125C Short-Circuit Output Current ..........................50mA for 1 second Soldering Temperature...................See J-STD-020 Specification
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage Input Logic 1 Input Logic 0 SYMBOL VCC VIH VIL (Note 1) CONDITIONS MIN 4.75 2.2 -0.3 TYP MAX 5.25 VCC + 0.3 +0.8 UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = +4.75V to +5.25V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Active Current High-Level Output Current Low-Level Output Current Input Leakage SYMBOL ICCA I OH IOL IL VCC = min, V OH = 2.3V Q pin, VCC = min, VOL = 0.5V OUT pin, VCC = min, V OL = 0.5V -1.0 CONDITIONS MIN TYP 15 MAX 30 -1.0 4.0 8.0 +1.0 UNITS mA mA mA A
AC ELECTRICAL CHARACTERISTICS
(VCC = +4.75V to +5.25V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Serial Clock Frequency Input Pulse Width (E, CLK) Data Setup to Clock Data Hold from Clock Data Setup to Enable Data Hold to Enable Enable Setup to Clock Enable Hold from Clock E to Q Valid E to Q High Impedance CLK to Q Valid CLK to Q Invalid SYMBOL fCLK t EW, tCW tDSC tDHC tDSE tDHE tES tEH t EQV t EQZ tCQV tCQX 0 0 50 30 0 30 0 0 30 50 50 50 CONDITIONS MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns
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5.0V 8-Bit Programmable Timing Element
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.75V to +5.25V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER E to Delay Valid E to Delay Invalid Power-Up Time Delay Step Size Step 0 Delay Step 0 Delay Initial Accuracy Step 0 Voltage Variation Step 0 Temperature Variation Step 0 Temperature Variation Step 255 Delay Step 255 Delay Initial Accuracy Step 255 Voltage Variation Step 255 Temperature Variation Step 255 Temperature Variation Integral Nonlinearity (Deviation from Straight Line) Minimum Input Pulse Width Minimum Input Period Input Rise and Fall Times t ERR tWI t PER tR, tF 0C to +70C -40C to +85C VCC = 5V, TA = +25C (Note 3) (Note 4) (Note 5) (Note 6) tD255 0C to +70C -40C to +85C (Note 2) VCC = 5V, TA = +25C SYMBOL t EDV t EDX t PU t STEP tD0 TA = +25C (Note 2) VCC = 5V, TA = +25C -0.75 17 -0.6 -0.4 -1 -1 77 -0.6 -0.4 -3 -5 -2 40 80 0 1 0 83.75 +0.25 20 0 100 +1 23 +0.6 +0.4 +1 +1 88 +0.6 +0.4 +3 +5 +2 CONDITIONS MIN TYP MAX 50 UNITS s ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
DS1124
Note 1: All voltages are referenced to ground. Note 2: Measured from rising edge of the input to the rising edge of the output. The programmed delay, tD, can be programmed with values from 0 to 255. See Figure 1. Note 3: See the Integral Nonlinearity section and Figure 5. Note 4: This is the minimum allowable interval between transitions on the input to ensure accurate device operation. This parameter can be violated but timing accuracy may be impaired and ultimately very narrow pulse widths will result in no output from the device. See Figure 1. Note 5: When a 50% duty cycle input clock is used, this defines the highest usable clock frequency. When asymmetrical clock inputs are used, the maximum usable clock frequency must be reduced to conform to the minimum input pulse-width requirement. See Figure 1. Note 6: Faster rise and fall times give the greatest accuracy in measured delay. Slow edges (outside the specification maximum) can result in erratic operations.
tWI IN IN OUT tWI
DS1124
tD0 OUT TIMING REFERENCED TO 1.5V. tD tD0
tD
Figure 1. Delay Timing Diagram
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5.0V 8-Bit Programmable Timing Element DS1124
Typical Operating Characteristics
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
TYPICAL DELAY vs. PROGRAMMED STEP
DS1124 toc01
CHANGE FROM NOMINAL DELAY vs. SUPPLY VOLTAGE
DS1124 toc02
CHANGE FROM NOMINAL DELAY vs. TEMPERATURE
1.5 PROGRAMMED DELAY (ns) 1.0 0.5 0 STEP 0 -0.5 -1.0 -1.5 -2.0
DS1124 toc03
90 80 70 TYPICAL DELAY (ns) 60 50 40 30 20 10 0 0 25 50 75 100 125 150 175 200 225 250 PROGRAMMED STEP (dec)
0.6 0.4 PROGRAMMED DELAY (ns) STEP 255 0.2 0 STEP 0 -0.2 -0.4 -0.6 4.75 4.85 4.95 5.05 5.15
2.0 STEP 255
5.25
-40
-20
0
20
40
60
80
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
ACTIVE SUPPLY CURRENT vs. INPUT FREQUENCY
DS1124 toc04
STANDBY SUPPLY CURRENT vs. TEMPERATURE
24 STANDBY SUPPLY CURRENT (mA) 23 22 21 20 19 18 17 16 15 0 -40 -20 0 20 40 60 80 0 VCC = 5.25V
DS1124 toc05
OUTPUT VOLTAGE LOW vs. OUTPUT CURRENT
VCC = 4.75V 0.25 OUTPUT VOLTAGE (V) 0.20 0.15 0.10 0.05
DS1124 toc06
20.0 ACTIVE SUPPLY CURRENT (mA) 19.5 19.0 18.5 18.0 17.5 17.0 16.5 1 10 100 1000 10000
25
0.30
100000
2
4
6
8
10
INPUT (IN) FREQUENCY (kHz)
TEMPERATURE (C)
OUTPUT CURRENT (mA)
4
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5.0V 8-Bit Programmable Timing Element
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
DS1124
OUTPUT VOLTAGE HIGH vs. OUTPUT CURRENT
DS1124 toc07
DELAY INTEGRAL NONLINEARITY vs. STEP
DS1124 toc08
DELAY DIFFERENTIAL NONLINEARITY vs. STEP
DELAY DIFFERENTIAL NONLINEARITY (ns)
DS1124 toc09
4.80 4.75 OUTPUT VOLTAGE (V) 4.70 4.65 4.60 4.55 4.50 -10 -8 -6 -4 -2 0 OUTPUT CURRENT (mA)
1.0 DELAY INTEGRAL NONLINEARITY (ns)
1.0
0.5
0.5
0
0
-0.5
-0.5
-1.0 0 25 50 75 100 125 150 175 200 225 250 STEP (dec)
-1.0 0 25 50 75 100 125 150 175 200 225 250 STEP (dec)
Pin Description
PIN 1 2 3 4, 5 6 7 8 9, 10 NAME IN E Q GND OUT CLK D VCC Delay Input Signal Input Enable Serial Data Output Ground. Both grounds must be connected. Delay Output Signal Serial Clock Input Serial Data Input Power Supply. Both supplies must be connected. FUNCTION
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5.0V 8-Bit Programmable Timing Element DS1124
Block Diagram
Using the Serial Programming Interface
Serial mode operates similar to a shift register. When the E pin is set at a high logic level, it enables the shift register and CLK clocks the data, D, into the register one bit at a time starting with the most significant bit. After all 8 bits are shifted into the DS1124, E must be pulled low to end the data transfer and activate the new value. A settling time (tEDV) is required after E is pulled low before the signal delay will meet its specified accuracy. A timing diagram for the serial interface is shown in Figure 3. The 3-wire interface also has an output (Q) that can be used to cascade multiple 3-wire devices, and it can be used to read the current value of the devices on the bus. To read the current values stored by the 3-wire device(s), the latch must be enabled and the value of Q must be read and then written back to D before the register is clocked. This causes the current value of the register to be written back into the DS1124 as it is being read. This can be accomplished in a couple of different ways. If the microprocessor has an I/O pin that is high impedance when set as an input, a feedback resistor (RFB, generally between 1k and 10k) can be used to write the data on Q back to D as the value is read, see Figure 4A. If the microprocessor has an internal pullup on its I/O pins, or only offers separate input and output pins, the value in the register can still be read. The circuit shown in Figure 4B allows the Q values to read by the microprocessor, which must write the Q value to D before it can clock the bus to read the next bit. If the Q values are read without writing them to D (with the pullup or otherwise), the read will be destructive. A destructive read cycle likely results in an undesirable change in the delay setting.
IN
PROGRAMMABLE DELAY
OUT
8 8-BIT LATCH E
8 8-BIT SHIFT REGISTER
Q CLK D
DS1124
Detailed Description
The DS1124 is an 8-bit programmable delay line that can be adjusted between 256 different delay intervals. The DS1124 architecture (see Figure 2) allows some signals to be delayed by more than one period, which lets the phase of the signal to be adjusted up to a full 360. Programming is performed by a 3-wire serial interface. Using the 3-wire interface, it is possible to cascade multiple devices together for systems requiring multiple programmable delays without using additional I/O resources.
IN
OUT
256 CONTROL LINES
tSTEP
tSTEP
tSTEP
tSTEP
256 LINE DECODER
255 UNIT DELAY CELLS
8-BIT LATCH VALUE
DS1124
Figure 2. Conceptual Design
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5.0V 8-Bit Programmable Timing Element DS1124
tEW
ENABLE (E)
tES CLOCK (CLK)
tCW
tCW
tEH
tDSC SERIAL INPUT (D)
tDHC
NEW BIT 7
NEW BIT 6
NEW BIT 0
tEQV SERIAL OUTPUT (Q)
tCQV
tCQX
tEQZ
OLD BIT 7
OLD BIT 6
OLD BIT 0
tEDV tEDX DELAY TIME
PREVIOUS VALUE
NEW VALUE
Figure 3. Serial Interface Timing Diagram
Figure 4C shows how to cascade multiple DS1124s onto the same 3-wire bus. One important detail of writing software for cascaded 3-wire devices is that all the devices on the bus must be written to or read from during each read or write cycle. Attempting to write to only the first device (U1) would cause the data stored in U1 to be shifted to U2, U2's data would be shifted to U3, etc. As shown, the microprocessor would have to shift 24 bits during each read or write cycle to avoid inadvertently changing the settings in any of the 3-wire devices. Also note that the feedback resistor or a separate input (not shown) can still be used to read the 3-wire device settings when multiple devices are cascaded.
Integral Nonlinearity
Integral nonlinearity (INL) is defined as the deviation from a straight line response drawn between the measured step zero delay (tD0) and the measured step 255 delay (tD255) with respect to the step 0 delay. Figure 5 shows INL's effect on delay performance graphically.
Application Information
Power-Supply Decoupling
To achieve the best results when using the DS1124, decouple the power supply with a 0.01F and a 0.1F capacitor. Use high-quality, ceramic, surface mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins of the DS1124 to minimize lead inductance. The DS1124 may not perform as specified if good decoupling practices are not followed.
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5.0V 8-Bit Programmable Timing Element DS1124
MICROPROCESSOR OUTPUT OUTPUT I/O PIN E CLK D Q MICROPROCESSOR
DS1124
OUTPUT OUTPUT OUTPUT INPUT
E CLK D
DS1124
Q
RFB A) USING A FEEDBACK RESISTOR WITH AN I/O PIN FOR READING THE DS1124. B) USING A SEPARATE INPUT PIN TO READ THE DS1124.
MICROPROCESSOR OUTPUT OUTPUT I/O PIN
E CLK D
DS1124 U1
Q
E CLK D
DS1124 U2
Q
E CLK D
DS1124 U3
Q
RFB C) CASCADING MULTIPLE DS1124s ON A 3-WIRE BUS.
Figure 4. Examples Using the Serial Interface
Test Conditions
Input: Ambient Temperature: Supply Voltage (VCC): Input Pulse: Source Impedance: Rise and Fall Times: Pulse Width: Period: 25C 3C 5.0V 0.1V High = 3.0V 0.1V Low = 0.0V 0.1V 50 max 3.0ns max (measured between 0.6V and 2.4V) 250ns 10s
Output: The outputs are loaded with 15pF. Delay is measured between the 1.5V level of the rising or falling edge of the input signal and the corresponding edge of the output signal. Note: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions.
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5.0V 8-Bit Programmable Timing Element DS1124
DELAY MEASURED tD255
MEASURED DELAY FOR ALL STEPS INL
LINE FIT BETWEEN MEASURED MAX AND MIN DELAY
EXAGGERATED
MEASURED tD0
STEP 0 64 128 192 255
Figure 5. Integral Nonlinearity
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 10 SOP PACKAGE CODE -- DOCUMENT NO. 21-0061
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5.0V 8-Bit Programmable Timing Element DS1124
Revision History
REVISION NUMBER 0 1 REVISION DATE 7/07 4/09 Initial release. Added VCC = 5V to the t ERR specification in the Electrical Characteristics table, indicating that it is only tested at TA = 25C and VCC = 5V. DESCRIPTION PAGES CHANGED -- 3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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