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| 19-5153; Rev 0; 2/10 SFP Controller with Dual LDD Interface General Description The DS1876 controls and monitors all functions for dual transmitter modules. The memory map is based on SFF-8472. The DS1876 supports APC and modulation control and eye safety functionality for two laser drivers. It continually monitors for high output current, high bias current, and low and high transmit power to ensure that laser shutdown for eye safety requirements are met without adding external components. Six ADC channels monitor VCC, temperature, and four external monitor inputs that can be used to meet all monitoring requirements. Monitoring Requirements S Six Analog Monitor Channels: Temperature, VCC, Features S Meets All SFF-8472 Transmitter Control and DS1876 PMON1, BMON1, PMON2, BMON2 PMON_ and BMON_ Support Internal and External Calibration Scalable Dynamic Range Internal Direct-to-Digital Temperature Sensor Alarm and Warning Flags for All Monitored Channels Functions for Laser Safety S Six Quick Trips for Fast Monitoring of Critical S Four 10-Bit Delta-Sigma Outputs Applications Dual Tx Video SFP Modules Each Controlled by 72-Entry Temperature Lookup Table (LUT) S Digital I/O Pins: Six Inputs, Five Outputs S Comprehensive Fault Measurement System with Ordering Information PART DS1876T+ DS1876T+T&R TEMP RANGE -40NC to +95NC -40NC to +95NC PIN-PACKAGE 28 TQFN-EP* 28 TQFN-EP* Maskable Laser Shutdown Capability S Flexible, Two-Level Password Scheme Provides +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad. Three Levels of Security S 256 Additional Bytes Located at A0h Slave Address S Transmitter 1 is Accessed at A2h Slave Address S Transmitter 2 is Accessed at B2h Slave Address S I2C-Compatible Interface S +2.85V to +3.9V Operating Voltage Range S -40NC to +95NC Operating Temperature Range S 28-Pin TQFN (5mm x 5mm x 0.8mm) Package _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. SFP Controller with Dual LDD Interface DS1876 TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MOD_, APC_ Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Analog Quick-Trip Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Quick-Trip Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Nonvolatile Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DACs During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DACs as a Function of Transmit Disable (TXD1, TXD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Quick-Trip Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Six Quick-Trip Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Six ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Delta-Sigma Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 IN1, RSEL, OUT1, RSELOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TXF1, TXF2, TXFOUT, TXD1, TXD2, TXDOUT1, TXDOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Transmit Fault (TXFOUT) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 ______________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 TABLE OF CONTENTS (continued) Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory Map Access Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory Addresses A0h, A2h, and B2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Auxiliary Memory A0h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 04h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Power-Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 _______________________________________________________________________________________ 3 SFP Controller with Dual LDD Interface DS1876 LIST OF FIGURES Figure 1. Power-Up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. TXD1, TXD2 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. ADC Round-Robin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. Low-Voltage Hysteresis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Recommended RC Filter for DAC Outputs in Voltage Mode and Current Sink Mode . . . . . . . . . . . . . . . . . 16 Figure 7. 3-Bit (8-Position) Delta-Sigma Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. DAC OFFSET LUTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Logic Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10. Logic Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11a. TXFOUT Nonlatched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11b. TXFOUT Latched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13. Example I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LIST OF TABLES Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 ______________________________________________________________________________________ SFP Controller with Dual LDD Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on PMON_, BMON_, RSEL, IN1, TXF_, and TXD_ Pins Relative to Ground ............................... -0.5V to (VCC + 0.5V)* Voltage Range on VCC, SDA, SCL, OUT1, RSELOUT, and TXFOUT Pins Relative to Ground ...............................................-0.5V to +6V *Subject to not exceeding +6V. Continuous Power Dissipation 28-Pin TQFN (derate 34.5mW/C) above +70C ....2758.6mW Operating Temperature Range .......................... -40NC to +95NC Programming Temperature Range ....................... 0NC to +95NC Storage Temperature Range............................ -55NC to +125NC Soldering Temperature ......................... Refer to the IPC/JEDEC J-STD-020 Specification. DS1876 Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Main Supply Voltage High-Level Input Voltage (SDA, SCL) Low-Level Input Voltage (SDA, SCL) High-Level Input Voltage (TXD_, TXF_, RSEL, IN1) Low-Level Input Voltage (TXD_, TXF_, RSEL, IN1) SYMBOL VCC VIH:1 VIL:1 VIH:2 VIL:2 (Note 1) CONDITIONS MIN +2.85 0.7 x VCC -0.3 2.0 -0.3 TYP MAX +3.9 VCC + 0.3 0.3 x VCC VCC + 0.3 +0.8 UNITS V V V V V DC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Supply Current Output Leakage (SDA, OUT1, RSELOUT, TXFOUT) Low-Level Output Voltage (SDA, OUT1, RSELOUT, TXDOUT_, MOD_, APC_, TXFOUT) High-Level Output Voltage (MOD_, APC_, TXDOUT_) TXDOUT_ Before EEPROM Recall MOD_, APC_ Before Recall Input Leakage Current (SCL, TXD_, RSEL, IN1, TXF_) Digital Power-On Reset Analog Power-On Reset ILI POD POA 1.0 2.0 Figure 1 SYMBOL ICC ILO IOL = 4mA IOL = 6mA IOH = 4mA VCC 0.4 10 10 100 100 1 2.2 2.75 (Notes 1, 2) CONDITIONS MIN TYP 2.5 MAX 10 1 0.4 V 0.6 V nA nA FA V V UNITS mA FA VOL VOH _______________________________________________________________________________________ 5 SFP Controller with Dual LDD Interface DS1876 MOD_, APC_ ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Main Oscillator Frequency Delta-Sigma Input-Clock Frequency Reference Voltage Input (REFIN) Output Range Output Resolution Output Impedance RDS See the Delta-Sigma Outputs section for details 35 SYMBOL fOSC fDS VREFIN Minimum 0.1FF to GND 2 0 CONDITIONS MIN TYP 5 fOSC/2 VCC VREFIN 10 100 MAX UNITS MHz MHz V V Bits I ANALOG QUICK-TRIP CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER TXP HI, TXP LO Full-Scale Voltage HBIAS Full-Scale Voltage PMON_ Input Resistance Resolution Error Integral Nonlinearity Differential Nonlinearity Temperature Drift Offset TA = +25C -1 -1 -2.5 -5 35 SYMBOL CONDITIONS MIN TYP 2.507 1.25 50 8 2 +1 +1 +2.5 +10 65 MAX UNITS V V kW Bits %FS LSB LSB %FS mV ANALOG VOLTAGE MONITORING CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER ADC Resolution Input/Supply Accuracy (BMON_, PMON_, VCC) Update Rate for Temperature, BMON_, PMON_, VCC Input/Supply Offset (BMON_, PMON_, VCC) Factory Setting (Note 4) ACC tRR VOS (Note 3) BMON_, PMON_ VCC At factory setting SYMBOL CONDITIONS MIN TYP 13 0.25 64 0 2.5 6.5536 0.5 78 5 MAX UNITS Bits %FS ms LSB V 6 ______________________________________________________________________________________ SFP Controller with Dual LDD Interface DIGITAL THERMOMETER CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Thermometer Error SYMBOL TERR CONDITIONS -40NC to +95NC MIN -3 TYP MAX +3 UNITS NC DS1876 AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER TXD_ Enable Recovery from TXD_ Disable (Figure 2) Fault Reset Time (to TXFOUT = 0) Fault Assert Time (to TXFOUT = 1) SYMBOL tOFF tON tINITR1 tINITR2 tFAULT From TXD_ From TXD_ From TXD_ On power-up or TXD_, when VCC LO alarm is detected (Note 5) After HTXP_, LTXP_, HBATH_ 131 161 1.6 10.5 ms Fs CONDITIONS MIN TYP MAX 5 1 UNITS Fs ms QUICK-TRIP TIMING CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Output-Enable Time Following POA Sample Time per Quick-Trip Comparison SYMBOL tINIT tREP CONDITIONS MIN TYP 20 1.6 MAX UNITS ms Fs I2C AC ELECTRICAL CHARACTERISTICS PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus Free Time Between STOP and START Condition START Hold Time START Setup Time Data Out Hold Time Data In Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals STOP Setup Time Capacitive Load for Each Bus Line EEPROM Write Time SYMBOL fSCL tLOW tHIGH tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO CB tWR (Note 8) (Note 7) (Note 7) (Note 6) (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted. See the I2C Communication section.) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 0.9 TYP MAX 400 UNITS kHz Fs Fs Fs Fs Fs Fs ns ns ns Fs pF ms 7 _______________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.85V to +3.9V, unless otherwise noted.) PARAMETER EEPROM Write Cycles Note Note Note Note Note 1: 2: 3: 4: 5: SYMBOL At +25NC At +85NC CONDITIONS MIN 200,000 50,000 TYP MAX UNITS All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative. Inputs are at supply rail. Outputs are not loaded. This parameter is guaranteed by design. Full scale is user programmable. A temperature conversion is completed and MOD1 DAC, MOD2 DAC, APC1 DAC, and APC2 DAC values are recalled from the LUT and VCC has been measured to be above VCC LO alarm, if the VCC LO alarm is enabled. Note 6: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard mode. Note 7: CB--Total capacitance of one bus line in pF. Note 8: EEPROM write begins after a STOP condition occurs. 8 ______________________________________________________________________________________ SFP Controller with Dual LDD Interface Typical Operating Characteristics (VCC = 3.3V, TA = +25C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.6 SUPPLY CURRENT (mA) 2.5 2.4 2.3 2.2 2.1 2.0 2.850 DS1876 SUPPLY CURRENT vs. TEMPERATURE 2.9 2.8 SUPPLY CURRENT (mA) 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 SDA = SCL = VCC DACs AT 1FFh +95C DS1876 toc01 DAC POSITIONS = 1FFh SDA = SCL = VCC VCC = 3.9V VCC = 3.3V +25C -40C VCC = 2.85V -40 -15 10 35 60 85 3.150 3.450 VCC (V) 3.750 TEMPERATURE (C) APC1/2 AND MOD1/2 DAC DNL DS1876 toc03 APC1/2 AND MOD1/2 DAC INL APC1/2 AND MOD1/2 DAC INL (LSB) DS1876 toc04 1.0 APC1/2 AND MOD1/2 DAC DNL (LSB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 DAC POSITION (DEC) 3 2 1 0 -1 -2 -3 1000 0 500 DAC POSITION (DEC) 1000 PMON1/2 AND BMON1/2 DNL DS1876 toc05 PMON1/2 AND BMON1/2 INL 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 PMON1/2 AND BMON1/2 DNL (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 0.5 1.0 1.5 2.0 2.5 PMON1/2 AND BMON1/2 INL (LSB) 0.8 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V 0 0.5 1.0 1.5 2.0 2.5 PMON1/2 AND BMON1/2 INPUT VOLTAGE (V) PMON1/2 AND BMON1/2 INPUT VOLTAGE (V) _______________________________________________________________________________________ DS1876 toc06 1.0 1.0 DS1876 toc02 2.7 3.0 9 SFP Controller with Dual LDD Interface DS1876 Pin Configuration MOD1 MOD2 TXDOUT2 GND GND 21 REFIN 22 TXD2 23 APC2 24 APC1 25 VCC 26 TXF2 27 OUT1 28 1 RSELOUT 20 19 18 17 VCC 16 N.C. 15 14 13 12 BMON1 PMON1 BMON2 PMON2 TXDOUT1 RSEL GND 11 10 9 8 7 TXD1 TOP VIEW DS1876 + 2 SCL 3 SDA 4 TXFOUT 5 TXF1 *EP 6 IN1 THIN QFN (5mm x 5mm x 0.8mm) *EXPOSED PAD. Pin Description PIN 1 2 3 4 5 6 7 8, 18, 21 9 10 11 12 13 NAME RSELOUT SCL SDA TXFOUT TXF1 IN1 TXD1 GND RSEL TXDOUT1 PMON2 BMON2 PMON1 FUNCTION Rate-Select Output I2C Serial-Clock Input I2C Serial-Data Input/Output Transmit Fault Output, Open Drain Transmit Fault Input 1 Digital Input. General-purpose input, AS1 in SFF-8079, or RS1 in SFF-8431. Transmit Disable Input 1 Ground Connection Rate-Select Input Transmit Disable Output 1 External Monitor Input PMON2 and HTXP2/LTXP2 Quick Trip External Monitor Input BMON2 and HBATH2 Quick Trip External Monitor Input PMON1 and HTXP1/LTXP1 Quick Trip PIN 14 15 16, 26 17 19 20 22 23 24 25 27 28 -- NAME BMON1 N.C. VCC TXDOUT2 MOD2 MOD1 REFIN TXD2 APC2 APC1 TXF2 OUT1 EP FUNCTION External Monitor Input BMON1 and HBATH1 Quick Trip No Connection Power-Supply Input Transmit Disable Output 2 MOD2 DAC, Delta-Sigma Output MOD1 DAC, Delta-Sigma Output Reference Input for DAC1 and DAC2 Transmit Disable Input 2 APC2 DAC, Delta-Sigma Output APC1 DAC, Delta-Sigma Output Transmit Fault Input 2 Digital Output. General-purpose output, AS1 output in SFF-8079, or RS1 output in SFF-8431. Exposed Pad (Connect to GND) 10 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Block Diagram DS1876 VCC VCC SDA SCL I2C INTERFACE MAIN MEMORY EEPROM/SRAM A/D CONFIGURATION/RESULTS, SYSTEM STATUS/CONTROL BITS, ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY MOD2 DAC 10 BITS REFIN MOD2 APC2 DAC 10 BITS APC2 EEPROM 256 BYTES AT A0h MOD1 DAC 10 BITS MOD1 VCC BMON1 BMON2 PMON2 ANALOG MUX PMON1 13-BIT ADC 8-BIT QTs APC1 DAC 10 BITS APC1 TXFOUT POWER-ON ANALOG INTERRUPT VCC TEMPERATURE SENSOR TXD1 TXDOUT1 TXD2 LOGIC CONTROL TXF1 VCC TXF2 TXDOUT2 RSELOUT RSEL LOGIC CONTROL IN1 OUT1 DS1876 GND ______________________________________________________________________________________ 11 SFP Controller with Dual LDD Interface DS1876 Typical Operating Circuit TOSA2 LDD2 BMON APCIN APCSET MODSET TOSA1 LDD1 BMON APCIN APCSET MODSET RC FILTERS (FIGURE 6) MOD1 DAC APC1 DAC EEPROM MOD2 DAC APC2 DAC BMON1 PMON1 BMON2 PMON2 RP1 RB1 RP2 RB1 ADC FAULT DISABLE FAULT DISABLE DS1876 TXF1 TXF2 TXFOUT TXDOUT1 TXDOUT2 TXD1 TXD2 TX_FAULT TX_DISABLE1 TX_DISABLE2 QUICK TRIP I2C SDA SCL MODE_DEF2 (SDA) MODE_DEF1 (SCL) Detailed Description The DS1876 integrates the control and monitoring functionality required in a dual transmitter system. Key components of the DS1876 are shown in the Block Diagram and described in subsequent sections. On power-up, the DS1876 sets the DACs to high impedance. After time tINIT, the DACs are set to an initial condition set in EEPROM. After a temperature conversion is completed and if the VCC LO alarm is enabled, an additional VCC conversion above the customer-defined VCC LO alarm level is required before the DACs are updated with the value determined by the temperature conversion and the DAC LUT. If a fault is detected, and TXD1 and TXD2 are toggled to re-enable the outputs, the DS1876 powers up following a similar sequence to an initial power-up. The DACs During Power-Up 12 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 1. Acronyms ACRONYM ADC AGC APC APD ATB DAC LOS LUT NV QT TE TIA ROSA SEE SFF SFF-8472 SFP SFP+ TOSA TXP DESCRIPTION Analog-to-Digital Converter Automatic Gain Control Automatic Power Control Avalanche Photodiode Alarm Trap Bytes Digital-to-Analog Converter Loss of Signal Lookup Table Nonvolatile Quick Trip Tracking Error Transimpedance Amplifier Receiver Optical Subassembly Shadowed EEPROM Small Form Factor Document Defining Register Map of SFPs and SFFs Small Form Factor Pluggable Enhanced SFP Transmit Optical Subassembly Transmit Power only difference is that the DS1876 already has determined the present temperature, so the tINIT time is not required for the DS1876 to recall the APC and MOD set points from EEPROM. See Figure 1. DS1876 If TXD1 or TXD2 are asserted (logic 1) during normal operation, the associated outputs are disabled within tOFF. When TXD1 or TXD2 are deasserted (logic 0), the DS1876 sets the DACs with the value associated with the present temperature. When asserted, soft TXD1 or soft TXD2 (TXDC) (Lower Memory, Register 6Eh) would allow a software control identical to the TXD1 or TXD2 pin (Figure 2). The POLARITY register (Table 02h, Register C6h) determines if the off-state value of the DACs is VREFIN or 0V. As shown in Figure 3, the DS1876's input comparator is shared among the six quick-trip alarms (TXP1 HI, TXP1 LO, TXP2 HI, TXP2 LO, BIAS1 HI, and BIAS2 HI). The comparator polls the alarms in a multiplexed sequence. The updates are used to compare the HTXP1, LTXP1, HTXP2, and LTXP2 (monitor diode voltages) and the HBATH1 and HBATH2 (BMON1, BMON2) signals against the internal APC and BIAS reference, respectively. Depending on the results of the comparison, the DACs as a Function of Transmit Disable (TXD1, TXD2) Quick-Trip Timing VPOA VCC 500s tINIT DAC SETTINGS HIGH IMPEDANCE OFF STATE LUT VALUE Figure 1. Power-Up Timing TXD_ tOFF DAC SETTINGS LUT VALUE OFF STATE tON LUT VALUE Figure 2. TXD1, TXD2 Timing ______________________________________________________________________________________ 13 SFP Controller with Dual LDD Interface DS1876 QT CYCLE QUICK-TRIP SAMPLE TIMES LTXP2 SAMPLE HBIAS1 SAMPLE tREP HBIAS2 SAMPLE HTXP1 SAMPLE HTXP2 SAMPLE LTXP1 SAMPLE LTXP2 SAMPLE HBIAS1 SAMPLE Figure 3. Quick-Trip Sample Timing Table 2. ADC Default Monitor Full-Scale Ranges SIGNAL (UNITS) Temperature (NC) VCC (V) PMON1, PMON2 and BMON1, BMON2 (V) +FS SIGNAL 127.996 6.5528 2.4997 +FS HEX 7FFF FFF8 FFF8 -FS SIGNAL -128 0 0 -FS HEX 8000 0000 0000 corresponding alarms and warnings (TXP HI1, TXP LO1, TXP HI2, TXP LO2, BIAS HI1, and BIAS HI2) are asserted or deasserted. After resetting, the device completes one QT cycle before making comparisons. The TXP LO quick-trip alarm updates its alarm bit, but does not create FETG until after TXDEXT. TXP HI and BIAS HI can also be configured to wait for TXDEXT; however, this can be disabled using QTHEXT_ (Table 02h, Register 88h). Monitors and Fault Detection Monitors Monitoring functions on the DS1876 include six quicktrip comparators and six ADC channels. This monitoring combined with the alarm enables (Table 01h/05h) determines when/if the DS1876 turns off DACs and triggers the TXFOUT and TXDOUT1, TXDOUT2 outputs. All the monitoring levels and interrupt masks are user programmable. Six Quick-Trip Monitors and Alarms Six quick-trip monitors are provided to detect potential laser safety issues and LOS status. These monitor the following: 1) High Bias Current 1 (HBATH1), causing QT BIAS1 HI 2) Low Transmit Power 1 (LTXP1), causing QT TXP1 LO 3) High Transmit Power 1 (HTXP1), causing QT TXP1 HI 4) High Bias Current 2 (HBATH2), causing QT BIAS2 HI 5) Low Transmit Power 2 (LTXP2), causing QT TXP2 LO 6) High Transmit Power 2 (HTXP2), causing QT TXP2 HI The high and low transmit power quick-trip registers (HTXP1, HTXP2, LTXP1, and LTXP2) set the thresholds used to compare against the PMON1 and PMON2 voltages to determine if the transmit power is within specification. The HBATH1 and HBATH2 QTs compare the BMON1 and BMON2 inputs (generally from the laser driver's bias monitor output) against their threshold settings to determine if the present bias current is above specification. The bias and power QTs are routed to FETG through interrupt masks to allow combinations of these alarms to be used to trigger FETG. The bias and power QTs are directly connected to TXFOUT (see Figure 9). The user can program up to eight different temperature-indexed threshold levels for HBATH1 and HBATH2 (Table 06h, Registers E0h-E7h). Six ADC Monitors and Alarms The ADC monitors six channels that measure temperature (internal temp sensor), VCC, PMON1, PMON2, BMON1, and BMON2 using an analog multiplexer to measure them round-robin with a single ADC (see the ADC Timing section). The channels have a customerprogrammable full-scale range, and all channels have a customer-programmable offset value that is factory programmed to a default value (see Table 2). Additionally, PMON1, PMON2 and BMON1, BMON2 can right-shift results by up to 7 bits before the results are compared to alarm thresholds or read over the I2C bus. This allows customers with specified ADC ranges to calibrate the ADC full scale to a factor of 1/2n of their specified range to measure small signals. The DS1876 can then rightshift the results by n bits to maintain the bit weight of their specification. 14 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface The ADC results (after right-shifting, if used) are compared to the alarm and warning thresholds after each conversion, and the corresponding alarms are set that can be used to trigger the TXFOUT output. These ADC thresholds are user programmable, as are the masking registers that can be used to prevent the alarms from triggering the TXFOUT output. ADC Timing There are six analog channels that are digitized in a round-robin fashion in the order as shown in Figure 4. The total time required to convert all six channels is tRR (see the Analog Voltage Monitoring Characteristics table for details). Right-Shifting ADC Result If the weighting of the ADC digital reading must conform to a predetermined full-scale (PFS) value defined by a standard's specification (e.g., SFF-8472), then rightshifting can be used to adjust the PFS analog measurement range while maintaining the weighting of the ADC results. The DS1876's range is wide enough to cover all requirements; when the maximum input value is P 1/2 the FS value, right-shifting can be used to obtain greater accuracy. For instance, the maximum voltage might be 1/8 the specified PFS value, so only 1/8 of the converter's range is effective over this range. An alternative is to calibrate the ADC's full-scale range to 1/8 the readable PFS value and use a right-shift value of 3. With this implementation, the resolution of the measurement is increased by a factor of 8, and because the result is digitally divided by 8 by right-shifting, the bit weight of the measurement still meets the standard's specification (i.e., SFF-8472). The right-shift operation on the ADC result is carried out based on the contents of right-shift control registers (Table 02h, Registers 8Eh-8Fh) in EEPROM. Four analog channels--PMON1, PMON2, BMON1, and BMON2-- each have 3 bits allocated to set the number of rightshifts. Up to seven right-shift operations are allowed and are executed as a part of every conversion before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers (Lower Memory, Registers 64h-6Bh). This is true during the setup of internal calibration as well as during subsequent data conversions. The DS1876 contains two power-on reset (POR) levels. The lower level is a digital POR (POD) and the higher level is an analog POR (POA). At startup, before the supply voltage rises above POA, the outputs are disabled, all SRAM locations are set to their defaults, shadowed EEPROM (SEE) locations are zero, and all analog circuitry is disabled. When VCC reaches POA, the SEE is recalled, and the analog circuitry is enabled. While VCC remains above POA, the device is in its normal operating state, and it responds based on its nonvolatile configuration. If during operation VCC falls below POA, but is still above POD, the SRAM retains the SEE settings from the first SEE recall, but the device analog is shut down and the outputs disabled. If the supply voltage recovers back above POA, the device immediately resumes normal operation. If the supply voltage falls below POD, the device SRAM is placed in its default state and another SEE recall is required to reload the nonvolatile settings. The EEPROM recall occurs the next time VCC next exceeds POA. Figure 5 shows the sequence of events as the voltage varies. Any time VCC is above POD, the I2C interface can be used to determine if VCC is below the POA level. This is accomplished by checking the RDYB bit in the status byte (Lower Memory, Register 6Eh). RDYB is set when VCC is below POA; when VCC rises above POA, RDYB is timed (within 500Fs) to go to 0, at which point the part is fully functional. DS1876 Low-Voltage Operation ONE ROUND-ROBIN ADC CYCLE TEMP VCC BMON1 tRR NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LO ALARM THRESHOLD. THIS ALSO OCCURS IF THERE ARE BOTH A TXD1 EVENT AND A TXD2 EVENT UNDER THE SAME CONDITIONS AS PREVIOUSLY MENTIONED. BMON2 PMON1 PMON2 TEMP Figure 4. ADC Round-Robin Timing ______________________________________________________________________________________ 15 SFP Controller with Dual LDD Interface DS1876 SEE RECALL VPOA VCC VPOD SEE RECALL SEE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 Figure 5. Low-Voltage Hysteresis Example 3.24k DAC 3.24k VOLTAGE OUTPUT 0.01F 0.01F DS1876 1k DAC 1k CURRENT SINK 0.1F 0.1F 2k A delta-sigma DAC has a digital output using pulsedensity modulation. It provides much lower output ripple than a standard digital PWM output given the same clock rate and filter components. Before tINIT, the DAC outputs are high impedance. The external RC filter components are chosen based on ripple requirements, output load, delta-sigma frequency, and desired response time. Figure 6 shows a recommended filter. For illustrative purposes, a 3-bit example is provided in Figure 7. In LUT mode the DACs are each controlled by an LUT with high-temperature resolution and an OFFSET LUT with lower temperature resolution. The high-resolution LUTs each have 2NC resolutions. The OFFSET LUTs are located in the upper eight registers (F8h-FFh) of the table containing each high-resolution LUT. The DAC values are determined as follows: DAC value = LUT + 4 x (OFFSET LUT) An example calculation for MOD1 DAC is as follows: Assumptions: 1) Temperature is +43NC 2) Table 04h (MOD1 OFFSET LUT), Register FCh = 2Ah 3) Table 04h (MOD1 LUT), Register AAh = 7Bh Because the temperature is +43NC, the MOD1 LUT index is AAh and the MOD1 OFFSET LUT index is FCh. MOD1 DAC = 7Bh + 4 x 2Ah = 123h = 291 DS1876 Figure 6. Recommended RC Filter for DAC Outputs in Voltage Mode and Current Sink Mode For all device addresses sourced from EEPROM (Table 02h, Register 8Bh), the default device addresses are A2h and B2h until VCC exceeds POA allowing the device address to be recalled from the EEPROM. Four delta-sigma outputs are provided: MOD1, MOD2, APC1, and APC2. With the addition of an external RC filter, these outputs provide 10-bit resolution analog outputs with the full-scale range set by the input REFIN. Each output is either manually controlled or controlled using a temperature-indexed LUT. Delta-Sigma Outputs 16 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 O 1 2 3 4 5 6 7 Figure 7. 3-Bit (8-Position) Delta-Sigma Example DAC OFFSET LUTs (04h/06h)[A2h/B2h] EIGHT REGISTERS PER DAC EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE TEMPCO. FDh FCh FBh 511 F8h 255 DAC LUT BITS 7:0 F9h DAC LUT BITS 7:0 FAh DAC LUT BITS 7:0 DAC LUT BITS 7:0 DAC LUT BITS 7:0 DAC LUT BITS 7:0 FFh FEh DAC LUT BITS 7:0 DAC LUT BITS 7:0 DELTA-SIGMA DACs DAC OFFSET LUTs (04h/06h)[A2h/B2h] EIGHT REGISTERS PER DAC EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE AND NEGATVE TEMPCO. FDh DAC LUT BITS 7:0 1023 1023 767 DELTA-SIGMA DACs 767 FBh FAh 511 F8h 255 DAC LUT BITS 7:0 F9h DAC LUT BITS 7:0 DAC LUT BITS 7:0 DAC LUT BITS 7:0 FCh DAC LUT BITS 7:0 FEh DAC LUT BITS 7:0 FFh DAC LUT BITS 7:0 0 -40C -8C +8C +24C +40C +56C +70C +88C +104C 0 -40C -8C +8C +24C +40C +56C +70C +88C +104C Figure 8. DAC OFFSET LUTs When temperature controlled, the DACs are updated after each temperature conversion. The reference input, REFIN, is the supply voltage for the output buffer of all four DACs. The voltage connected to REFIN and its decoupling must be able to support the edge rate requirements of the delta-sigma outputs. In a typical application, a 0.1FF capacitor should be connected between REFIN and ground. ______________________________________________________________________________________ 17 SFP Controller with Dual LDD Interface DS1876 VCC RPU TXD_ TXDC_ TXP_ HI FLAG TXP HI ENABLE HBAL_ FLAG HBAL ENABLE TXFOUTS_ QTHEXT_ TXP_ LO FLAG TXP LO ENABLE FAULT RESET TIMER (130ms) OUT IN IN OUT TXDS_ SET BIAS_ DAC AND MOD_ DAC TO HIGH IMPEDANCE C C D S R Q Q FETG_ TXD_ TXDIO_ TXDFG_ TXDOUT_ TXDFLT_ TXFINT TXFOUTS1 INVTXF_ TXF_ POWER-ON RESET TXFS_ NOTE: _ CAN BE EITHER 1 OR 2 CORRESPONDING TO TRANSMITTERS 1 OR 2. REFERS TO A PIN. TXFOUTS2 TXFOUT TXDEXT (tINITR1) Figure 9. Logic Diagram 1 IN1S INVOUT1 IN1C IN1 INVRSOUT RSELS RSELC RSEL = PINS OUT1 Register 89h). The open-drain RSELOUT output is software controlled and/or inverted through the STATUS register and CNFGA register (Table 02h, Register 88h). External pullup resistors must be provided on OUT1 and RSELOUT to realize high logic levels. TXF1, TXF2, TXFOUT, TXD1, TXD2, TXDOUT1, TXDOUT2 TXDOUT1 and TXDOUT2 are generated from a combination of TXF1, TXF2, TXD1, TXD2, and the internal signals FETG1 and FETG2 (Table 02h, Register 8Ah). A software control identical to TXD1 and TXD2 is also available (TXDC1 and TXDC2, Lower Memory, Register 6Eh). A TXD1 or TXD2 pulse is internally extended (TXDEXT) by time tINITR1 to inhibit the latching of low alarms and warnings related to the APC loop to allow for the loop to stabilize. The nonlatching alarms and warnings are TXP LO, BMON1 LO, BMON2 LO, PMON1 LO, and PMON2 LO. In addition, TXP LO is disabled from creating FETG. See the Transmit Fault (TXFOUT) Output section for a detailed explanation of TXFOUT. As shown in Figure 9, the same signals and faults can also be used to generate the internal signal FETG. FETG is used to send a fast "turn-off" command to the laser driver. The intended use is a direct connection to the laser driver's TXD1, TXD2 input if this is desired. When VCC < POA, TXDOUT1 and TXDOUT2 are high impedance. RSELOUT Figure 10. Logic Diagram 2 Six digital input pins and five digital output pins are provided for monitoring and control. Digital I/O Pins IN1, RSEL, OUT1, RSELOUT Digital input pins IN1 and RSEL primarily serve to meet the rate-select requirements of SFP and SFP+. They can also serve as general-purpose inputs. OUT1 and RSELOUT are driven by a combination of the IN1, RSEL, and logic dictated by control registers in the EEPROM (see Figure 10). The levels of IN1 and RSEL can be read from the STATUS register (Lower Memory, Register 6Eh). The open-drain output OUT1 can be controlled and/or inverted using the CNFGB register (Table 02h, 18 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 DETECTION OF TXFOUT FAULT TXFOUT Figure 11a. TXFOUT Nonlatched Operation DETECTION OF TXFOUT FAULT TXD_ OR TXFOUT RESET TXFOUT Figure 11b. TXFOUT Latched Operation Transmit Fault (TXFOUT) Output TXFOUT can be triggered by all alarms, warnings, QTs, TXD1, TXD2, TXF1, and TXF2 (see Figure 9). The six ADC alarms and warnings are controlled by enable bits (Table 01h/05h, Registers F8h and FCh). See Figures 11a and 11b for nonlatched and latched operation for TXFOUT. The CNFGB register (Table 02h, Register 89h) controls the latching of the alarms. The DS1876 has an ID hardcoded in its memory. Two registers (Table 02h, Registers 86h-87h) are assigned for this feature. Register 86h reads 76h to identify the part as the DS1876; Register 87h reads the present device version. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 12 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 12 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 12 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (Figure 12). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 12) before the next rising edge 19 Die Identification I2C Communication The following terminology is commonly used to describe I2C data transfers. I2C Definitions Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. ______________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not-acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 12) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS1876 responds to three slave addresses. The auxiliary memory always responds to a fixed I2C slave address, A0h. (If the main device's slave address is programmed to be A0h, access to the auxiliary memory is disabled.) The Lower Memory and Tables 00h-06h respond to I2C slave addresses whose lower 3 bits are configurable (A0h-AEh, B0h-BEh) using the DEVICE ADDRESS byte (Table 02h, Register 8Bh). The user also must set the ASEL bit (Table 02h, Register 88h) for this address to be active. By writing the correct slave address with R/W = 0, the master indicates it writes data to the slave. If R/W = 1, the master reads data from the slave. If an incorrect slave address is written, the DS1876 assumes the master is communicating with another I2C device and ignores the communications until the next START condition is sent. Memory Address: During an I2C write operation to the DS1876, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is SDA tBUF tF tLOW SCL tHD:STA tSP tHD:STA tR tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO STOP START NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 12. I2C Timing 20 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface always the second byte transmitted during a write operation following the slave address byte. See Figure 13 for an example of I2C timing. I2C Protocol Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS1876 writes 1 to 8 bytes (one page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). Attempts to write to additional pages of memory without sending a STOP condition between pages result in the address counter wrapping around to the beginning of the present row. TYPICAL I2C WRITE TRANSACTION MSB START X X X X SLAVE ADDRESS* 0 0 1 LSB R/W READ/ WRITE SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 For example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three "consecutive" addresses. The result is that addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time a EEPROM page is written, the DS1876 requires the EEPROM write time (tWR) after the STOP condition to write the contents of the page to EEPROM. During the EEPROM write time, the DS1876 does not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeatedly addressing the DS1876, which allows the next page to be written as soon as the DS1876 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of tWR to elapse before attempting to write again to the DS1876. DS1876 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP REGISTER ADDRESS DATA *IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY. IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED ADDRESS FOR THE MAIN MEMORY IS A0h. EXAMPLE I2C TRANSACTIONS WITH A2h AS THE SLAVE ADDRESS A) SINGLE-BYTE WRITE -WRITE 00h TO REGISTER BAh A2h BAh 00h START 1 0 1 0 0 0 1 0 SLAVE 1 0 1 1 1 0 1 0 SLAVE 0 0 0 0 0 0 0 0 SLAVE ACK ACK ACK A2h BAh START 1 0 1 0 0 0 1 0 SLAVE 1 0 1 1 1 0 1 0 SLAVE ACK ACK STOP B) SINGLE-BYTE READ -READ REGISTER BAh REPEATED START A3h 1 0 1 0 0 0 1 1 SLAVE ACK DATA DATA IN BAh MASTER NACK STOP C) TWO-BYTE WRITE -WRITE 01h AND 75h TO REGISTERS C8h AND C9h A2h C8h 01h 75h START 1 0 1 0 0 0 1 0 SLAVE 1 1 0 0 1 0 0 0 SLAVE 0 0 0 0 0 0 0 1 SLAVE 0 1 1 1 0 1 0 1 SLAVE ACK ACK ACK ACK A2h C8h START 1 0 1 0 0 0 1 0 SLAVE 1 1 0 0 1 0 0 0 SLAVE ACK ACK A3h 1 0 1 0 0 0 1 1 SLAVE ACK DATA STOP DATA MASTER ACK DATA IN C9h MASTER NACK STOP D) TWO-BYTE READ -READ C8h AND C9h REPEATED START DATA IN C8h Figure 13. Example I2C Timing ______________________________________________________________________________________ 21 SFP Controller with Dual LDD Interface EEPROM Write Cycles: When EEPROM writes occur, the DS1876 writes the whole EEPROM memory page, even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page 1 byte at a time wears the EEPROM out 8x faster than writing the entire page at once. The DS1876's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It can handle approximately 10x that many writes at room temperature. Writing to SRAM-shadowed EEPROM memory with SEEB = 1 does not count as a EEPROM write cycle when evaluating the EEPROM's estimated lifetime. Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address pointer to a particular value. To do this, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. DS1876 Table 01h, A2h primarily contains user EEPROM (with PW1 level access) as well as alarm and warning enable bytes. Table 02h, A2h/B2h is a multifunction space that contains configuration registers, scaling and offset values, passwords, and interrupt registers as well as other miscellaneous control bytes. All functions and status can be written and read from either A2h or B2h addresses. Table 04h, A2h contains a temperature-indexed LUT for control of the MOD1 voltage. The MOD1 LUT can be programmed in 2NC increments over the -40NC to +102NC range. This also contains a temperature-indexed LUT for the MOD1 offsets. Table 05h, A2h is empty by default. It can be configured to contain the alarm and warning enable bytes from Table 01h, Registers F8h-FFh with the MASK bit enabled (Table 02h, Register 88h). In this case Table 01h is empty. Table 06h, A2h contains a temperature-indexed LUT for control of the APC1 voltage. The APC1 LUT can be programmed in 2NC increments over the -40NC to +102NC range. This also contains a temperature-indexed LUT for the APC1 offsets. The main device located at B2h is used for transmitter 2 control, calibration, alarms, warnings, and monitoring. Lower Memory, B2h is addressed from 00h-7Fh and contains alarm and warning thresholds, flags, masks, several control registers, PWE, and the table-select byte. Table 01h, B2h contains alarm and warning enable bytes. Table 04h, B2h contains a temperature-indexed LUT for control of the MOD2 voltage. The MOD2 LUT can be programmed in 2NC increments over the -40NC to +102NC range. This also contains a temperature-indexed LUT for the MOD2 offsets. Table 05h, B2h is empty by default. It can be configured to contain the alarm and warning enable bytes from Table 01h, Registers F8h-FFh with the MASK bit enabled (Table 02h, Register 88h). In this case Table 01h is empty. Table 06h, B2h contains a temperature-indexed LUT for control of the APC2 voltage. The APC2 LUT can be programmed in 2NC increments over the -40NC to +102NC range. This also contains a temperature-indexed LUT for the APC2 offsets. Memory Organization The DS1876 features nine separate memory tables that are internally organized into 8-byte rows. The main device located at A2h is used for overall device configuration and transmitter 1 control, calibration, alarms, warnings, and monitoring. Lower Memory, A2h is addressed from 00h-7Fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (PWE), and the table-select byte. 22 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 I2C ADDRESS A0h 00h I2C ADDRESS A2h/B2h 00h LOWER MEMORY PASSWORD ENTRY (PWE) (4 BYTES) TABLE-SELECT BYTE 7Fh NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h/B2h. IF ASEL = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN TABLE 02h, REGISTER 8Bh. NOTE 2: TABLE 00h DOES NOT EXIST. NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE MASK BIT IN TABLE 02h, REGISTER 88h. MAIN DEVICES AT A2h AND B2h EEPROM (256 BYTES) AUXILIARY DEVICE 80h TABLE 01h (A2h ONLY) EEPROM (120 BYTES) F7h F8h ALARMENABLE ROW (8 BYTES) FFh 80h TABLE 02h NONLOOKUP TABLE CONTROL AND CONFIGURATION REGISTERS (B2h ONLY CONTAINS TRANSMITTER 2RELATED REGISTERS) FFh 80h TABLE 04h MOD1 (A2h) MOD2 (B2h) LOOKUP TABLE (72 BYTES) C7h ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING MASK BIT IN TABLE 02h, REGISTER 88h. 80h TABLE 06h APC1 (A2h) APC2 (B2h) LOOKUP TABLE (72 BYTES) C7h E0h (APC1/2, HBATH1/2, TXP HI 1/2, TXP LO 1/2) OFFSET LUT FFh F8h FFh MOD1/2 OFFSET LUT FFh F8h TABLE 05h ALARM-ENABLE ROW (8 BYTES) FFh Figure 14. Memory Map Auxiliary Memory (Device A0h) contains 256 bytes of EE memory accessible from address 00h-FFh. It is selected with the device address of A0h. See the Register Descriptions section for a more complete detail of each byte's function, as well as for read/ write permissions for each byte. Many nonvolatile memory locations (listed within the Register Descriptions section) are actually shadowed EEPROM and are controlled by the SEEB bit in Table 02h, Register 80h. The DS1876 incorporates shadowed EEPROM memory locations for key memory addresses that can be written many times. By default the shadowed EEPROM bit, Shadowed EEPROM SEEB, is not set and these locations act as ordinary EEPROM. By setting SEEB, these locations function like SRAM cells, which allow an infinite number of write cycles without concern of wearing out the EEPROM. This also eliminates the requirement for the EEPROM write time, tWR. Because changes made with SEEB enabled do not affect the EEPROM, these changes are not retained through power cycles. The power-on value is the last value written with SEEB disabled. This function can be used to limit the number of EEPROM writes during calibration or to change the monitor thresholds periodically during normal operation helping to reduce the number of times EEPROM is written. Figure 14 shows the memory map and indicates which locations are shadowed EEPROM. ______________________________________________________________________________________ 23 SFP Controller with Dual LDD Interface DS1876 Register Descriptions The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two memory locations beyond the previous byte/ word's address. A total of 8 bytes are present on each row. For more information about each of these bytes, see the corresponding register description. The following section provides the DS1876 register definitions. Each register or row of registers has an access descriptor that determines the password level required to read or write the memory. Level 2 password is intended for the module manufacture access only. Level 1 password allows another level of protection for items the end consumer wishes to protect. Many registers are always readable, but require password access to write. There are a few registers that cannot be read without password access. The following access codes describe each mode used by the DS1876 with factory settings for the PW_ENA and PW_ENB (Table 02h, Registers C0h- C1h) registers. WRITE ACCESS Memory Map Access Codes ACCESS CODE <0/_> <1/_> <2/_> <3/_> <4/_> <5/_> <6/_> <7/_> <8/_> <9/_> <10/_> <11/_> READ ACCESS At least 1 byte/bit in the row/byte is different than the rest of the row/byte, so look at each byte/bit separately for permissions. Read all Read all Read all Read PW2 Read all Read not applicable Read PW1 Read PW2 Read not applicable Read PW2 Read all Write PW2 Write not applicable Write all, but the DS1876 hardware also writes to these bytes/bits Write PW2 + mode_bit Write all Write all Write PW1 Write PW2 Write PW2 Write not applicable Write PW1 There are three separate I2C addresses in the DS1876: A0h, A2h, and B2h. A2h and B2h are used to configure and monitor two transmitters. Transmitter 1 is accessed MEMORY CODE Memory Addresses A0h, A2h, and B2h using A2h. Transmitter 2 is accessed using B2h. Many of the registers in A2h and B2h are shared registers. These registers can be read and written from both A2h and B2h. A2h AND B2h REGISTERS A common memory location is used for A2h and B2h device addresses. Reading or writing to these locations is identical, regardless of using A2h or B2h addresses. Different memory locations are used for A2h and B2h device addresses. Mixture of common and different memory locations for A2h and B2h device addresses. See the individual bytes within the row for clarification. If "M" is used on an individual byte, see the expanded bit descriptions to determine which bits are common vs. different. 24 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 Lower Memory Register Map LOWER MEMORY ROW (HEX) 00 08 10 18 20-40 48-50 58 60 68 70 78 ROW NAME <1/C> <1/C > <1/D> <1/D> WORD 0 BYTE 0/8 BYTE 1/9 WORD 1 BYTE 2/A BYTE 3/B WORD 2 BYTE 4/C BYTE 5/D BYTE 6/E WORD 3 BYTE 7/F THRESHOLD0 THRESHOLD1 THRESHOLD2 THRESHOLD3 EEPROM EEPROM EEPROM TEMP ALARM HI VCC ALARM HI BMON ALARM HI PMON ALARM HI EE EE EE TEMP ALARM LO VCC ALARM LO BMON ALARM LO PMON ALARM LO EE EE TEMP WARN HI VCC WARN HI BMON WARN HI PMON WARN HI EE EE TEMP WARN LO VCC WARN LO BMON WARN LO PMON WARN LO EE EE EE EE <1/C > <1/D > <1/C > <2/M> <0/M> <5/D> <0/M> EE VALUE EE EE VCC VALUE EE EE VALUE <3/D> ADC VALUES0 ADC VALUES1 ALARM/WARN TABLE SELECT VALUE RESERVED ALARM3 RESERVED ALARM2 RESERVED RESERVED ALARM1 RESERVED RESERVED <6/C> RESERVED WARN3 PWE MSW RESERVED <6/C> UPDATE RESERVED PWE LSW RESERVED <5/D> TBL SEL Table 01h Register Map TABLE 01h ROW (HEX) 80-F7 F8 ROW NAME <1/C> WORD 0 BYTE 0/8 EE WORD 1 BYTE 1/9 EE BYTE 2/A EE WORD 2 BYTE 4/C EE WORD 3 BYTE 6/E EE RESERVED BYTE 7/F EE RESERVED BYTE 3/B EE BYTE 5/D EE EEPROM ENABLE <7/M>ALARM EN3 RESERVED EN1 RESERVED EN3 RESERVED The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h-C1h). These registers also allow for custom permissions. ACCESS CODE Read Access Write Access <0/_> <1/_> All <2/_> All <3/_> All All and DS1876 Hardware <4/_> PW2 PW2 + mode bit <5/_> All <6/_> N/A <7/_> PW1 <8/_> PW2 <9/_> N/A <10/_> PW2 <11/_> All See each bit/byte separately PW2 N/A All All PW1 PW2 PW2 N/A PW1 ______________________________________________________________________________________ 25 SFP Controller with Dual LDD Interface DS1876 Table 02h Register Map TABLE 02h (PW2) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0-FF ROW NAME <0/C> <8/C> WORD 0 BYTE 0/8 <8/C>MODE WORD 1 BYTE 1/9 BYTE 2/A RESERVED CNFGC BYTE 3/B RESERVED DEVICE ADDRESS WORD 2 BYTE 4/C RESERVED RANGING2 BYTE 5/D RESERVED RANGING1 BYTE 6/E <10> WORD 3 BYTE 7/F CONFIG0 CONFIG1 SCALE0 SCALE1 OFFSET0 OFFSET1 <4/C>TINDEX DEVICE ID <10> DEVICE VER RSHIFT1 CNFGA CNFGB RSHIFT2 <8/C> <8/C> <8/C> <8/C> <9/C> <8/C> <8/C> <4/C> RESERVED BMON2 SCALE INTERNAL TEMP OFFSET* BMON2 OFFSET PW1 MSW RESERVED PW_ENA HBIAS2 DAC PW_ENB VCC SCALE PMON2 SCALE VCC OFFSET PMON2 OFFSET PW1 LSW HTXP2 DAC RESERVED LTXP2 DAC RESERVED RESERVED BMON1 SCALE RESERVED BMON1 OFFSET PW2 MSW RESERVED RESERVED HBIAS1 DAC RESERVED RESERVED PMON1 SCALE RESERVED PMON1 OFFSET PW2 LSW HTXP1 DAC POLARITY LTXP1 DAC TBLSELPON PWD VALUE THRESHOLD PWD ENABLE DAC VALUES EMPTY MOD2 DAC EMPTY EMPTY EMPTY APC2 DAC EMPTY EMPTY MOD1 DAC EMPTY EMPTY APC1 DAC EMPTY Table 04h Register Map TABLE 04h (MODULATION LUT) ROW (HEX) 80-C7 C8-F7 F8 <8/D> ROW NAME <8/D> WORD 0 BYTE 0/8 MOD EMPTY MOD OFFSET LUT BYTE 1/9 MOD EMPTY MOD OFFSET LUT WORD 1 BYTE 2/A MOD EMPTY MOD OFFSET LUT BYTE 3/B MOD EMPTY MOD OFFSET LUT WORD 2 BYTE 4/C MOD EMPTY MOD OFFSET LUT BYTE 5/D MOD EMPTY MOD OFFSET LUT BYTE 6/E MOD EMPTY WORD 3 BYTE 7/F MOD EMPTY MOD OFFSET LUT LUT4 EMPTY MOD OFFSET MOD OFFSET LUT The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h-C1h). These registers also allow for custom permissions. ACCESS CODE Read Access Write Access <0/_> <1/_> All <2/_> All <3/_> All All and DS1876 Hardware <4/_> PW2 PW2 + mode bit <5/_> All <6/_> N/A <7/_> PW1 <8/_> PW2 <9/_> N/A <10/_> PW2 <11/_> All See each bit/byte separately PW2 N/A All All PW1 PW2 PW2 N/A PW1 26 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 Table 05h Register Map TABLE 05h ROW (HEX) 80-F7 F8 <7/M> ROW NAME EMPTY ALARM ENABLE WORD 0 BYTE 0/8 EMPTY WORD 1 BYTE 1/9 EMPTY BYTE 2/A EMPTY WORD 2 BYTE 4/C EMPTY WORD 3 BYTE 6/E EMPTY RESERVED BYTE 7/F EMPTY RESERVED BYTE 3/B EMPTY BYTE 5/D EMPTY RESERVED EN3 RESERVED EN1 RESERVED EN3 Table 06h Register Map TABLE 06h (APC LUT) ROW (HEX) 80-C7 C8-DF E0 E8 F0 F8 ROW NAME <8/D> WORD 0 BYTE 0/8 APC LUT EMPTY HBATH LUT HTXP LUT LTXP LUT APC OFFSET LUT BYTE 1/9 APC LUT EMPTY HBATH LUT HTXP LUT LTXP LUT APC OFFSET LUT WORD 1 BYTE 2/A APC LUT EMPTY HBATH LUT HTXP LUT LTXP LUT APC OFFSET LUT BYTE 3/B APC LUT EMPTY HBATH LUT HTXP LUT LTXP LUT APC OFFSET LUT WORD 2 BYTE 4/C APC LUT EMPTY HBATH LUT HTXP LUT LTXP LUT APC OFFSET LUT BYTE 5/D APC LUT EMPTY HBATH LUT HTXP LUT LTXP LUT APC OFFSET LUT BYTE 6/E APC LUT EMPTY WORD 3 BYTE 7/F APC LUT EMPTY HBATH LUT HTXP LUT LTXP LUT APC OFFSET LUT LUT6 EMPTY <8/D> HBATH HTXP LTXP HBATH LUT HTXP LUT LTXP LUT APC OFFSET LUT <8/D> <8/D> <8/D> APC OFFSET Auxiliary Memory A0h Register Map AUXILIARY MEMORY (A0h) ROW (HEX) 00-7F 80-FF ROW NAME <5> <5> WORD 0 BYTE 0/8 EE EE BYTE 1/9 EE EE WORD 1 BYTE 2/A EE EE BYTE 3/B EE EE WORD 2 BYTE 4/C EE EE BYTE 5/D EE EE BYTE 6/E EE EE WORD 3 BYTE 7/F EE EE AUX EE AUX EE The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h-C1h). These registers also allow for custom permissions. ACCESS CODE Read Access Write Access <0/_> <1/_> All <2/_> All <3/_> All All and DS1876 Hardware <4/_> PW2 PW2 + mode bit <5/_> All <6/_> N/A <7/_> PW1 <8/_> PW2 <9/_> N/A <10/_> PW2 <11/_> All See each bit/byte separately PW2 N/A All All PW1 PW2 PW2 N/A PW1 ______________________________________________________________________________________ 27 SFP Controller with Dual LDD Interface DS1876 Lower Memory Register Descriptions Lower Memory, Register 00h-01h: TEMP ALARM HI Lower Memory, Register 04h-05h: TEMP WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 00h, 04h 01h, 05h S 2-1 BIT 7 26 2-2 7FFFh All PW2 or (PW1 and WLOWER) Common A2h and B2h memory location Nonvolatile (SEE) 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0 Temperature measurement updates above this two's complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or below this threshold clear its alarm or warning bit. Lower Memory, Register 02h-03h: TEMP ALARM LO Lower Memory, Register 06h-07h: TEMP WARN LO FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 02h, 06h 03h, 07h S 2-1 BIT 7 26 2-2 8000h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory location Nonvolatile (SEE) 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0 Temperature measurement updates below this two's complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit. 28 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Lower Memory, Register 08h-09h: VCC ALARM HI Lower Memory, Register 0Ch-0Dh: VCC WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 08h, 0Ch 09h, 0Dh 215 27 BIT 7 214 26 FFFFh All PW2 or (PW1 and WLOWER) Common A2h and B2h memory location Nonvolatile (SEE) 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 DS1876 Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit. Lower Memory, Register 0Ah-0Bh: VCC ALARM LO Lower Memory, Register 0Eh-0Fh: VCC WARN LO FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 0Ah, 0Eh 0Bh, 0Fh 215 27 BIT 7 214 26 0000h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory location Nonvolatile (SEE) 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit. ______________________________________________________________________________________ 29 SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 10h-11h: BMON ALARM HI Lower Memory, Register 14h-15h: BMON WARN HI Lower Memory, Register 18h-19h: PMON ALARM HI Lower Memory, Register 1Ch-1Dh: PMON WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 10h, 14h, 18h, 1Ch 11h, 15h, 19h, 1Dh 215 27 BIT 7 214 26 FFFFh All PW2 or (PW1 and WLOWER) Different A2h and B2h memory locations Nonvolatile (SEE) 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit. Lower Memory, Register 12h-13h: BMON ALARM LO Lower Memory, Register 16h-17h: BMON WARN LO Lower Memory, Register 1Ah-1Bh: PMON ALARM LO Lower Memory, Register 1Eh-1Fh: PMON WARN LO FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 12h, 16h, 1Ah, 1Eh 13h, 17h, 1Bh, 1Fh 215 27 BIT 7 214 26 0000h All PW2 or (PW1 and WLOWER) Different A2h and B2h memory locations Nonvolatile (SEE) 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit. 30 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Lower Memory, Register 20h-47h: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 20h-47h EE BIT 7 PW2 level access-controlled EEPROM. EE 00h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory location Nonvolatile (EE) EE EE EE EE EE EE BIT 0 DS1876 Lower Memory, Register 48h-57h: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 48h-57h EE BIT 7 PW2 level access-controlled EEPROM. EE 00h All PW2 or (PW1 and WLOWER) Different A2h and B2h memory locations Nonvolatile (EE) EE EE EE EE EE EE BIT 0 Lower Memory, Register 58h-5Fh: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 58h-5Fh EE BIT 7 PW2 level access-controlled EEPROM. EE 00h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory location Nonvolatile (EE) EE EE EE EE EE EE BIT 0 ______________________________________________________________________________________ 31 SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 60h-61h: TEMP VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 60h 61h S 2-1 BIT 7 Signed two's complement direct-to-temperature measurement. 26 2-2 0000h All N/A Common A2h and B2h memory location Volatile 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0 Lower Memory, Register 62h-63h: VCC VALUE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 62h 63h 215 27 BIT 7 Left-justified unsigned voltage measurement. 214 26 0000h All N/A Common A2h and B2h memory location Volatile 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 32 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Lower Memory, Register 64h-65h: BMON VALUE Lower Memory, Register 66h-67h: PMON VALUE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 64h, 66h 65h, 67h 215 27 BIT 7 Left-justified unsigned voltage measurement. 214 26 0000h All N/A Different A2h and B2h memory locations Volatile 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 DS1876 Lower Memory, Register 68h-6Dh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 68h, 6Dh 0 BIT 7 These registers are reserved. The value when read is 00h. 0 N/A N/A N/A N/A 0 0 0 0 0 0 BIT 0 ______________________________________________________________________________________ 33 SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 6Eh: STATUS POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE Write Access 6Eh N/A X0XX 0XXXb All See below Mixture of common memory locations and different memory locations (see below) Volatile All N/A All All N/A N/A N/A BIT 7 TXDS1 [A2h]: TXD1 status bit. Reflects the logic state of the TXD1 pin (read-only). 0 = TXD1 pin is logic-low. 1 = TXD1 pin is logic-high. TXDS2 [B2h]: TXD2 status bit. Reflects the logic state of the TXD2 pin (read-only). 0 = TXD2 pin is logic-low. 1 = TXD2 pin is logic-high. BIT 0 BIT 7 BIT 6 TXDC1 [A2h]: TXD1 software control bit. This bit allows for software control that is identical to the TXD1 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further information. Its value is wire-ORed with the logic value of the TXD1 pin (writable by all users). 0 = (default) 1 = Forces the device into a TXD1 state regardless of the value of the TXD1 pin. TXDC2 [B2h]: TXD2 software control bit. This bit allows for software control that is identical to the TXD2 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further information. Its value is wire-ORed with the logic value of the TXD2 pin (writable by all users). 0 = (default) 1 = Forces the device into a TXD2 state regardless of the value of the TXD2 pin. IN1S [A2h or B2h]: IN1 status bit. Reflects the logic state of the IN1 pin (read-only). 0 = IN1 pin is logic-low. 1 = IN1 pin is logic-high. RSELS [A2h or B2h]: RSEL status bit. Reflects the logic state of the RSEL pin (read-only). 0 = RSEL pin is logic-low. 1 = RSEL pin is logic-high. RSELC [A2h or B2h]: RSEL software control bit. This bit allows for software control that is identical to the RSEL pin. Its value is wire-ORed with the logic value of the RSEL pin to create the RSELOUT pin's logic value (writable by all users). 0 = (default) 1 = Forces the device into a RSEL state regardless of the value of the RSEL pin. TXFS1 [A2h]: Reflects state of the TXF1 pin (read-only). 0 = TXF1 pin is low. 1 = TXF1 pin is high. TXFS2 [B2h]: Reflects the state of the TXF2 pin (read-only). 0 = TXF2 pin is low. 1 = TXF2 pin is high. RAM1 [A2h]: Volatile memory location. RAM2 [B2h]: Volatile memory location. RDYB [A2h or B2h]: Ready bar. 0 = VCC is above POA. 1 = VCC is below POA and/or too low to communicate over the I2C bus. BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 34 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Lower Memory, Register 6Fh: UPDATE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE TEMP RDY BIT 7 00h All All and DS1876 hardware Different A2h and B2h memory locations Volatile BMON RDY PMON RDY DS1876 6Fh VCC RDY RESERVED RESERVED RESERVED RESERVED BIT 0 BITS 7:4 BITS 3:0 TEMP RDY, VCC RDY, BMON RDY, PMON RDY: Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed. These bits can be cleared so that a completion of a new conversion is verified. RESERVED ______________________________________________________________________________________ 35 SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 70h: ALARM3 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 70h TEMP HI BIT 7 TEMP HI: High alarm status for temperature measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low alarm status for temperature measurement. 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High alarm status for VCC measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. VCC LO: Low alarm status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (default) Last measurement was below threshold setting. BMON HI: High alarm status for BMON measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BMON LO: Low alarm status for BMON measurement. 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. PMON HI: High alarm status for PMON measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. PMON LO: Low alarm status for PMON measurement. 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. TEMP LO 10h All N/A Different A2h and B2h memory locations Volatile VCC HI VCC LO BMON HI BMON LO PMON HI PMON LO BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 36 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Lower Memory, Register 71h: ALARM2 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 71h RESERVED BIT 7 BITS 7:3 BIT 2 RESERVED TXFOUTS: TXFOUT status. Indicates the state the open-drain output is attempting to achieve. 0 = TXFOUT is pulling low. 1 = TXFOUT is high impedance. FETG: Status of internal signal FETG. The FETG signal is part of the internal shutdown logic. 0 = (default) FETG is low. 1 = FETG is high. TXFINT: TXF interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with their corresponding enable bits, plus the wire-ORed logic of HBAL, TXP HI, and TXP LO. The enable bits are found in Table 01h/05h, Registers F8h-FFh. RESERVED 00h All N/A Mixed A2h and B2h memory locations Volatile RESERVED RESERVED RESERVED DS1876 TXFOUTS FETG TXFINT BIT 0 BIT 1 BIT 0 Lower Memory, Register 72h: ALARM1 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 72h RESERVED BIT 7 BITS 7:4, 2 BIT 3 RESERVED HBAL: High bias alarm status; fast comparison. A TXD event clears this alarm. 0 = (default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. TXP HI: High alarm status TXP; fast comparison. A TXD event clears this alarm. 0 = (default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. TXP LO: Low alarm status TXP; fast comparison. A TXD event clears this alarm. 0 = (default) Last comparison was above threshold setting. 1 = Last comparison was below threshold setting. RESERVED 00h All N/A Different A2h and B2h memory locations Volatile RESERVED RESERVED HBAL RESERVED TXP HI TXP LO BIT 0 BIT 1 BIT 0 ______________________________________________________________________________________ 37 SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 73h: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. N/A N/A N/A N/A Lower Memory, Register 74h: WARN3 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 74h TEMP HI BIT 7 TEMP HI: High warning status for temperature measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low warning status for temperature measurement. 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High warning status for VCC measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. VCC LO: Low warning status for VCC measurement. This bit is set when the VCC supply is below the POA trip-point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (default) Last measurement was below threshold setting. BMON HI: High warning status for BMON measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BMON LO: Low warning status for BMON measurement. 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. PMON HI: High warning status for PMON measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. PMON LO: Low warning status for PMON measurement. 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. TEMP LO 10h All N/A Different A2h and B2h memory locations Volatile VCC HI VCC LO BMON HI BMON LO PMON HI PMON LO BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 38 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Lower Memory, Registers 75h-7Ah: RESERVED MEMORY POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE N/A N/A N/A N/A DS1876 These registers are reserved. The value when read is 00h. Lower Memory, Registers 7Bh-7Eh: PASSWORD ENTRY (PWE) POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7Bh 7Ch 7Dh 7Eh 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A All Common A2h and B2h memory location Volatile 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0 There are two passwords for the DS1876. Each password is 4 bytes long. The lower level password (PW1) has all the access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory. At power-up, all PWE bits are set to 1. All reads at this location are 0. ______________________________________________________________________________________ 39 SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 7Fh: TABLE SELECT (TBL SEL) POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7Fh 27 BIT 7 26 TBLSELPON (Table 02h, Register C7h) All All Different A2h and B2h memory locations Volatile 25 24 23 22 21 20 BIT 0 The upper memory tables of the DS1876 are accessible by writing the desired table value in this register. The power-on value of this register is defined by the value written to TBLSELPON (Table 02h, Register C7h). Table 01h Register Descriptions Table 01h, Register 80h-F7h: EEPROM POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 80h-F7h EE BIT 7 EEPROM for PW1 and/or PW2 level access. EE 00h PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A) PW2 or (PW1 and RWTBL1A) Common A2h and B2h memory location Nonvolatile (EE) EE EE EE EE EE EE BIT 0 40 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 01h, Register F8h: ALARM EN3 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE F8h DS1876 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) PW2 or (PW1 and RWTBL1C) Mixture of common memory locations and different memory locations (see the descriptions below) Nonvolatile (SEE) BIT 7 BIT 0 Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. BIT 7 TEMP HI [A2h or B2h]: 0 = Disables interrupt from TEMP HI alarm. 1 = Enables interrupt from TEMP HI alarm. TEMP LO [A2h or B2h]: 0 = Disables interrupt from TEMP LO alarm. 1 = Enables interrupt from TEMP LO alarm. VCC HI [A2h or B2h]: 0 = Disables interrupt from VCC HI alarm. 1 = Enables interrupt from VCC HI alarm. VCC LO [A2h or B2h]: 0 = Disables interrupt from VCC LO alarm. 1 = Enables interrupt from VCC LO alarm. BMON1 HI [A2h]: 0 = Disables interrupt from BMON1 HI alarm. 1 = Enables interrupt from BMON1 HI alarm. BMON2 HI [B2h]: 0 = Disables interrupt from BMON2 HI alarm. 1 = Enables interrupt from BMON2 HI alarm. BMON1 LO [A2h]: 0 = Disables interrupt from BMON1 LO alarm. 1 = Enables interrupt from BMON1 LO alarm. BMON2 LO [B2h]: 0 = Disables interrupt from BMON2 LO alarm. 1 = Enables interrupt from BMON2 LO alarm. PMON1 HI [A2h]: 0 = Disables interrupt from PMON1 HI alarm. 1 = Enables interrupt from PMON1 HI alarm. PMON2 HI [B2h]: 0 = Disables interrupt from PMON2 HI alarm. 1 = Enables interrupt from PMON2 HI alarm. PMON1 LO [A2h]: 0 = Disables interrupt from PMON1 LO alarm. 1 = Enables interrupt from PMON1 LO alarm. PMON2 LO [B2h]: 0 = Disables interrupt from PMON2 LO alarm. 1 = Enables interrupt from PMON2 LO alarm. 41 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ______________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 Table 01h, Register F9h: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. N/A N/A N/A N/A Table 01h, Register FAh: ALARM EN1 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE FAh RESERVED BIT 7 RESERVED 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) PW2 or (PW1 and RWTBL1C) Different A2h and B2h memory locations Nonvolatile (SEE) RESERVED RESERVED HBAL RESERVED TXP HI TXP LO BIT 0 Layout is identical to ALARM1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see Figure 9). The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. BITS 7:4, 2 BIT 3 RESERVED HBAL: Enables alarm to create internal signal FETG. 0 = Disables interrupt from HBAL alarm. 1 = Enables interrupt from HBAL alarm. TXP HI: Enables alarm to create internal signal FETG. 0 = Disables interrupt from TXP HI alarm. 1 = Enables interrupt from TXP HI alarm. TXP LO: Enables alarm to create internal signal FETG. 0 = Disables interrupt from TXP LO alarm. 1 = Enables interrupt from TXP LO alarm. BIT 1 BIT 0 Table 01h, Register FBh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. N/A N/A N/A N/A 42 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 01h, Register FCh: WARN EN3 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE FCh DS1876 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) PW2 or (PW1 and RWTBL1C) Mixture of common memory locations and different memory locations (see the bit descriptions) Nonvolatile (SEE) BIT 7 BIT 0 Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. BIT 7 TEMP HI [A2h or B2h]: 0 = Disables interrupt from TEMP HI warning. 1 = Enables interrupt from TEMP HI warning. TEMP LO [A2h or B2h]: 0 = Disables interrupt from TEMP LO warning. 1 = Enables interrupt from TEMP LO warning. VCC HI [A2h or B2h]: 0 = Disables interrupt from VCC HI warning. 1 = Enables interrupt from VCC HI warning. VCC LO [A2h or B2h]: 0 = Disables interrupt from VCC LO warning. 1 = Enables interrupt from VCC LO warning. BMON1 HI [A2h]: 0 = Disables interrupt from BMON1 HI warning. 1 = Enables interrupt from BMON1 HI warning. BMON1 HI [B2h]: 0 = Disables interrupt from BMON2 HI warning. 1 = Enables interrupt from BMON2 HI warning. BMON1 LO [A2h]: 0 = Disables interrupt from BMON1 LO warning. 1 = Enables interrupt from BMON1 LO warning. BMON2 LO [B2h]: 0 = Disables interrupt from BMON2 LO warning. 1 = Enables interrupt from BMON2 LO warning. PMON1 HI [A2h]: 0 = Disables interrupt from PMON1 HI warning. 1 = Enables interrupt from PMON1 HI warning. PMON2 HI [B2h]: 0 = Disables interrupt from PMON2 HI warning. 1 = Enables interrupt from PMON2 HI warning. PMON1 LO [A2h]: 0 = Disables interrupt from PMON1 LO warning. 1 = Enables interrupt from PMON1 LO warning. PMON2 LO [B2h]: 0 = Disables interrupt from PMON2 LO warning. 1 = Enables interrupt from PMON2 LO warning. 43 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ______________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 Table 01h, Register FDh-FFh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE N/A N/A N/A N/A These registers are reserved. Table 02h Register Descriptions Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 80h SEEB BIT 7 MOD2EN 7Fh PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Volatile QT2EN APC2EN AEN MOD1EN QT1EN APC1EN BIT 0 SEEB: 0 = (default) Enables EEPROM writes to SEE bytes. 1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the SEE locations again for data to be written to the EEPROM. MOD2EN: 0 = MOD2 DAC is writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing the values for MOD2. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for MOD2 DAC. QT2EN: 0 = QTs (HBIAS, TXP HI, TXP LO) for transmitter 2 are writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing to the QT thresholds. The thresholds are updated with the new values at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT QTs for transmitter 2. APC2EN: 0 = APC2 DAC is writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing the values for APC2. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for APC2 DAC. AEN: 0 = The temperature-calculated index value TINDEX is writable by the user and the updates of calculated indexes are disabled. This allows the user to interactively test their modules by controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC registers after the next completion of a temperature conversion. 1 = (default) The temperature-calculated index value TINDEX is used to control the LUTs. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 44 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register 80h: MODE (continued) MOD1EN: 0 = MOD1 DAC is writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing the values for MOD1. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for MOD1 DAC. QT1EN: 0 = QTs (HBIAS, TXP HI, TXP LO) for transmitter 1 are writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing to the QT thresholds. The thresholds are updated with the new values at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT QTs for transmitter 1. APC1EN: 0 = APC1 DAC is writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing the values for APC1. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for APC1 DAC. DS1876 BIT 2 BIT 1 BIT 0 Table 02h, Register 81h: TEMPERATURE INDEX (TINDEX) FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 81h 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and AEN = 0) or (PW1 and RWTBL2 and AEN = 0) Common A2h and B2h memory location Volatile 25 24 23 22 21 20 BIT 0 Holds the calculated index based on the temperature measurement. This index is used for the address during lookup of Tables 04h and 06h. Temperature measurements below -40NC or above +102NC are clamped to 80h and C7h, respectively. The calculation of TINDEX is as follows: TINDEX = Temp_Value + 40C + 80h 2C TINDEX4 TINDEX4 TINDEX3 TINDEX3 TINDEX2 TINDEX2 TINDEX1 TINDEX1 TINDEX0 TINDEX0 For the temperature-indexed LUTs (2NC), the index used during the lookup function for each table is as follows: Table 04h (MOD) Table 06h (APC) 1 1 TINDEX6 TINDEX6 TINDEX5 TINDEX5 For the 8-position LUT tables, the following table shows the lookup function: TINDEX BYTE TEMP (NC) 1000_0xxx F8 < -8 1001_0xxx F9 -8 to +8 1001_1xxx FA +8 to +24 1010_0xxx FB +24 to +40 1010_1xxx FC +40 to +56 1011_0xxx FD +56 to +72 1011_1xxx FE +72 to +88 11xx_xxxx FF R 88 ______________________________________________________________________________________ 45 SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 82h-85h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. N/A N/A N/A N/A Table 02h, Register 86h: DEVICE ID FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 86h 0 BIT 7 Hardwired connections to show the device ID. 1 76h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) N/A ROM 1 1 0 1 1 0 BIT 0 Table 02h, Register 87h: DEVICE VER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 87h BIT 7 Hardwired connections to show the device version. DEVICE VERSION PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) N/A ROM DEVICE VERSION BIT 0 46 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register 88h: CNFGA FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 88h QTHEXT2 BIT 7 QTHEXT1 C0h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) RESERVED ASEL MASK INVRSOUT INVTXFOUT2 INVTXFOUT1 BIT 0 QTHEXT2: QT high extension for transmitter 2. 0 = Disabled. TXP HI and HBIAS QT alarms of transmitter 2 immediately create FETG. 1 = (default) Enabled. TXP HI and HBIAS QT alarms of transmitter 2 do not create FETG until the timeout of the TXDEXT time interval. QTHEXT1: QT high extension for transmitter 1. 0 = Disabled. TXP HI and HBIAS QT alarms of transmitter 1 immediately create FETG. 1 = (default) Enabled. TXP HI and HBIAS QT alarms of transmitter 1 do not create FETG until the timeout of the TXDEXT time interval. RESERVED ASEL: Address select. 0 = (default) Device address is A2h for transmitter 1 and B2h for transmitter 2. 1 = The DEVICE ADDRESS register (Table 02h, Register 8Bh) is used to determine the main device address. MASK: 0 = (default) Alarm-enable row exists at Table 01h, Registers F8h-FFh. Table 05h, Registers F8h- FFh are empty. 1 = Alarm-enable row exists at Table 05h, Registers F8h-FFh. Table 01h, Registers F8h-FFh are empty. INVRSOUT: Allow for inversion of the RSELOUT pin (see Figure 10). 0 = (default) RSELOUT is not inverted. 1 = RSELOUT is inverted. INVTXFOUT2: Allow for inversion of signal driven by the TXF2 input pin. 0 = (default) TXF2 signal is not inverted. 1 = TXF2 signal is inverted. INVTXFOUT1: Allow for inversion of signal driven by the TXF1 input pin. 0 = (default) TXF1 signal is not inverted. 1 = TXF1 signal is inverted. DS1876 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ______________________________________________________________________________________ 47 SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 89h: CNFGB FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 89h IN1C BIT 7 IN1C: IN1 software control bit (see Figure 10). 0 = IN1 pin's logic controls OUT1 pin. 1 = OUT1 is active (bit 6 defines the polarity). INVOUT1: Inverts the active state for OUT1 (see Figure 10). 0 = Noninverted. 1 = Inverted. ALATCH2: ADC alarm's comparison latch for transmitter 2. Latches alarms in Lower Memory, Registers 70h-71h. 0 = ADC alarm and flags reflect the status of the last comparison. 1 = ADC alarm flags remain set. QTLATCH2: QT's comparison latch for transmitter 2. Latches QT alarms in Lower Memory, Registers 72h-73h and 76h. 0 = QT alarm and warning flags reflect the status of the last comparison. 1 = QT alarm and warning flags remain set. WLATCH2: ADC warning's comparison latch for transmitter 2. Latches warnings in Lower Memory, Registers 74h-75h. 0 = ADC warning flags reflect the status of the last comparison. 1 = ADC warning flags remain set. ALATCH1: ADC alarm's comparison latch for transmitter 1. Latches alarms in Lower Memory, Registers 70h-71h. 0 = ADC alarm and flags reflect the status of the last comparison. 1 = ADC alarm flags remain set. QTLATCH1: QT's comparison latch for transmitter 1. Latches QT alarms in Lower Memory, Registers 72h-73h and 76h. 0 = QT alarm and warning flags reflect the status of the last comparison. 1 = QT alarm and warning flags remain set. WLATCH1: ADC warning's comparison latch for transmitter 1. Latches warnings in Lower Memory, Registers 74h-75h. 0 = ADC warning flags reflect the status of the last comparison. 1 = ADC warning flags remain set. INVOUT1 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) ALATCH2 QTLATCH2 WLATCH2 ALATCH1 QTLATCH1 WLATCH1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 48 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register 8Ah: CNFGC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Ah TXDFG2 BIT 7 TXDFG2: See Figure 9. 0 = FETG2, an internal signal, has no effect on TXDOUT2. 1 = FETG2 is enabled and ORed with other possible signals to create TXDOUT2. TXDFLT2: See Figure 9. 0 = TXF2 pin has no effect on TXDOUT2. 1 = TXF2 pin is enabled and ORed with other possible signals to create TXDOUT2. TXDIO2: See Figure 9. 0 = (default) TXD2 input signal is enabled and ORed with other possible signals to create TXDOUT2. 1 = TXD2 input signal has no effect on TXDOUT2. TXDFG1: See Figure 9. 0 = FETG1, an internal signal, has no effect on TXDOUT1. 1 = FETG1 is enabled and ORed with other possible signals to create TXDOUT1. TXDFLT1: See Figure 9. 0 = TXF1 pin has no effect on TXDOUT1. 1 = TXF1 pin is enabled and ORed with other possible signals to create TXDOUT1. TXDIO1: See Figure 9. 0 = (default) TXD1 input signal is enabled and ORed with other possible signals to create TXDOUT1. 1 = TXD1 input signal has no effect on TXDOUT1. RESERVED TXDFLT2 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) TXDIO2 TXDFG1 TXDFLT1 TXDIO1 RESERVED RESERVED BIT 0 DS1876 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BITS 1:0 Table 02h, Register 8Bh: DEVICE ADDRESS FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Bh SEE BIT 7 SEE 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) SEE SEE 23 22 21 SEE BIT 0 This value becomes the I2C slave address for the main memory when the ASEL bit (Table 02h, Register 88h) is set. If A0h is programmed to this register, the auxiliary memory is disabled. For example, writing xxxx_010x makes the main device addresses A4h and B4h. ______________________________________________________________________________________ 49 SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 8Ch: RANGING2 FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Ch RESERVED BIT 7 HBIAS22 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) HBIAS21 HBIAS20 RESERVED TXP22 TXP21 TXP20 BIT 0 The upper nibble of this byte controls the full-scale range of the QT monitoring for BMON2. The lower nibble of this byte controls the full-scale range for the QT monitoring for PMON2. BITS 7, 3 RESERVED (default = 0) HBIAS2[2:0]: HBIAS2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for BMON2. Default is 000b and creates a full scale of 1.25V. HBIAS2[2:0] 000b 001b BITS 6:4 010b 011b 100b 101b 110b 111b % OF 1.25V 100.00 80.03 66.71 50.07 40.08 33.41 28.65 25.08 FS VOLTAGE (V) 1.250 1.000 0.834 0.626 0.501 0.418 0.358 0.314 TXP2[2:0]: TXP2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for PMON2. Default is 000b and creates a full scale of 2.5V. TXP2[2:0] 000b 001b BITS 2:0 010b 011b 100b 101b 110b 111b % OF 2.5V 100.00 80.03 66.71 50.07 40.08 33.41 28.65 25.08 FS VOLTAGE (V) 2.507 2.006 1.672 1.255 1.005 0.838 0.718 0.629 50 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register 8Dh: RANGING1 FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Dh RESERVED BIT 7 HBIAS12 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) HBIAS11 HBIAS10 RESERVED TXP12 TXP11 TXP10 BIT 0 DS1876 The upper nibble of this byte controls the full-scale range of the QT monitoring for BMON1. The lower nibble of this byte controls the full-scale range for the QT monitoring for PMON1. BITS 7, 3 RESERVED (default = 0) HBIAS1[2:0]: HBIAS1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for BMON1. Default is 000b and creates a full scale of 1.25V. HBIAS1[2:0] 000b 001b BITS 6:4 010b 011b 100b 101b 110b 111b % OF 1.25V 100.00 80.03 66.71 50.07 40.08 33.41 28.65 25.08 FS VOLTAGE (V) 1.250 1.000 0.834 0.626 0.501 0.418 0.358 0.314 TXP1[2:0]: TXP1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for PMON1. Default is 000b and creates a full scale of 2.5V. TXP1[2:0] 000b 001b BITS 2:0 010b 011b 100b 101b 110b 111b % OF 2.5V 100.00 80.03 66.71 50.07 40.08 33.41 28.65 25.08 FS VOLTAGE (V) 2.507 2.006 1.672 1.255 1.005 0.838 0.718 0.629 ______________________________________________________________________________________ 51 SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 8Eh: RIGHT-SHIFT2 (RSHIFT2) FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Eh RESERVED BIT 7 BMON22 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) BMON21 BMON20 RESERVED PMON22 PMON21 PMON20 BIT 0 Allows for right-shifting the final answer of BMON2 and PMON2 voltage measurements. This allows for scaling the measurement to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. Table 02h, Register 8Fh: RIGHT-SHIFT1 (RSHIFT1) FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Fh RESERVED BIT 7 BMON12 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) BMON11 BMON10 RESERVED PMON12 PMON11 PMON10 BIT 0 Allows for right-shifting the final answer of BMON1 and PMON1 voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. Table 02h, Register 90h-91h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. N/A N/A N/A N/A 52 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register 92h-93h: VCC SCALE Table 02h, Register 94h-97h: RESERVED Table 02h, RegisteR 98h-99h: BMON2 SCALE Table 02h, Register 9Ah-9Bh: PMON2 SCALE Table 02h, Register 9Ch-9Dh: BMON1 SCALE Table 02h, Register 9Eh-9Fh: PMON1 SCALE FACTORY CALIBRATED READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 92h, 94h, 96h, 98h, 9Ah, 9Ch, 9Eh 93h, 95h, 97h, 99h, 9Bh, 9Dh, 9Fh PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) DS1876 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Controls the scaling or gain of the full-scale voltage measurements. The factory-calibrated value produces an FS voltage of 6.5536V for VCC and 2.5V for BMON2, PMON2, BMON1, and PMON1. Table 02h, Register A0h-A1h: INTERNAL TEMP OFFSET FACTORY CALIBRATED READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE A0h A1h S 21 BIT 7 28 20 PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) 27 2-1 26 2-2 25 2-3 24 2-4 23 2-5 22 2-6 BIT 0 Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius. ______________________________________________________________________________________ 53 SFP Controller with Dual LDD Interface DS1876 Table 02h, Register A2h-A3h: VCC OFFSET Table 02h, Register A4h-A7h: RESERVED Table 02h, Register A8h-A9h: BMON2 OFFSET Table 02h, Register AAh-ABh: PMON2 OFFSET Table 02h, Register ACh-ADh: BMON1 OFFSET Table 02h, Register AEh-AFh: PMON1 OFFSET FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE A2h, A4h, A6h, A8h, AAh, ACh, AEh A3h, A5h, A7h, A9h, ABh, ADh, AFh 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) S S 215 214 213 212 211 210 29 28 27 26 25 24 23 22 BIT 7 Allows for offset control of these voltage measurements if desired. This number is two's complement. BIT 0 Table 02h, Register B0h-B3h: PW1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B0h B1h B2h B3h 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A PW2 or (PW1 and WPW1) Nonvolatile (SEE) 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0 The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without writing the password entry. All reads of this register are 00h. 54 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register B4h-B7h: PW2 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B4h B5h B6h B7h 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A PW2 Nonvolatile (SEE) 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0 DS1876 The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-on without writing the password entry. All reads of this register are 00h. Table 02h, Register B8h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. N/A N/A N/A N/A Table 02h, Register B9h: HBIAS2 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE B9h 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) Common A2h and B2h memory location Volatile 25 24 23 22 21 20 BIT 0 The digital value used for the HBIAS2 reference and recalled from Table 06h (Registers E0h-E7h) (transmitter 2) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons greater than VHBIAS2 compared against VBMON2 create an HBAL alarm. VHBIAS2 = Full Scale x HBIAS2 DAC 256 ______________________________________________________________________________________ 55 SFP Controller with Dual LDD Interface DS1876 Table 02h, Register BAh: HTXP2 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BAh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) Common A2h and B2h memory location Volatile 25 24 23 22 21 20 BIT 0 The digital value used for the HTXP2 reference and recalled from Table 06h (Registers E8h-EFh) (transmitter 2) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons greater than VHTXP2 compared against VPMON2 create a TXP HI alarm. VHTXP2 = Full Scale x HTXP2 DAC 256 Table 02h, Register BBh: LTXP2 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BBh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) Common A2h and B2h memory location Volatile 25 24 23 22 21 20 BIT 0 The digital value used for the LTXP2 reference and recalled from Table 06h (Registers F0h-F7h) (transmitter 2) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons less than VLTXP2 compared against VPMON2 create a TXP LO alarm. VLTXP2 = Full Scale x LTXP2 DAC 256 Table 02h, Register BCh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. N/A N/A N/A N/A 56 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register BDh: HBIAS1 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BDh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0) Common A2h and B2h memory location Volatile 25 24 23 22 21 20 BIT 0 DS1876 The digital value used for the HBIAS1 reference and recalled from Table 06h (Registers E0h-E7h) (transmitter 1) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons greater than VHBIAS1 compared against VBMON1 create an HBAL alarm. VHBIAS1 = Full Scale x HBIAS1 DAC 256 Table 02h, Register BEh: HTXP1 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BEh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0) Common A2h and B2h memory location Volatile 25 24 23 22 21 20 BIT 0 The digital value used for the HTXP1 reference and recalled from Table 06h (Registers E8h-EFh) (transmitter 1) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons great than VHTXP1 compared against VPMON1 create a TXP HI alarm. VHTXP1 = Full Scale x HTXP1 DAC 256 Table 02h, Register BFh: LTXP1 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BFh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0) Common A2h and B2h memory location Volatile 25 24 23 22 21 20 BIT 0 The digital value used for the LTXP1 reference and recalled from Table 06h (Registers F0h-F7h) (transmitter 1) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons less than VLTXP1 compared against VPMON1 create a TXP LO alarm. VLTXP1 = Full Scale x LTXP1 DAC 256 57 ______________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 Table 02h, Register C0h: PW_ENA FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C0h RESERVED BIT 7 BIT 7 RESERVED RWTBL1C: Table 01h or 05h bytes F8-FFh. Table address is dependent on MASK bit (Table 02h, Register 88h). 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. RWTBL2: Table 02h. Writing a nonvolatile value to this bit requires PW2 access. 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. RWTBL1A: Table 01h, Registers 80h-BFh. 0 = Read and write access for PW2 only. 1 = (default) Read and write access for both PW1 and PW2. RWTBL1B: Table 01h, Registers C0h-F7h. 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. WLOWER: Bytes 00h-5Fh in main memory. All users can read this area. 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. WAUXA: Auxiliary memory, Registers 00h-7Fh. All users can read this area. 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. WAUXB: Auxiliary memory, Registers 80h-FFh. All users can read this area. 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. RWTBL1C 10h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) RWTBL2 RWTBL1A RWTBL1B WLOWER WAUXA WAUXB BIT 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 58 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register C1h: PW_ENB FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C1h RWTBL46 BIT 7 RWTBL46: Tables 04h and 06h. 0 = (default) Read and write access for PW2 only. 1 = Read and write access for PW1 and PW2. RTBL1C: Table 01h or Table 05h, Registers F8h-FFh. Table address is dependent on MASK bit (Table 02h, Register 88h). 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL2: Table 02h. 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL1A: Table 01h, Registers 80h-BFh. 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL1B: Table 01h, Registers C0h-F7h. 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. WPW1: Register PW1 (Table 02h, Registers B0h-B3h). For security purposes these registers are not readable. 0 = (default) Write access for PW2 only. 1 = Write access for PW1 and PW2. WAUXAU: Auxiliary memory, Registers 00h-7Fh. All users can read this area. 0 = Write access for PW2 only. 1 = (default) Write access for user, PW1, and PW2. WAUXBU: Auxiliary memory, Registers 80h-FFh. All users can read this area. 0 = Write access for PW2 only. 1 = (default) Write access for user, PW1, and PW2. RTBL1C 03h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) RTBL2 RTBL1A RTBL1B WPW1 WAUXAU WAUXBU BIT 0 DS1876 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Table 02h, Register C2h-C5h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. N/A N/A N/A N/A ______________________________________________________________________________________ 59 SFP Controller with Dual LDD Interface DS1876 Table 02h, Register C6h: POLARITY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C6h RESERVED BIT 7 BITS 7:4 RESERVED MOD2P: MOD2 DAC polarity. The MOD2 DAC (Table 02h, Registers C8h-C9h) range is 000h-3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of MOD2 DAC is 000h; thus an application that needs VREFIN to be the off state should use the inverted polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. APC2P: APC2 DAC polarity. The APC2 DAC (Table 02h, Registers CAh-CBh) range is 000h-3FFh. A setting of 000h creates a pulse-density of zero, and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of APC DAC is 000h; thus an application that needs VREFIN to be the off state should use the inverted polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. MOD1P: MOD1 DAC polarity. The MOD1 DAC (Table 02h, Registers CCh-CDh) range is 000h-3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of MOD1 DAC is 000h; thus an application that needs VREFIN to be the off state should use the inverted polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. APC1P: APC1 DAC polarity. The APC1 DAC (Table 02h, Registers CEh-CFh) range is 000h-3FFh. A setting of 000h creates a pulse-density of zero, and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of APC1 DAC is 000h; thus an application that needs VREFIN to be the off state should use the inverted polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. RESERVED 0Fh PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) RESERVED RESERVED MOD2P APC2P MOD1P APC1P BIT 0 BIT 3 BIT 2 BIT 1 BIT 0 60 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register C7h: TBLSELPON FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C7h 27 BIT 7 Chooses the initial value for the TBL SEL byte (Lower Memory, Register 7Fh) at power-on. 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0 DS1876 Table 02h, Register C8h-C9h: MOD2 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C8h C9h 0 27 BIT 7 0 26 0000h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and MOD2EN = 0) or (PW1 and RWTBL2 and MOD2EN = 0) Common A2h and B2h memory location Volatile 0 25 0 24 0 23 0 22 29 21 28 20 BIT 0 The digital value used for MOD2 DAC. It is the result of LUT4 plus MOD2 OFFSET times 4 recalled from Table 04h (Registers F8h-FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. MOD2 DAC = LUT4 + MOD2 OFFSET x 4 V VMOD2 = REFIN x MOD2 DAC 1024 ______________________________________________________________________________________ 61 SFP Controller with Dual LDD Interface DS1876 Table 02h, Register CAh-CBh: APC2 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE CAh CBh 0 27 BIT 7 0 26 0000h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and APC2EN = 0) or (PW1 and RWTBL2 and APC2EN = 0) Common A2h and B2h memory location Volatile 0 25 0 24 0 23 0 22 29 21 28 20 BIT 0 The digital value used for APC2 DAC. It is the result of LUT6 plus APC2 OFFSET times 4 recalled from Table 06h (Registers F8h-FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. APC2 DAC = LUT6 + APC2 OFFSET x 4 V VAPC2 = REFIN x APC2 DAC 1024 Table 02h, Register CCh-CDh: MOD1 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE CCh CDh 0 27 BIT 7 0 26 0000h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and MOD1EN = 0) or (PW1 and RWTBL2 and MOD1EN = 0) Common A2h and B2h memory location Volatile 0 25 0 24 0 23 0 22 29 21 28 20 BIT 0 The digital value used for MOD1 DAC. It is the result of LUT4 plus MOD1 OFFSET times 4 recalled from Table 04h (Registers F8h-FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. MOD1 DAC = LUT4 + MOD1 OFFSET x 4 V VMOD1 = REFIN x MOD1 DAC 1024 62 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 02h, Register CEh-CFh: APC1 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE CEh CFh 0 27 BIT 7 0 26 0000h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and APC1EN = 0) or (PW1 and RWTBL2 and APC1EN = 0) Common A2h and B2h memory location Volatile 0 25 0 24 0 23 0 22 29 21 28 20 BIT 0 DS1876 The digital value used for APC1 DAC. It is the result of LUT6 plus APC1 OFFSET times 4 recalled from Table 06h (Registers F8h-FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. APC1 DAC = LUT6 + APC1 OFFSET x 4 V VAPC1 = REFIN x APC1 DAC 1024 Table 02h, Register D0h-FFh: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers do not exist. 00h N/A N/A N/A None ______________________________________________________________________________________ 63 SFP Controller with Dual LDD Interface DS1876 Table 04h Register Descriptions Table 04h, Register 80h-C7h: MODULATION LUT (MOD) FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 80h-C7h 27 BIT 7 26 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 Digital value for the MOD1 DAC (A2h address) and MOD2 DAC (B2h address) outputs. The MODULATION LUT is a set of registers assigned to hold the temperature profile for the MOD1 and MOD2 DACs. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2NC increments from -40NC to +102NC, starting at 80h in Table 04h. Register 80h defines the -40NC to -38NC MOD output, Register 81h defines -38NC to -36NC MOD output, and so on. Values recalled from this EEPROM memory table are written into the MOD1 and MOD2 DACs (Table 02h, Registers C8h-C9h, CCh-CDh) locations that hold the values until the next temperature conversion. The part can be placed into a manual mode (MOD1EN and MOD2EN bits, Table 02h, Register 80h), where MOD1 and MOD2 DACs are directly controlled for calibration. If the temperature compensation functionality is not required, program the entire Table 04h to the desired modulation setting. Table 02h, Register C8h-F7h: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers do not exist. 00h N/A N/A N/A None 64 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 04h, Register F8h-FFh: MOD OFFSET LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE F8h-FFh 29 BIT 7 The digital value for the temperature offset of the MOD1 and MOD2 DAC outputs. F8h F9h FAh FBh FCh FDh FEh FFh Less than or equal to -8NC Greater than -8NC up to +8NC Greater than +8NC up to +24NC Greater than +24NC up to +40NC Greater than +40NC up to +56NC Greater than +56NC up to +72NC Greater than +72NC up to +88NC Greater than +88NC 28 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 27 26 25 24 23 22 BIT 0 DS1876 The MOD DAC is a 10-bit value. The MODULATION LUT is an 8-bit LUT. The MOD OFFSET LUT times 4 plus the MODULATION LUT makes use of the entire 10-bit range. Table 06h Register Descriptions Table 06h, Register 80h-C7h: APC LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 80h-C7h 27 BIT 7 26 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 The digital value for the APC1 DAC (A2h address) and APC2 DAC (B2h address) outputs. The APC LUT is a set of registers assigned to hold the temperature profile for the APC1 and APC2 DACs. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2NC increments from -40NC to +102NC, starting at 80h. Register 80h defines the -40NC to -38NC APC output, Register 81h defines -38NC to -36NC APC output, and so on. Values recalled from this EEPROM memory table are written into the APC1 and APC2 DACs (Table 02h, Registers CAh-CBh, CEh-CFh) locations that hold the values until the next temperature conversion. The part can be placed into a manual mode (APC1EN and APC2EN bits, Table 02h, Register 80h), where APC1 and APC2 DACs are directly controlled for calibration. If the temperature compensation functionality is not required, program the entire Table 06h to the desired APC setting. ______________________________________________________________________________________ 65 SFP Controller with Dual LDD Interface DS1876 Table 06h, Register C8h-DFh: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers do not exist. 00h N/A N/A N/A None Table 06h, Register E0h-E7h: HBATH LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE E0h-E7h 27 BIT 7 26 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 The high bias alarm threshold (HBATH) LUT is used to temperature compensate the bias QT threshold (HBIAS). The table below shows the range of temperature for each byte's location. The table shows a rising temperature; for a falling temperature there is 1NC of hysteresis. E0h E1h E2h E3h E4h E5h E6h E7h Less than or equal to -8NC Greater than -8NC up to +8NC Greater than +8NC up to +24NC Greater than +24NC up to +40NC Greater than +40NC up to +56NC Greater than +56NC up to +72NC Greater than +72NC up to +88NC Greater than +88NC 66 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface Table 06h, Register E8h-EFh: HTXP LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE E8h-EFh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 DS1876 The HTXP LUT is used to temperature compensate the transmit power-high QT threshold (TXP HI). The table below shows the range of temperature for each byte's location. The table shows a rising temperature; for a falling temperature there is 1NC of hysteresis. E8h E9h EAh EBh ECh EDh EEh EFh Less than or equal to -8NC Greater than -8NC up to +8NC Greater than +8NC up to +24NC Greater than +24NC up to +40NC Greater than +40NC up to +56NC Greater than +56NC up to +72NC Greater than +72NC up to +88NC Greater than +88NC Table 06h, Register F0h-F7h: LTXP LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE F0h-F7h 27 BIT 7 26 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 The LTXP LUT is used to temperature compensate the transmit power-low QT threshold (TXP LO). The table below shows the range of temperature for each byte's location. The table shows a rising temperature; for a falling temperature there is 1NC of hysteresis. F0h F1h F2h F3h F4h F5h F6h F7h Less than or equal to -8NC Greater than -8NC up to +8NC Greater than +8NC up to +24NC Greater than +24NC up to +40NC Greater than +40NC up to +56NC Greater than +56NC up to +72NC Greater than +72NC up to +88NC Greater than +88NC ______________________________________________________________________________________ 67 SFP Controller with Dual LDD Interface DS1876 Table 06h, Register F8h-FFh: APC OFFSET LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE F8h-FFh 29 BIT 7 The digital value for the temperature offset of the APC1 and APC2 DAC outputs. F8h F9h FAh FBh FCh FDh FEh FFh Less than or equal to -8NC Greater than -8NC up to +8NC Greater than +8NC up to +24NC Greater than +24NC up to +40NC Greater than +40NC up to +56NC Greater than +56NC up to +72NC Greater than +72NC up to +88NC Greater than +88NC 28 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 27 26 25 24 23 22 BIT 0 The APC DAC is a 10-bit value. The APC LUT is an 8-bit LUT. The APC OFFSET LUT times 4 plus the APC LUT makes use of the entire 10-bit range. Auxiliary Memory A0h Register Descriptions Auxiliary Memory A0h, Register 00h-7Fh: EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h-7Fh 27 BIT 7 Accessible with the slave address A0h. 26 00h All PW2 or (PW1 and WAUXA) or (WAUXAU) Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 68 _____________________________________________________________________________________ SFP Controller with Dual LDD Interface DS1876 Auxiliary Memory A0h, Register 80h-FFh: EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 80h-FFh 27 BIT 7 Accessible with the slave address A0h. 26 00h All PW2 or (PW1 and WAUXB) or (WAUXBU) Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 Applications Information To achieve best results, it is recommended that the power supply is decoupled with a 0.01FF or a 0.1FF capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins to minimize lead inductance. SDA is an open-collector output on the DS1876 that requires a pullup resistor to realize high logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I2C AC Electrical Characteristics table are within specification. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 28 TQFN-EP PACKAGE CODE T2855+6 DOCUMENT NO. 21-0140 Power-Supply Decoupling SDA and SCL Pullup Resistors Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 69 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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