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| MC74VHC4316 Quad Analog Switch/ Multiplexer/Demultiplexer with Separate Analog and Digital Power Supplies High-Performance Silicon-Gate CMOS The MC74VHC4316 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF-channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full analog power-supply range (from VCC to VEE). The VHC4316 is similar in function to the metal-gate CMOS MC14016 and MC14066, and to the High-Speed CMOS HC4066A. Each device has four independent switches. The device control and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. Logic-level translators are provided so that the On/Off Control and Enable logic-level voltages need only be VCC and GND, while the switch is passing signals ranging between VCC and VEE. When the Enable pin (active-low) is high, all four analog switches are turned off. Features http://onsemi.com MARKING DIAGRAMS 16 16 1 SOIC-16 D SUFFIX CASE 751B 1 16 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package VHC 4316 ALYWG G VHC4316G AWLYWW (Note: Microdot may be in either location) * * * * * * * * * Logic-Level Translator for On/Off Control and Enable Inputs Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Diode Protection on All Inputs/Outputs Analog Power-Supply Voltage Range (VCC - VEE) = 2.0 to 12.0 V Digital (Control) Power-Supply Voltage Range (VCC - GND) = 2.0 V to 6.0 V, Independent of VEE Improved Linearity of ON Resistance Chip Complexity: 66 FETs or 16.5 Equivalent Gates These are Pb-Free Devices ORDERING INFORMATION Device MC74VHC4316DG MC74VHC4316DR2G Package SOIC-16 (Pb-Free) Shipping 48 Units / Rail SOIC-16 2500/Tape&Reel (Pb-Free) TSSOP16 (Pb-Free) 96 Units / Rail MC74VHC4316DTG MC74VHC4316DTR2G TSSOP16 2500/Tape&Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2008 1 March, 2008 - Rev. 2 Publication Order Number: MC74VHC4316/D MC74VHC4316 XA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL ENABLE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC VEE FUNCTION TABLE Inputs Enable L L H X = Don't Care. On/Off Control H L X State of Analog Switch On Off Off Figure 1. Pin Assignment 1 15 LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG SWITCH LEVEL TRANSLATOR ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD 12 YD 11 YC 3 YB ANALOG OUTPUTS/INPUTS PIN 16 = VCC PIN 8 = GND PIN 9 = VEE GND VEE ANALOG SWITCH 2 XA A ON/OFF CONTROL YA XB B ON/OFF CONTROL 4 5 XC C ON/OFF CONTROL 10 6 XD D ON/OFF CONTROL ENABLE 13 14 7 Figure 2. Logic Diagram http://onsemi.com 2 MC74VHC4316 MAXIMUM RATINGS Symbol VCC VEE VIS Vin I PD Tstg TL Parameter Positive DC Supply Voltage (Ref. to GND) (Ref. to VEE) Value - 0.5 to + 7.0 - 0.5 to + 14.0 - 7.0 to + 0.5 VEE - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 25 SOIC Package* TSSOP Package* 500 450 - 65 to + 150 260 Unit V V V V mA mW C C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance cir cuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. Negative DC Supply Voltage (Ref. to GND) Analog Input Voltage DC Input Voltage (Ref. to GND) DC Current Into or Out of Any Pin Power Dissipation in Still Air Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (SOIC or TSSOP Package) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *Derating - SOIC Package: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC VEE VIS Vin VIO* TA tr, tf Parameter Positive DC Supply Voltage (Ref. to GND) Negative DC Supply Voltage (Ref. to GND) Analog Input Voltage Digital Input Voltage (Ref. to GND) Static or Dynamic Voltage Across Switch Operating Temperature, All Package Types Input Rise and Fall Time (Control or Enable Inputs) (Figure 10) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V Min 2.0 - 6.0 VEE GND - 55 0 0 0 0 Max 6.0 GND VCC VCC 1.2 + 125 1000 600 500 400 Unit V V V V V C ns *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. http://onsemi.com 3 MC74VHC4316 DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted Guaranteed Limit Symbol VIH Parameter Minimum High-Level Voltage, Control or Enable Inputs Test Conditions Ron = Per Spec VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 - 55 to 25C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 0.1 v 85C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.0 v 125C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.0 Unit V VIL Maximum Low-Level Voltage, Control or Enable Inputs Ron = Per Spec V Iin ICC Maximum Input Leakage Current, Control or Enable Inputs Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VEE = - 6.0 V Vin = VCC or GND VIO = 0 V VEE = GND VEE = - 6.0 mA mA 6.0 6.0 2 4 20 40 40 160 NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE) Guaranteed Limit Symbol Ron Parameter Maximum "ON" Resistance Test Conditions Vin = VIH VIS = VCC to VEE IS v 2.0 mA Vin = VIH VIS = VCC or VEE (Endpoints) IS v 2.0 mA DRon Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum Off-Channel Leakage Current, Any One Channel Maximum On-Channel Leakage Current, Any One Channel Vin = VIH VIS = 1/2 (VCC - VEE) IS v 2.0 mA Vin = VIL VIO = VCC or VEE Switch Off (Figure 3) Vin = VIH VIS = VCC or VEE (Figure 4) VCC V 2.0* 45 4.5 6.0 2.0 4.5 4.5 6.0 2.0 4.5 4.5 6.0 6.0 VEE V - 55 to 25C 160 90 90 90 70 70 20 15 15 0.1 v 85C 200 110 110 115 90 90 25 20 20 0.5 v 125C 240 130 130 140 105 105 30 25 25 1.0 Unit W 0.0 0.0 - 4.5 - 6.0 0.0 0.0 - 4.5 - 6.0 0.0 0.0 - 4.5 - 6.0 - 6.0 W Ioff mA Ion 6.0 - 6.0 0.1 0.5 1.0 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). *At supply voltage (VCC - VEE) approaching 2.0 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals. http://onsemi.com 4 MC74VHC4316 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND) Guaranteed Limit Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH C Parameter Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) Maximum Capacitance ON/OFF Control and Enable Inputs VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25C 40 6 5 130 40 30 140 40 30 10 v 85C 50 8 7 160 50 40 175 50 40 10 v 125C 60 9 8 200 60 50 250 60 50 10 Unit ns ns ns pF Control Input = GND Analog I/O 35 35 35 Feedthrough 1.0 1.0 1.0 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 15 Power Dissipation Capacitance (Per Switch) (Figure 13)* pF CPD *Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol BW Parameter Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) Off-Channel Feedthrough Isolation (Figure 6) Test Conditions fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 W, CL = 10 pF fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF VCC V 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 VEE V - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 Limit* 25C 150 160 160 - 50 - 50 - 50 - 40 - 40 - 40 60 130 200 30 65 100 - 70 - 70 - 70 - 80 - 80 - 80 % 2.25 4.50 6.00 - 2.25 - 4.50 - 6.00 0.10 0.06 0.04 dB mVPP Unit MHz - dB - Feedthrough Noise, Control to Switch (Figure 7) Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 W, CL = 50 pF RL = 10 kW, CL = 10 pF - Crosstalk Between Any Two Switches (Figure 12) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF THD Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave *Limits not tested. Determined by design and verified by qualification. http://onsemi.com 5 MC74VHC4316 PLOTTER PROGRAMMABLE POWER SUPPLY + MINI COMPUTER DC ANALYZER VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND VEE Figure 1. On Resistance Test Set-Up http://onsemi.com 6 MC74VHC4316 VCC VEE VCC A OFF 16 VCC VCC A O/I VEE ON 16 VCC N/C VIL 7 8 9 VEE SELECTED CONTROL INPUT VEE 7 8 9 SELECTED CONTROL INPUT VIH Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 3. Maximum On Channel Leakage Current, Test Set-Up VIS VCC 16 fin 0.1 mF ON RL VCC SELECTED CONTROL INPUT VEE *Includes all probe and jig capacitance. CL* VCC RL 16 TO dB METER fin 0.1 mF RL OFF RL CL* TO dB METER VCC 7 8 9 VEE 7 8 9 SELECTED CONTROL INPUT *Includes all probe and jig capacitance. Figure 4. Maximum On-Channel Bandwidth Test Set-Up Figure 5. Off-Channel Feedthrough Isolation, Test Set-Up VCC 16 TEST POINT RL SELECTED CONTROL INPUT CL* ANALOG IN tPLH 50% GND tPHL ON/OFF RL 7 8 9 VEE CONTROL *Includes all probe and jig capacitance. VCC ANALOG OUT 50% Figure 6. Feedthrough Noise, Control to Analog Out, Test Set-Up Figure 7. Propagation Delays, Analog In to Analog Out http://onsemi.com 7 MC74VHC4316 VCC 16 ANALOG I/O ON 50 pF* ANALOG O/I TEST POINT ENABLE 50% CONTROL tPZL 7 8 9 SELECTED CONTROL INPUT VCC ANALOG OUT 50% tPZH 50% *Includes all probe and jig capacitance. tPHZ 10% 90% tPLZ GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE tr tf VCC Figure 8. Propagation Delay Test Set-Up Figure 9. Propagation Delay, ON/OFF Control to Analog Out POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 CONTROL OR ENABLE 8 9 VEE ON/OFF 50 pF* POSITION 2 WHEN TESTING tPLZ AND tPZL RL VCC 16 1 kW TEST POINT fin 0.1 mF VIS VCC 16 ON CL* ANALOG I/O OFF 7 8 9 RL VCC SELECTED CONTROL INPUT CL* TEST POINT RL *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 10. Propagation Delay Test Set-Up Figure 11. Crosstalk Between Any Two Switches, Test Set-Up (Adjacent Channels Used) VCC A 16 N/C ON/OFF N/C 10 mF fin ON RL 7 8 9 VEE CONTROL CL* VIS VCC 16 VOS TO DISTORTION METER SELECTED CONTROL INPUT VEE 7 8 9 SELECTED CONTROL INPUT VCC *Includes all probe and jig capacitance. Figure 12. Power Dissipation Capacitance Test Set-Up Figure 13. Total Harmonic Distortion, Test Set-Up http://onsemi.com 8 MC74VHC4316 APPLICATIONS INFORMATION 0 - 10 - 20 - 30 dBm - 40 - 50 - 60 - 70 - 80 - 90 - 100 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY Figure 14. Plot, Harmonic Distortion The Enable and Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or VEE through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In the example below, the difference between VCC and VEE is 12 V. Therefore, using the configuration in Figure 15, a maximum analog signal of twelve volts peak-to-peak can be controlled. When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 16. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOSORBs (MOSORBt is an acronym for high current surge protectors). MOSORBs are fast turn-on devices ideally suited for precise dc protection with no inherent wear out mechanism. VCC = 6 V +6V -6 V +6V SELECTED CONTROL INPUT VEE 8 -6 V 16 ANALOG I/O ON ANALOG O/I +6V -6 V Dx VCC 16 ON Dx VCC SELECTED CONTROL INPUT VEE VCC Dx Dx VEE ENABLE CONTROL INPUTS (VCC OR GND) ENABLE CONTROL INPUTS (VCC OR GND) VEE Figure 15. Figure 16. Transient Suppressor Application http://onsemi.com 9 MC74VHC4316 VCC = 5 V +5 V ANALOG SIGNALS R* R* R* R* R* 16 ANALOG SIGNALS ANALOG SIGNALS HCT BUFFER LSTTL/ NMOS 5 6 14 15 16 ANALOG SIGNALS VHC4316 TTL 7 5 6 14 15 R* = 2 TO 10 kW ENABLE AND CONTROL 9 INPUTS 8 VEE = 0 TO - 6 V HC4016A VEE = 0 TO - 6 V CONTROL INPUTS 9 7 a. Using Pull-Up Resistors b. Using HCT Buffer Figure 17. LSTTL/NMOS to HCMOS Interface VCC = 12 V 12 V POWER SUPPLY R1 GND = 6 V R2 VEE = 0 V R1 = R2 VCC ANALOG INPUT SIGNAL C R3 R4 VEE R1 = R2 R3 = R4 ANALOG OUTPUT SIGNAL 12 V 0 12 VPP 1 OF 4 SWITCHES Figure 18. Switching a 0-to-12 V Signal Using a Single Power Supply (GND 0 V) CHANNEL 4 1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES INPUT 1 OF 4 SWITCHES + 0.01 mF 1 2 34 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT CHANNEL 3 CHANNEL 2 CHANNEL 1 Figure 19. 4-Input Multiplexer Figure 20. Sample/Hold Amplifier http://onsemi.com 10 MC74VHC4316 PACKAGE DIMENSIONS SOIC-16 D SUFFIX CASE 751B-05 ISSUE K -ANOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 -B1 8 P 8 PL 0.25 (0.010) M B S G F K C -TSEATING PLANE R X 45 _ M D 16 PL M J DIM A B C D F G J K M P R 0.25 (0.010) TB S A S SOLDERING FOOTPRINT 8X 6.40 16X 1.12 16 1 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 11 MC74VHC4316 PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 2X L/2 16 9 J1 B -U- SECTION N-N J N L PIN 1 IDENT. 1 8 0.25 (0.010) M 0.15 (0.006) T U S A -V- N F DETAIL E C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 -WJ 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT 7.06 1 16X 0.36 16X 1.26 MOSORB is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 12 EEE CCC EEE CCC 0.65 PITCH DIMENSIONS: MILLIMETERS MC74VHC4316/D |
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