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Features
* Power Management
- Supply Input from USB or 1x Disposal Battery (Alkaline, NimH, NiCd) - Input Voltage Range: 0.9V to 1.8V - 2.7V/2.9V/3.1V/3.3V - 100 mA Step-Up DC/DC Converter for Main Supply - 2.7V to 3.5V (100mV step) - 150 mA LDO from USB supply - 2.4V to 3.0V (200mV step) - 60 mA LDO for Analog Supply - Reset Generator - SPI Interface and Internal Programming Registers - Dynamic Power Management - Very Low Quiescent Current Operation * Stereo Audio DAC - Programmable Stereo Audio DAC (16-bits, 18-bits or 20-bits) - 93 dB SNR Playback Stereo Channels - 32 Ohm/20 mW Stereo Headset Drivers with Master Volume and Mute Controls - Stereo Line Level Input with Volume Control/Mute and Playback through the Headset Driver - Microphone Preamplifier - Stereo, Mono and Reverse Stereo Mixer - Left/Right Speaker Short-Circuit Detection Flag - 8, 11.024, 16, 22.05, 24, 32, 44.1 and 48 kHz Sampling Rates - 256x or 384xFs Master Clock Frequency - I2S Serial Audio Interface - Low Power Operation * Applications: - Ideally Suited to Interface with Atmel's AT8xC51SNDxC MP3 Microcontroller - Portable Music Players, Digital Cameras, CD Players, Handheld GPS
Power Management and Analog Companions (PMAAC) AT73C209 Audio and Power Management
1. Description
The AT73C209 is a fully integrated, low cost, combined Stereo Audio DAC and Power Management Circuit targeted for battery powered devices such as MP3 players in "walkman" format or "mass storage" USB format. The stereo DAC section is a complete high performance, stereo audio digital-to-analog converter delivering a 93 dB dynamic range. It comprises a multibit sigma-delta modulator with dither, continuous time analog filters and analog output drive circuitry. This architecture provides a high insensitivity to clock jitter. The digital interpolation filter increases the sample rate by a factor of 8, using 3 linear phase half-band cascaded filters, followed by a first order SINC interpolator with a sample-rate factor of 8. This filter eliminates the images of baseband audio, retaining only the image at 64x the input sample rate, which is eliminated by the analog post filter. Optionally, a dither signal can be added that reduces possible noise tones at the output. However, the use of a multibit sigma-delta modulator provides extremely low noise tone energy. Master clock is 256 or 384 times the input data rate, allowing multiple choice of input data rate up to 48 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz. The DAC section also comprises volume and mute control and can be simultaneously played back directly on the line outputs and through a 32-Ohms stereo headset.
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The 32-Ohms pair of stereo-headset drivers also includes a LINEL and LINER channel-mixer pair of stereo inputs. Every DAC can be powered down separately via internal register control. Each single left or right DAC can be directed in MONO mode to the stereo headset and line outputs while the other is set in off mode. In addition, a microphone preamplifier with a microphone bias switch is integrated, reducing external ICs and saving board space. The volume, mute, power down, de-emphasis controls and 16-bit, 18-bit and 20-bit audio formats are digitally programmable via a 4-wire SPI bus and the digital audio data is provided through a multi-format I2S interface. The Power Management section can tolerate several types of input supply, such as: * Battery: voltage is converted to 3.3V via a DC/DC step up converter using 1 external inductor, 1 schottky diode and a capacitor. - Disposable AA or AAA size - coin cell size, 1 cell, as low as 0.9V for alkaline * USB: 5V VBUS supply from a USB connector or a Lithium-Ion battery The Power Management section also includes a set of low dropout (LDO) voltage regulators with different voltages to supply specific chip and analog requirements: * LDO1 is designed to drive up to 150 mA from a USB port with 9-step programmable output voltages: 2.7V, 2.8V, 2.9V, 3.0V, 3.1V, 3.2V, 3.3V, 3.4V, 3.5V. Default voltage is 3.4V and represents the initial output voltage of LDO1 at start up. When RSTB is activated, the external MCU can change the output voltage via the SPI serial interface. This LDO is designed to supply the complete chip when the device is connected to a USB port. * LDO2 is designed to drive up to 60 mA from LDO1 with 4-step programmable output voltages: 2.4V, 2.6V, 2.8V, 3.0V with low noise and high PSRR. Default voltage is 3.0V and represents the initial output voltage of LDO2 at start up. When RSTB is activated, the MCU can change the output voltage via the SPI serial interface. This LDO is designed to supply the internal analog section.
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2. Block Diagram
Figure 2-1. AT73C209 Functional Block Diagram
USB IN
VREF GNDB VBG
Voltage Reference
Integrated RC Oscillator
LX
Band Gap
SW1 DC-DC Step Up 3.3V / 100mA
FB GNDSW1 GNDSW1S ONOFF
Temperature Monitoring Unit
MICOUT MICINN
PGA
VCM
LDO1 3.4V / 150mA Internal VCM
VBOOST
MICB
to LDO2
-36 to +12dB/ 3dB step
Power Management Logic
LDO2 3.0V / 60mA
Internal Analog Section
VANA
LINEL
PGA
-36 to +12dB/ 3dB step LINER
Status Registers
AT73C209
SPI_DOUT
PGA
SPI
SPI_DIN SPI_CLK SPI_CSB
en_DAR -6 to +6dB/ 3dB step HSR
-46.5dB to 0dB 1.5dB step
32 Driver
DAC en_DAL
Serial Audio I/F
Right Volume Control
MCLK RSTB ITB SDIN LRFS BCLK
-6 to +6dB/ 3dB step HSL
Codec & Mixer
-46.5dB to 0dB 1.5dB step
32 Driver
DAC
Left Volume Control
INGND AVDDHS AGNDHS
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3. Application Diagram
Figure 3-1. Application Using One Cell Battery
L1
AC73C209
0.9V to 1.8V C14 22F
28
IN
LX FB
25
D1
26
Battery Cell
C1 22F
DC-DC
GNDSW1 GNDSW1S
23
24
R1 100m
29
3.1V to 5.5V
USB
LDO1 LDO2
VBOOST
30
VANA
31
Push Button
27
C2 2.2F
ONOFF RSTB ITB
22
5
LOGIC CONTROL
MICOUT
8
TO ADC C11 1F
16
MICINN INGND VCM
7 17
C10 10F
C9 1F
32
MIC
VBG
C8 100nF
BANDGAP
6
R2 2.2K MICB C12 10F C3 470nF
1
SPI_DIN SPI_DOUT SPI_CLK SPI_CSB LINEL
2
SERIAL INTERFACE
3
SPI
LINER
15
Analog Signal Analog Signal
4
14
C4 470nF
18
SDIN HSR BCLK MCLK LRFS
11
C5 100F RIGHT HEADSET
19
DIGITAL AUDIO INTERFACE
20
IS
CODEC & MIXER
HSL
10
C6 100F LEFT HEADSET
21
Connected to VANA
12
AVDDHS
AGNDHS
13
GNDB
33 9
VREF
C13 1F
C7* 1F
C7* =~ C3 + C4
NOTE: = DGND = AGND
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4. Components List
Table 4-1.
Reference C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 L1 R1 R2 SW1
Components List
Value 22 F 2.2 F / 10V 470 nF / 10V 470 nF / 10V 100 F / 6.3V 100 F / 6.3V 1 F / 6.3V 100 nF / 16V 1 F / 6.3V 10 F / 6.3V 1 F / 6.3V 10 F / 6.3V 1 F / 6.3V 22 F / 4V -10 H /550mA 0.1 Ohms 2.2 kOhms Push Button 1% 5% N/A Techno Tantalum Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Schottky 1812 -0402 N/A Series DSTMxx (APEM COMPONENTS) or equivalent Size Case A 0603 0402 0402 1210 1210 0402 0402 0402 0402 0402 0603 0402 0805 Manufacturer & Reference (AVX) or equivalent C1608X5R1A225MT (TDK) or GRM188R61A225 (Murata) C1005X5R1A474KT (TDK) or GRM155F51A474 (Murata) C1005X5R1A474KT (TDK) or GRM155F51A474 (Murata) C3225X5R0J107MT (TDK) or GRM32ER60J107 (Murata) C3225X5R0J107MT (TDK) or GRM32ER60J107 (Murata) C1005X5R0J105KT (TDK) or GRM155R60J105 (Murata) C1005X5R1C104KT (TDK) or GRM155F51C104 (Murata) C1005X5R0J105KT (TDK) or GRM155R60J105 (Murata) C1608X5R0J106MT (TDK) or GRM188R60G106 (Murata) C1005X5R0J105KT (TDK) or GRM155R60J105 (Murata) C1608X5R0J106MT (TDK) or GRM188R60G106 (Murata) C1005X5R0J105KT (TDK) or GRM155R60J105 (Murata) C2012X5R0J226MT (TDK) or GRM21BR60J226 (Murata) MBRA120LT3 (ON Semiconductors) or equivalent NLC453232T-100K-PF (TDK) or LQH43CN100K03 (Murata) in 0805 Case or can be made by PCB tracks
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5. Pin Description
Table 5-1.
Pin Name SPI_DIN SPI_DOUT SPI_CLK SPI_CSB ITB MICB MICINN MICOUT VREF HSL HSR AVDDHS AGNDHS LINEL LINER INGND VCM SDIN BCLK MCLK LRFS RSTB GNDSW1 GNDSW1S LX FB ONOFF IN USB VBOOST VANA VBG GNDB
Pin Description
I/O I O I I O O I O O O O I Ground I I O O I I I I O Ground I O I I I I O O O Ground Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Type Digital Digital Digital Digital Digital Analog Analog Analog Analog Analog Analog Supply Ground Analog Analog Analog Analog Digital Digital Digital Digital Digital Ground Analog Analog Analog Analog Supply Supply Analog Analog Analog Ground Function SPI Data Input SPI Data Output SPI Clock SPI Chip Select Open Drain Interruption / Test Analog Signal Output Microphone Bias Microphone Amplifier Input Microphone Amplifier Output Voltage Reference Pin For Audio Part Line-out/Headphone Left channel output Line-out/Headphone Right channel output Headset Amplifier Supply Headset Amplifier Ground Line-in, Left channel input Line-in, Right channel input Line-in, virtual signal ground pin for decoupling. Common Mode Reference Serial Data Input For Audio Interface Bit Clock Input For Audio Interface Master Clock Input For Audio Interface Audio interface left/right channel synchronization frame pulse Reset Active Low Power SW1 Ground SW1 Current Sense. Connected to 0.1 Ohms external limiting current sense resistor SW1 Inductor Switching Node SW1 Feedback SW1 Switch On Input power supply voltage. Connected to single Alkaline battery USB Supply Input LDO1 Output Voltage LDO2 Output Voltage Band Gap Voltage Analog Ground -Value 0 - VANA 0 - VANA 0 - VANA 0 - VANA 0 to VANA -Half VANA 0 to VANA -0 - AVDDHS 0 - AVDDHS VANA ----Half VANA 0 - VANA 0 - VANA 0 - VANA 0 - VANA 0 - VBOOST ---2.7V - 3.5V IN Level 0.9V - 1.8V 3.1 V to 5.5 V 0 to 3.5 V 0 to 3V
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6. Absolute Maximum Ratings
Table 6-1.
Operating Temperature (Industrial) Storage Temperature Power Supply Input: on Battery Input on USB Input -0.3V to +1.8V -0.3V to +5.5V
Absolute Maximum Ratings*
-40C to +85C -55C to +150C *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7. Digital IOs
All the digital IOs: SDIN, BCLK, LRFS, MCLK, RSTB, SPI_DOUT, SPI_DIN, SPI_CLK, SPI_CSB are referred to as VBOOST. Table 7-1.
Symbol VIL VIH VOL VOH
Digital IOs
Parameter Low level input voltage High level input voltage Low level output voltage High level output voltage Conditions Guaranteed input low Voltage Guaranteed input high Voltage IOL = 2 mA IOH = 2 mA VBOOST 2.7V to 3.5V 2.7V to 3.5V 2.7V to 3.5V 2.7V to 3.5V Min -0.3 0.8 x VBOOST -VBOOST - 0.5V Max 0.2 x VBOOST VBOOST + 0.3 0.4 -Unit V V V V
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8. SPI Interface
8.1 SPI architecture
The SPI is a 4 wire bi-directional asynchronous serial link. It works only in slave mode. The protocol is the following: Figure 8-1. SPI Protocol Diagram
SPI_CSB
SPI_CLK
rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0
SPI_DIN
d7 d6 d5 d4 d3 d2 d1 d0
SPI_DOUT
8.2
SPI Protocol
On SPI_DIN, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a read operation. The 7 following bits are used for the register address and the 8 last ones are the write data. For both address and data, the most significant bit is the first one. In case of a read operation, SPI_DOUT provides the contents of the read register, MSB first. The transfer is enabled by the SPI_CSB signal, active low. When there is no operation on the SPI interface, SPI_DOUT is set in high impedance to allow sharing of MCU serial interface with other devices. The interface is reset at every rising edge of SPI_CSB in order to return to an idle state, even if the transfer does not succeed. The SPI is synchronized with the serial clock SPI_CLK. Falling edge latches SPI_DIN input and rising edge shifts SPI_DOUT output bits. Note that MCLK (Audio Interface Master Clock Input) must run during any SPI write access registers (from address 0x00 to 0x0C).
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8.3 Timing Diagram for SPI Interface
SPI Timing Diagram
Figure 8-2.
SPI_CSB
Tssen Twl Tc Thsen
SPI_CLK
Twh Tssdi Thsdi
SPI_DIN
Tdsdo
Thsdo
SPI_DOUT
8.4
SPI Timing
SPI Timing Table
Description SPI_CLK min period SPI_CLK min pulse width low SPI_CLK min pulse width high Setup Time SPI_CSB falling to SPI_CLK rising Hold Time SPI_CLK falling to SPI_CSB rising Setup Time SPI_DIN valid to SPI_CLK falling Hold Time SPI_CLK falling to SPI_DIN not valid Delay Time SPI_CLK rising to SPI_DOUT valid Hold Time SPI_CLK rising to SPI_DOUT not valid Min 150 ns 50 ns 50 ns 50 ns 50 ns 20 ns 20 ns -0 ns Max -------20 ns --
Table 8-1.
Timing Parameter Tc Twl Twh Tssen Thsen Tssdi Thsdi Tdsdo Thsdo
8.5
SPI Register Tables
SPI Register Mapping
Register DAC_CTRL DAC_LLIG DAC_RLIG DAC_LPMG DAC_RPMG Name DAC Control DAC Left Line in Gain DAC Right Line in Gain DAC Left Master Playback Gain DAC Right Master Playback Gain Access Read/Write Read/Write Read/Write Read/Write Read/Write Reset 0x00 0x05 0x05 0x08 0x08
Table 8-2.
Offset 0x00 0x01 0x02 0x03 0x04
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Table 8-2.
Offset 0x05 0x06 0x07 0x08 0x09 0x0A 0x0C 0x10 0x11 0x12 0x14 0x15 0x17 0x20
SPI Register Mapping (Continued)
Register DAC_LLOG DAC_RLOG DAC_OLC DAC_MC DAC_CSFC DAC_MISC DAC_PRECH DAC_RST MISC_STATUS INT_MASK REG_CTRL SW_CTRL MIC_CTRL DC_SEL_VOUT Name DAC Left Line Out Gain DAC Right Line Out Gain DAC Output Level Control DAC Mixer Control DAC Clock and Sampling Frequency Control DAC Miscellaneous DAC Precharge Control Dac Reset USB and Headset Short Status Interrupt Mask Regulators Control Switcher Control Microphone Amplifier Control DC/DC Output Voltage Control Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Reset 0x00 0x00 0x22 0x09 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 DC_SEL_VOUT = 00
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8.5.1 DAC Control Register Register Name: DAC_CTRL Access Type: Read/Write Address: 0x00
7 RSRV1 6 RSRV2 5 ONDACR 4 ONDACL 3 ONLNOR 2 ONLNOL 1 ONLNIR 0 ONLNIL
Register (0x00): DAC Control
Bit 0 1 2 3 4 5 6 7 Name ONLNIL ONLNIR ONLNOL ONLNOR ONDACL ONDACR RSRV2 RSRV1 Description Left channel line in amplifier (L to power down, H to power up) Right channel line in amplifier (L to power down, H to power up) Left channel line out driver (L to power down, H to power up) Right channel line out driver (L to power down, H to power up) Left channel DAC (L to power down, H to power up) Right channel DAC (L to power down, H to power up) Reserved Bit Reserved Bit Reset Value ONLNIL = 0 ONLNIR = 0 ONLNOL = 0 ONLNOR = 0 ONDACL = 0 ONDACR = 0 0 0
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8.5.2 DAC Left Line In Gain Register Register Name: DAC_LLIG Access Type: Read/Write Address: 0x01
7 RSRV1 6 RSRV2 5 RSRV3 4 3 2 LLIG 1 0
Register (0x01): Left Line In Gain
Bit 4:0 7:5 Name LLIG<4:0> RSRV<1:3> Description Left channel line in analog gain selector Reserved Bits Reset Value LLIG<4:0>=00101 (0dB) 000
LLIG<4:0> 00000 00001 00010 00011 00100 00101 (Default) 00110 00111 01000
Gain 20 12 9 6 3 0 -3 -6 -9
Unit dB dB dB dB dB dB dB dB dB
LLIG<4:0> 01001 01010 01011 01100 01101 01110 01111 10000 >10001
Gain -12 -15 -18 -21 -24 -27 -30 -33 <-60
Unit dB dB dB dB dB dB dB dB dB
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8.5.3 DAC Right Line In Gain Register Register Name: DAC_RLIG Access Type: Read/Write Address: 0x02
7 RSRV1 6 RSRV2 5 RSRV3 4 3 2 RLIG 1 0
Register (0x02): Right Line In Gain
Bit 4:0 7:5 Name RLIG<4:0> RSRV<1:3> Description Right channel line in analog gain selector Reserved Bits Reset Value RLIG<4:0>=00101 (0dB) 000
RLIG<4:0> 00000 00001 00010 00011 00100 00101 (Default) 00110 00111 01000
Gain 20 12 9 6 3 0 -3 -6 -9
Unit dB dB dB dB dB dB dB dB dB
RLIG<4:0> 01001 01010 01011 01100 01101 01110 01111 10000 >10001
Gain -12 -15 -18 -21 -24 -27 -30 -33 <-60
Unit dB dB dB dB dB dB dB dB dB
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8.5.4 DAC Left Master Playback Gain Register Register Name: DAC_LMPG Access Type: Read/Write Address: 0x03
7 RSRV1 6 RSRV2 5 4 3 LMPG 2 1 0
Register (0x03): Left Master Playback Gain
Bit 5:0 7:6 Name LMPG<5:0> RSRV<1:2> Description Left channel master playback digital gain selector Reserved Bits Reset Value LMPG<5:0>=001000 (0dB) 00
LMPG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 (Default) 001001 001010 001011 001100 001101 001110 001111 010000
Gain 12 10.5 9 7.5 6 4.5 3 1.5 0 -1.5 -3 -4.5 -6 -7.5 -9 -10.5 -12
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
LMPG<5:0> 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 >100000
Gain -13.5 -15 -16.5 -18 -19.5 -21 -22.5 -24 -25.5 -27 -28.5 -30 -31.5 -33 -34.5 Mute
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.5.5 DAC Right Master Playback Gain Register Register Name: DAC_RMPG Access Type: Read/Write Address: 0x04
7 RSRV1 6 RSRV2 5 4 3 RMPG 2 1 0
Register (0x04): Right Master Playback Gain
Bit 5:0 7:6 Name RMPG<5:0> RSRV<1:2> Description Right channel master playback digital gain selector Reserved Bits Reset Value RMPG<5:0>=001000 (6dB) 00
RMPG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000
Gain 12 10.5 9 7.5 6 4.5 3 1.5 0 -1.5 -3 -4.5 -6 -7.5 -9 -10.5 -12
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
RMPG<5:0> 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 >100000
Gain -13.5 -15 -16.5 -18 -19.5 -21 -22.5 -24 -25.5 -27 -28.5 -30 -31.5 -33 -34.5 Mute
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.5.6 DAC Left Line Out Gain Register Register Name: DAC_LLOG Access Type: Read/Write Address: 0x05
7 RSRV1 6 RSRV2 5 4 3 LLOG 2 1 0
Register (0x05) Left Line Out Gain
Bit 5:0 7:6 Name LLOG<5:0> RSRV<1:2> Description Left channel line out digital gain selector Reserved Bits Reset Value LLOG<5:0>=000000 (0dB) 00
LLOG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000
Gain 0 -1.5 -3 -4.5 -6 -7.5 -9 -10.5 -12 -13.5 -15 -16.5 -18 -19.5 -21 -22.5 -24
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
LLOG<5:0> 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 >100000
Gain -25.5 -27 -28.5 -30 -31.5 -33 -34.5 -36 -37.5 -39 -40.5 -42 -43.5 -45 -46.5 Mute
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.5.7 DAC Right Line Out Gain Register Register Name: DAC_RLOG Access Type: Read/Write Address: 0x06
7 RSRV1 6 RSRV2 5 4 3 RLOG 2 1 0
Register (0x06): Right Line Out Gain
Bit 5:0 7:6 Name RLOG<5:0> RSRV<1:2> Description Right channel line out digital gain selector Reserved Bits Reset Value RLOG<5:0>=000000 (0dB) 00
RLOG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000
Gain 0 -1.5 -3 -4.5 -6 -7.5 -9 -10.5 -12 -13.5 -15 -16.5 -18 -19.5 -21 -22.5 -24
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
RLOG<5:0> 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 >100000
Gain -25.5 -27 -28.5 -30 -31.5 -33 -34.5 -36 -37.5 -39 -40.5 -42 -43.5 -45 -46.5 Mute
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.5.8 DAC Output Level Control Register Register Name: DAC_OLC Access Type: Read/Write Address: 0x07
7 RSHORT 6 5 ROLC 4 3 LSHORT 2 1 LOLC 0
Register (0x07): Output Level Control
Bit 2:0 Name LOLC<2:0> Description Left channel output level control selector Left channel short circuit indicator (Persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated. Must be cleared by reset cycle or direct register write operation.) Right channel output level control selector Right channel short circuit indicator (Persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated. Must be cleared by reset cycle or direct register write operation.) Reset Value LLOC<2:0>=010 (0dB)
3
LSHORT
LSHORT = 0
6:4
ROLC<6:4>
ROLC<6:4>=010 (0dB)
7
RSHORT
RSHORT = 0
LOLC<2:0> - ROLC<6:4> 000 001 010 011 >100
Gain -6 -3 0 +3 +6
Unit dB dB dB dB dB
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8.5.9 DAC Mixer Control Register Register Name: DAC_MC Access Type: Read/Write Address: 0x08
7 RSRV1 6 RSRV2 5 INVR 4 INVL 3 RMSMIN2 2 RSMIN1 1 LMSMIN2 0 LMSMIN1
Register (0x08): Mixer Control
Bit 0 1 2 3 4 5 7:6 Name LMSMIN1 LMSMIN2 RMSMIN1 RMSMIN2 INVL INVR RSRV<1:2> Description Left Channel Mono/Stereo Mixer Left Mixed input enable (H to enable, L to disable) Left Channel Mono/Stereo Mixer Right Mixed input enable (H to enable, L to disable) Right Channel Mono/Stereo Mixer Left Mixed input enable (H to enable, L to disable) Right Channel Mono/Stereo Mixer Right Mixed input enable (H to enable, L to disable) Left channel mixer output invert (H to enable, L to disable) Right channel mixer output invert (H to enable, L to disable) Reserved Bits Reset Value LMSMIN1 = 1 LMSMIN2 = 0 RMSMIN1 = 0 RMSMIN2 = 1 INVL = 0 INVR = 0 00
* Digital Mixer Control The Audio DAC features a digital mixer that allows the mixing and selection of multiple input sources. The mixing/multiplexing functions are described in the figure below:
Left channel Volume Control 2 To DACs 1 Volume Control 2 Right channel
Note: Whenever the two mixer inputs are selected, a -6 dB gain is applied to the output signal. Whenever only one input is selected, no gain is applied.
1
Volume Control
From digital
filters
Volume Control
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8.5.10 Clock and Sampling Frequency Control Register Register Name: DAC_CSFC Access Type: Read/Write Address: 0x09
7 RSRV1 6 RSRV2 5 RSRV3 4 OVRSEL 3 RSRV4 2 RSRV5 1 RSRV6 0 RSRV7
Register (0x09): Clock and Sampling Frequency Control
Bit 3:0 4 7:5 Name RSRV<4:7> OVRSEL RSRV<1:3> Description Reserved Bits Master clock selector (L to 256xFs, H to 384xFs) Reserved Bits Reset Value 0000 OVRSEL = 0 000
* Master Clock and Sampling Frequency Selection The following table describes the modes available for master clock and sampling frequency selection.
OVRSEL 0 1 Master Clock 256 x Fs 384 x Fs
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8.5.11 DAC Miscellaneous Register Name: DAC_MISC Access Type: Read/Write Address: 0x0A
7 RSRV1 6 RSRV2 5 DINTSEL 4 3 DITHEN 2 DEEMPEN 1 NBITS 0
Register (0x0A): Miscellaneous
Bit 1:0 2 3 5:4 7:6 Name NBITS<1:0> DEEMPEN DITHEN DINTSEL<5:4> RSRV<1:2> Description Data interface word length De-emphasis enable (L to disable, H to enable) Dither enable (L to disable, H to enable) I2S data format selector Reserved Bits Reset Value NBITS<1:0>=10 DEEMPEN = 0 DITHEN = 0 DINTSEL<5:4>=00 00
* Interface Word Length The selection of input sample size is done using the nbits<1:0> register according to the following table:
NBITS<1:0> 00 01 10
Format 16 bits 18 bits 20 bits
* De-emphasis and Dither Enable The circuit features a de-emphasis filter for the playback channel. To enable the de-emphasis filtering the deemphen signal must be set to high. Likewise, the dither option (added in the playback channel) is enabled by setting the dithen signal to High. * I2S Data Format Selector The selection between modes is done using the dintsel<1:0> signal according to the following table:
DINTSEL<5:4> 00 01 10
Format I2S Justified MSB Justified LSB Justified
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8.5.12 DAC Precharge Register Name: DAC_PRECH Access Type: Read/Write Address: 0x0C
7 RSRV1 6 RSRV2 5 PRCHGLNOR 4 PRCHGLNOL 3 PRCHGLNIR 2 PRCHGLNIL 1 PRCHG 0 ONMSTR
Register (0x0C): Pre-Charge Control
Bit 0 1 2 3 4 5 7:6 Name ONMSTR PRCHG PRCHGLNIL PRCHGLNIR PRCHGLNOL PRCHGLNOR RSRV<1:2> Description Master power on control (L: power down, H: power up) Master pre-charge (H to charge) Left channel line in pre-charge (H to charge) Right channel line in pre-charge (H to charge) Left channel line out pre-charge (H to charge) Right channel line out pre-charge (H to charge) Reserved Bits Reset Value ONMSTR = 0 PRCHG = 0 PRCHGLNIL = 0 PRCHGLNIR = 0 PRCHGLNOL = 0 PRCHGLNOR = 0 00
8.5.13 DAC Reset Register Name: DAC_RST Access Type: Read/Write Address: 0x10
7 RSRV1 6 RSRV2 5 RSRV3 4 RSRV4 3 RSRV5 2 UNCHANGE 1 RESFILZ 0 RSTZ
Register (0x10): DAC Reset
Bit 0 1 2 7:3 Note: Name RSTZ RESFILZ UNCHANGE RSRV<1:5> Description Active low reset of the audio codec Active low reset of the audio codec filter This Register Bit could not be changed Reserved Bits Reset Value RSTZ = 0 RESFILZ = 0 UNCHANGE = 0 00000
It's important to never change bit 2. It must stay at 0 (low state).
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8.5.14 DAC Miscellaneous Status Register Name: MISC_STATUS Access Type: Read-Only Address: 0x11
7 RSRV1 6 RSRV2 5 RSRV3 4 RSRV4 3 RSRV5 2 RSRV6 1 USBOK 0 HSSHORT
Register (0x11): Miscellaneous Status
Bit 0 1 7:2 Name HSSHORT USBOK RSRV<1:6> Description Headset Short Flag USB Supply Flag Reserved Bits Reset Value HSSHORT = 0 USBOK = 0 000000
8.5.15 Interrupt Mask: INT_ MASK (0x12) Register Name: MISC_STATUS Access Type: Read/Write Address: 0x12
7 RSRV1 6 RSRV2 5 RSRV3 4 RSRV4 3 RSRV5 2 USBFMSK 1 USBRMSK 0 HSSMSK
Register (0x12): Interrupt Mask
Bit 0 1 2 7:3 Name HSSMSK USBRMSK USBFMSK RSRV<1:5> Description Headset short interrupt mask (1 to enable interrupt) USB supply rising interrupt mask (1 to enable interrupt) USB supply falling interrupt mask (1 to enable interrupt) Reserved Bits Reset Value HSSMSK = 0 USBRMSK = 0 USBFMSK = 0 00000
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8.5.16 Regulator Control Register Name: REG_CTRL Access Type: Read/Write Address: 0x14
7 RSRV1 6 ONVANA 5 SELVANA 4 3 2 SELVBOOST 1 0
Register (0x14) Regulators Control
Bit 3:0 5:4 6 7 Name SELVBOOST<3:0> SELVANA<1:0> ONVANA RSRV1 Description LDO1 VBOOST regulator output voltage selection LDO2 VANA regulator output voltage selection LDO2 VANA regulator enable (active high) Reserved Bit Reset Value SELVBOOST<3:0>=0000 (3.4 V) SELVANA<1:0>=00 (2.8 V) ONVANA = 0 0
* SELVBOOST
SELVBOOST<3:0> x001 x010 x011 x100 x101 x110 x111 0000 1000 Output Value 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 3.2 V 3.3 V 3.4 V 3.5 V
* SELVANA
SELVANA<1:0> 00 01 10 11 Output Value 2.8 V 2.6 V 3.0 V 2.4 V
* ONVANA
ONVANA 0 1 VANA Output High Impedance Enable
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8.5.17 Switcher Control Register Name: SW_CTRL Access Type: Read/Write Address: 0x15
7 RSRV1 6 RSRV2 5 RSRV3 4 RSRV4 3 RSRV5 2 RSRV6 1 RSRV7 0 UPONOFF
Register (0x15): Switcher Control
Bit 0 7:1 Name UPONOFF RSRV<1:7> Description Microprocessor ON/OFF (1 to enable SW1) Reserved Bits Reset Value UPONOFF = 0 0000000
8.5.18 Microphone Amplifier Control Register Name: MIC_CTRL Access Type: Read/Write Address: 0x17 Read/Write
7 RSRV1 6 RSRV2 5 RSRV3 4 RSRV4 3 RSRV5 2 RSRV6 1 ONAMP 0 ONMIC
Register (0x17): Microphone Amplifier Control
Bit 0 1 7:2 Name ONMIC ONAMP RSRV<1:6> Description Microphone bias enable, active high Microphone amplifier enable, active high Reserved Bits Reset Value ONMIC = 0 ONAMP = 0 000000
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8.5.19 DC/DC Output Voltage Control Register Name: DC_SEL_VOUT Access Type: Read/Write Address: 0x20 Read/Write
7 RSRV1 6 RSRV2 5 RSRV3 4 3 2 RSRV4 1 RSRV5 0 RSRV6
DC_SEL_VOUT
Register (0x20): DC/DC Output Voltage Control
Bit 2:0 4:3 7:5 Name RSRV<4:6> DC_SEL_VOUT<4:3> RSRV<1:3> Description Reserved Bits and Never Change value DC/DC Output Voltage Control Reserved Bits and Never Change value Reset Value Don't Change DC_SEL_VOUT = 00 (3.3V) Don't Change
* DC_SEL_VOUT
DC_SEL_VOUT<4:3> 00 01 10 11 Notes: Output Value 3.3 V 2.6 V 2.8 V 3.0 V 1. Important: In the Register 0x20, only the Bits #4 and #3 can be modified. The others bits should keep there initial values.
It's important to apply the sequence as follows: - Read The register 0x20 - Copy the values - Only modify the bits #4 and #3 of DC_SEL_VOUT - Write the register 0x20
2. It's important to have an output voltage correlation between DC/DC output and VBOOST_LDO output. The correlation should be as shown in Table 8-3 that follows:
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Table 8-3.
Reg
DC/DC Output Voltage vs. VBOOST LDO Output Voltage
DC_SEL_VOUT<4:3> Output Value Reg SELVBOOST<3:0> Min - x001 01 2.6 V Max - 1000 Min - x011 10 2.8 V Max - 1000 0x14 Min - x101 11 3.0 V Max - 1000 Min - 0000 00 3.3 V Max - 1000 Up to 3.5 V Up to 3.5 V 3.4V 3.1 V Up to 3.5 V Up to 3.5 V 2.9 V Output Value 2.7 V
0x20
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9. Power Supplies
9.1
9.1.1
DC to DC Boost Converter (SW1)
Features * * * * *
Input Voltage Range: 0.9V to 1.8V (Single Alkaline Battery) From 0 to 100 mA Maximum Output Current When Started 4 Programmable Output Voltages, 2.6V, 2.8V, 3.0V and 3.3V (Default Value). Peak Efficiency with 50 mA Output Current Overcurrent Protection Through External Resistor
9.1.2
Description * DCDC is a high-efficiency DC/DC boost converter designed for single cell alkaline batteries found in PDA's, MP3 players, and other handheld portable devices. It can work with battery voltage as low as 0.9V, and lower than 1.8V. * The Boost Converter is optimized for current load of 50 mA and 3.3V output voltage. It includes a low resistive 0.2 Ohms N-channel power switch, a start-up oscillator, and an integrated current limitation. In particular, this current limitation can be achieved using a lowvalue 100 mOhms external resistor.
9.1.3
Functional Diagram and Typical Application DC/DC Typical Application Diagram
L = 10 H
Figure 9-1.
in
lx
DC
Push Button Cell 0.9V - 1.8V on/off
ref Digital Control
Schottky Diode fb Vout
gndsw1s 22 F Current Control DC/DC
gndsw1 0.1 Ohms
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9.1.4 Electrical Specifications
Conditions L = 10 H (0.1 Ohms ESR) IN = 1.2V -40C .No load current in start-up phase (load resistor higher than 10 KOhms).
Table 9-1.
Symbol IN VFB ISD IL Ic tSTART RNMOS
DC to DC Boost Converter (SW1)Electrical Characteristics
Parameter Input Voltage Output Voltage Shutdown Current Inductor Current Limitation Output Current Start Up Time NMOS switch resistance IN = 1.2V, VFB = 0.95 * 3.3 From disabled to enabled RLOAD = 10 kOhms VFB = 3.3V Load of 3 mA and IN = 1.2V 45 65 65 DC_SEL_VOUT = 00 DC/DC is Off IN = 1.2V, VFB > 2.4V 600 50 5 0.2 50 70 70 30 30 50 60 mV mV % 100 Conditions Min 0.9 3.10 Typ 1.2 3.3 Max 1.8 3.45 10 Unit V V A mA mA ms Ohms
Yield
Power efficiency
Load of 50 mA and IN = 1.2V Load of 100 mA and IN = 1.2V
tR_LOAD
Transient Load Regulation
IN =1.2V, Iout = 0 to 100 mA in 0.5s Load of 10 mA, IN = 1.2V VFB = 3.3V and 100 mOhms Rsense
FRIPP
Frequency Ripple
Load of 50 mA, IN = 1.2V VFB = 3.3V and 100 mOhms Rsense Load of 100mA, IN = 1.2V VFB = 3.3V and 100 mOhms Rsense
9.1.5
Control Modes FB Voltage Selection 29
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* The FB voltage can be selected with DC_SEL_VOUT<4:3>, according to the following table. When DCDC starts SEL_VOUT must be set to <00>. * The FB voltage can be modified by changing bits 4 and 3 of the register 0x20. It's important to only modify this two bits in this register. (see 8.5.19 for the sequence)
Table 9-2.
Control Modes
Minimum Output Value 3.10V 2.52V 2.67V 2.82V Output Value 3.3V 2.6V 2.8V 3.0V Maximum Output Value 3.45V 2.66V 2.88V 3.10V
DC_SEL_VOUT<4:3> 00 (default) 01 10 11
9.1.6
Typical Performance Characteristics Typical condition means:
Typical process conditions VFB = 3.3V IN = 1.2V and ILOAD = 50 mA Recommended external components
Figure 9-2.
Spice Simulation Results
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9.2
9.2.1
LDO1: 3.3V From USB Port
Features * Stand Alone Voltage Regulator with Internal Bandgap Voltage Generator * 2.7V, 2.8V, 2.9V, 3.0V, 3.1V, 3.2V, 3.3V, 3.4V and 3.5V Programmable Output Voltages and 150 mA of
Max Load Current
* 4.5V to 5.5V Supply Voltage * 3.1V to 5.5V Supply Voltage for 2.7V and 2.9V output voltage 9.2.2 Description LDO1 is a low drop out voltage regulation module that can be used to provide 9-step programmable output voltages and 150 mA of maximum load current. It is designed to be integrated with other analog cells, digital logic, microcontrollers, DSP cores, and memory blocks into system-onchip products. An internal reference voltage (bandgap voltage) is provided to the regulator, so only a compensation capacitor connected at the output node versus ground is needed for correct operations. 9.2.3 Functional Diagram and Typical Application LDO1 Typical Application Diagram
USB VBOOST
Figure 9-3.
VBOOST
USB 3.1V - 5.5V DC
ref
22 F
gnd LDO1
9.2.4 Table 9-3.
Symbol VDD tJ
Electrical Specifications LDO1 Electrical Specifications
Parameter Operating Supply Voltage Temperature Range Conditions 3.1V operation required (Li-Ion Battery) Min 3.1 -20 Typ --Max 5.5 125 Unit V C
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Table 9-3.
Symbol
LDO1 Electrical Specifications (Continued)
Parameter Conditions Programmed @ 3.5V Programmed @ 3.4V Programmed @ 3.3V Programmed @ 3.2V Min 3.45 3.35 3.25 3.15 3.05 2.95 2.85 2.75 2.65 -300 -3.1V < VDD < 5.5V; I_Load = 150 mA VDD = 5V; I_Load = 0 to 150 mA I_Load = 150 mA; BW: 10 Hz - 100 kHz ----On = 0 @ f = 200 Hz @ f = 20 kHz -28 8 Typ 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 -500 40 -----40 12 Max 3.55 3.45 3.35 3.25 3.15 3.05 2.95 2.85 2.75 150 800 60 15 10 1 700 1 48 19 mA mA A mV mV mVrms s A dB dB V Unit
VOUT
Output Voltage
Programmed @ 3.1V Programmed @ 3.0V Programmed @ 2.9V Programmed @ 2.8V Programmed @ 2.7V
IO ILIMIT IQ VDC VDC VNOISE tR ISD PSRR
Output Current Current Limit Quiescent Current Line Regulation Load Regulation Output Noise Rise Time Shut Down Current Power Supply Rejection Ratio
9.2.5
Control Modes - Enable/Disable The LDO is enabled by applying a voltage on the USB pin. It is automatically disabled by removing the USB supply. Output Voltage Selection The VBOOST voltage can be modified by changing SELVBOOST<3:0> of the register 0x14. (See Section 8.5.16 "Regulator Control".) Table 9-4. LDO Output Voltage Selection
Output Voltage 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 3.2 V 3.3 V 3.4 V 3.5 V
9.2.6
SELVBOOST<3:0> x001 x010 x011 x100 x101 x110 x111 0000 1000
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9.3
9.3.1
LDO2: 2.4V to 3.0V for Internal Analog Section Supply
Features * * * * * * *
Low Noise Low Drop Out Voltage Regulator 2.4V to 3V Programmable Output Voltage 2.7V to 3.5V Supply Operation (VANA = 2.4V, 2.6V, 2.8V) 3.2V to 3.5V Supply Operation (VANA = 3V) 60mA of Max Load Current Power-down Mode (Consumption <1mA) Typical cUrrent Consumption 195 A
9.3.2
Description LDO2 is a Low Drop Out (LDO) voltage regulator with a programmable 2.4V to 3V output voltage, rated for loads up to 20 mA. The circuit comprises a PMOS pass device, an error amplifier, a feedback resistive network sized to have closed loop gain. These blocks constitute the regulating loop. A 2-bit decoder allows controlling the programmable output voltage. Available output voltages are 2.4V, 2.6V, 2.8V and 3V. An over-current and short-circuit protection circuit has been included to limit the output current delivered by the regulator, thus avoiding its destruction in short circuit configuration. An external reference voltage (bandgap voltage) is needed. The target reference voltage is 1.231V delivered. A ceramic or low ESR tantalum capacitor is needed (2.2 F minimum value) as external compensation.
9.3.3
Functional Diagram and Typical Application LDO2 Typical Application Diagram
VANA VBOOST VANA
Figure 9-4.
Input from LDO1 Output
ref 2,2 F
gnd LDO2
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9.3.4 Table 9-5.
Electrical Specifications General Power Supply Parameters
Parameter Symbol VBOOST2 VBOOST2 IC VNOISE Conditions VBOOST2 - VANA >= 0.2V VBOOST2 - VANA >= 0.2V For all Sel<1:0> conditions BW: 10 Hz to 100 kHz, Sel <10> = xx Min 2.7 3.2 --Typ 3.2 3.3 40 -Max 3.5 3.5 60 70 Unit V V mA Vrms
Operating Supply Voltage (#1) Operating Supply Voltage (#2) Output Current Output Noise
Table 9-6.
LDO2 Parameters
Parameter Symbol Conditions Sel <10> = 00 Sel <10> = 01 Min 2.75 2.55 2.95 2.35 179 ----34 54 53 45 Typ 2.8 2.6 3.0 2.4 189 ---140 ----Max 2.85 2.65 V Sel <10> = 10 Sel <10> = 11 3.05 2.45 300 10 10 10 -----A mV mV s nA dB dB dB dB Unit
Output Voltage
VANA
Quiescent Current Line Regulation Load Regulation Rise Time Shut Down Current
IC VANA VANA tC ISD PSRR
Worst case VBOOST2 = 3.0V, VBOOST2: 3.1 V to 3.5V, IOUT = 2 0mA 10% - 90% IOUT VBOOST2 = 3.3V 10% - 90% VANA RLOAD = 120 Ohms CLOAD = 2.2F worst case @VBOOST2 = 3V On = 0 Band Pass: 0 Hz to 500 kHz IOUT = 10 mA worst case @ VBOOST2 = 3.2V DC 20 kHz 100 kHz
Power Supply Rejection Ratio
PSRR PSRR PSRR
9.3.5
Control Modes - Truth Table Figure 9-5. Table 9-7. The LDO2 can be enabled and disabled by activating the bit #6 (ONVANA) on the register 0x14. (See Section 8.5.16 "Regulator Control") LDO2 Activation
VANA Output Power Down (HiZ) Power On
ONVANA (bit #6) 0 1
All digital signals are referred to the supply voltage VBOOST.
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9.3.6 Output Voltage Selection The VANA voltage can be modified by changing the value of SELVANA<5:4> of the register 0x14. (See Section 8.5.16 "Regulator Control") Table 9-8. LDO2 Output Voltage Selection
Output Values 2.8 V 2.6 V 3.0 V 2.4 V
SELVANA<5:4> 00 01 10 11
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10. Audio DAC
10.1 Description
The Audio DAC IP core includes the functions of Stereo D-to-A conversion, channel filtering, line-in/microphone and line-out/headphone interfacing with integrated short-circuit detection. Oversampling sigma delta technology is used in the D-to-A conversion. The channel filters are implemented digitally, embedded in the interpolation filters associated with the converter. Stereo single-ended interfaces are available for line-in/microphone and line-out/headphone connections. Mono differential interfaces are available for auxiliary input amplifier and PA driver. The line-out/headphone amplifier can drive an external load of 32 Ohms with 20 mWrms. The linein/microphone amplifier has an input range of 70 mVrms at maximum gain. The data port is I2S serial at 8 to 48kHz. In full power-down mode the standby current consumption is less than 10 A.
10.2
Functional Diagram
Figure 10-1. Audio DAC Functional Diagram
avddhs
linel
PGA
ingnd liner PGA Status Registers spi_csb spi_din spi_dout spi_clk
bclk hsl
SPKR DRV 32
+
DAC
Volume Control
+
Volume Control
Digital Filter Serial Audio Interface
lrfs mclk sdin
hsr
SPKR DRV 32
+
DAC
Volume Control
+
Volume Control
Digital Filter
agndhs
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10.3 Electrical Specifications
AVDD, AVDDHS = 2.8 V, TA = 25C, typical case, unless otherwise noted. All noise and distortion specifications are measured in the 20 Hz to 0.425xFs and A-weighted filtered. Full-scale levels scale proportionally with the analog supply voltage. Table 10-1.
Parameters Overall Analog Supply Voltage (AVDD, AVDDHS) Digital Supply Voltage (VDIG) Digital Inputs/outputS Resolution Logic Family Logic Coding 20 CMOS 2's Complement ANALOG PERFORMANCE - DAC to Line-out/Headphone Output -Output Common Mode Voltage Output load resistance (on HSL, HSR) Headphone load Line load Output load capacitance (on HSL) Headphone load Line load Signal to Noise Ratio (-1dBFS @ 1kHz input and 0dB Gain) Line and Headphone loads Total Harmonic Distortion (-1dBFS @ 1kHz input and 0dB Gain) Line Load Headphone Load Headphone Load (16 Ohm) Dynamic Range (measured with -60 dBFS @ 1kHz input, extrapolated to fullscale) Line Load Headphone Load Interchannel mismatch Left-channel to right-channel crosstalk (@ 1kHz) Output Headset Driver Level Control Range Output Headset Driver Level Control Step PSRR 1 kHz 20 kHz Maximum output slope at power up (100 to 220 F coupling capacitor) -6 3 55 50 3 87 -1.65 0.5 x AVDDHS 32 10 30 30 92 1000 150 --Vpp V bits 2.7 2.4 2.8 2.8 3.3 3.3 V V
Audio DAC Electrical Specifications
Min Typ Max Units
16
Ohm kOhm pF pF dB
-80 -65 -40
-76 -60
dB dB dB
88 70
93 74 0.1 -90 1 -80 6
dB dB dB dB dB dB dB dB V/s
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Table 10-1.
Parameters
Audio DAC Electrical Specifications (Continued)
Min Typ Max Units
Analog Performance - Line-in to Line-out/Headphone Output Input level for full scale output - 0dBFS Level @ AVDD, AVDDHS = 2.8 V and 0 dB gain @ AVDD, AVDDHS = 2.8 V and 20 dB gain Input common mode voltage Input impedance Signal to Noise Ratio -1 dBFS @ 1kHz input and 0 dB gain -21 dBFS @ 1kHz input and 20 dB gain Dynamic Range (extrapolated to full scale level) -60 dBFS @ 1kHz input and 0 dB gain -60 dBFS @ 1kHz input and 20 dB gain Total Harmonic Distortion -1dBFS @ 1kHz input and 0 dB gain -1dBFS @ 1kHz input and 20 dB gain Interchannel mismatch Left-channel to right-channel crosstalk (@ 1kHz) Master Clock Master Clock Maximum Long Term Jitter Digital Filter Performance Frequency response (10 Hz to 20 kHz) Deviation from linear phase (10 Hz to 20 kHz) Passband 0.1 dB corner Stopband Stopband Attenuation 0.5465 65 De-emphasis Filter Performance (for 44.1kHz Fs) Frequency Pass band Transition band Stop Band 0 Hz to 3180 Hz 3180 Hz to 10600 Hz 10600 Hz to 20 kHz Gain -1dB Logarithm decay -10.45dB Margin 1dB 1 dB 1 dB 0.1 0.1 0.4535 dB deg Fs Fs dB 1.5 nspp 7 81 1.65 583 0.165 58.3 0.5 x AVDD 10 85 71 86 72 -80 -75 0.1 -90 -76 -68 1 -80 Vpp mVrms Vpp mVrms V kOhm dB dB dB dB dB dB dB dB
82
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Table 10-1.
Parameters Power Performance Current consumption from Analog supply in power on Current consumption from Analog supply in power down Power on Settling Time From full power down to full power up (Vref and VCM decoupling capacitors charge) Line in amplifier (line in coupling capacitors charge) Driver amplifier (out driver DC blocking capacitors charge) 500 50 500 9.5 10 mA A ms ms ms
Audio DAC Electrical Specifications (Continued)
Min Typ Max Units
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10.4
Data Interface
Normal operation is entered by applying correct LRFS, BCLK and SDIN waveforms to the serial interface, as illustrated in the timing diagrams below. To avoid noise at the output, the reset state is maintained until proper synchronization is achieved in the serial interface. The data interface allows three different data transfer modes as described below.
Figure 10-2. 20-bit I2S Justified Mode
BCLK
LRFS
SDIN
R1
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
Figure 10-3. 20-bit MSB Justified Mode
BCLK
LRFS
SDIN
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
L(N-1)
Figure 10-4. 20-bit LSB Justified Mode
BCLK
LRFS
SDIN
R0
L(N-1)
L(N-2)
...
L1
L0
R(N-1)
R(N-2)
...
R1
R0
L(N-1)
The selection between modes is done using the DINTSEL<5:4> bits in the register 0x0A according with the following table.
DINTSEL <5:4> 00 01 1x Format I2S Justified MSB Justified LSB Justified
The data interface always works in slave mode. This means that the LRFS and the BCLK signals are provided by the host controller. In order to achieve proper operation, the LRFS and the BCLK signals must be synchronous with the MCLK master clock signal and their frequency relationship must reflect the selected data mode. For example, if the data mode selected is the 20bit MSB Justified, then the BCLK frequency must be 40 times higher than the LRFS frequency.
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10.5 Timing Specifications
Figure 10-5. Data Interface Timing Diagram The timing constraints of the data interface are described in the following diagram and table. Figure 10-6. I2S Timing Diagram
1 N 19N+1 20N M/2.N+1 M/2.(N+1) (M-1).N+1 M.N
MCLK
td1
1
20
M/2+1
M
BCLK
td2
LRFS
ts3 th3
SDIN
Table 10-2.
Data Interface Timing Parameters
Parameter Min 2.5 0 10 10 Typ ----Max 7.5 5 --Unit ns ns ns ns
td1 td2 ts3 th3
Delay from MCLK rising edge to BCLK edges Delay from BCLK falling edge to LRFS edges din set-up time before BCLK rising edge din hold time after BCLK rising edge
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11. Microphone Preamplifier (OP065)
11.1 Features
* * * * * *
Standard Quality Amplifier for Electret Microphone Preamplifier Low Power Consumption Few External Components Necessary for a Complete Preamplifier Internal Bias Internal Bias for the Electret Microphone Stand-by Mode
11.2
Description
The OP065 is a low-voltage operational amplifier designed for a standard quality electret microphone preamplifier. It presents a frequency response, a supply rejection and a noise compatible with voice quality applications. All voltages are referred to gnda. The OP065 is powered by vdda pin, with a nominal voltage of 2.8V. The normal operating mode is defined with ONAMP and ONMIC pins set to 1 (referred to vdda).
11.3
Functional Diagram
Figure 11-1. Microphone Preamplifier Functional Diagram
560k
6.8k micinn micout vcm OP065
2.2k micb
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11.4 Detailed Description
The OP065 is a two-stage class A amplifier with a nominal 40 dB gain. The gain can be reduced simply by adding a resistor in serie with the MICINN input. Included input resistor is 2.2 KOhms. Few external components are needed for a complete electret microphone preamplifier solution: * Input capacitor between the microphone and the MICINN input of the OP065 (2.2 F recommended), * Resistive bridge and the decoupling capacitor for the VCM common mode input (100 KOhms + 100 KOhms bypassed by a 10 F capacitor recommended) * Power supply decoupling capacitor for the microphone (10 F recommended, on MICOUT) Refer to the typical application suggestion presented in Figure 2-1 "AT73C209 Functional Block Diagram" on page 3. The common mode is to be set externally to half supply. The output MICOUT is then centered to half supply. It is self-biased. The biasing of the electret microphone is included, through a 1.2 KOhms resistor in serie with the VDDA supply, and available on MICOUT. This bias can be shut down by ONMIC input (bias available with ONMIC = 1). The MICINN input should be AC coupled to the microphone, its DC value is normally set to half supply (as soon as VCM input is biased to half supply). The output stage is a class A linear structure with an internal low quiescent current. This current will be actually essentially fixed by the external load to be connected (DC coupled) between the output (MICOUT) and the ground. A typical 50 KOhms load is recommended. A maximum 100pF load can be connected to the output. The OP065 is not optimized for general buffer purpose. The biasing of the electret microphone is included, through a 2.2 KOhms resistor in serie with the VDDA supply, and available on MIC output. The MICINN input should be AC coupled to the microphone, its DC value is set to half supply.
11.5
Electrical Specifications
TA = 25C, VSUPPLY = 2.4V to 3.0V, unless otherwise specified. Microphone Preamplifier (OP065) Electrical Specifications
Symbol VANA Vc Gv ZIN VOFF AC input coupling 20 Hz - 20 KHz bandwidth, unweighted 50 kOhms // 100 pF load 50 kOhms // 100 pF load 50 KOhms load With an ideal voltage source Conditions Min 2.4 0.2 ---10 Typ 2.8 -40 2200 -Max 3.0 Vana-0.2 --10 Unit V V dB Ohms mV
Table 11-1.
Parameter Operating Supply Voltage Output swing Voltage gain Input impedance Output offset voltage Output noise, 40dB gain, without power Supply and microphone contribution Slew-rate
onoise
--
-67
-62
dBV
SR
0.2
--
0.4
V/s
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Table 11-1.
Microphone Preamplifier (OP065) Electrical Specifications (Continued)
Symbol F-3 PM tSTUP ICC ISBY Not including microphone bias current Conditions 50 kOhms // 100 pF load 40 dB gain 50 kOhms // 100 pF load Min 15 45 ---Typ 18 50 40 15 -Max --50 30 1 Unit kHz s A A
Parameter Frequency response Phase margin Start-up time Supply current, active mode Supply current, stand-by mode
11.6
Control Modes
The Preamplifier can be enabled or disabled by activating the bit #1 (ONAMP) on the register 0x17. (See Section 8.5.18 "Microphone Amplifier Control".) Microphone Preamplifier Mode
onamp 0 1 Active Mode Stand By Mode Active Mode
The microphone bias of the preamplifier can be activated or deactivated by changing the bit #0 (ONMIC) on the register 0x17. (See Section 8.5.18 "Microphone Amplifier Control".) Microphone Bias Mode
onmic 0 1 Note: Microphone Bias Mode No Microphone Bias Microphone Bias Available when onmic = 0, the MIC pin is pulled down to the ground through a 3 kOhms resistor.
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11.7 Typical Application
Figure 11-2. Microphone Preamplifier Typical Application Diagram
560k
Cin 1F
micinn
6.8k + micout micout
vcm
Rbias - 2.2k
micb
2.2k OP065
10F
Rb1 - 100k
micn
Rb2 - 100k
10F
micp
Cmc
C2
vdda gnda
The OP065 is used as a 37 dB gain amplifier. Grounds of the microphone and the OP065 are common (GNDA in the schematic). The amplifier is internally supplied by VANA. A capacitive filter (C2) is added for the microphone supply, since its noise is amplified by the OP065 and then is very critical. A 10 uF minimum value is recommended. The gain can be attenuated simply by adding an input resistor in serie with MICINN input. The gain is also determined by Gv[dB] = 20.log(220000/(2200+Rsad)), with Rsad the additional input resistor added. The common mode input (VCM) is internally biased, and has to be decoupled with a 10 uF minimum external capacitor. It is very important for the total output noise. Care should be taken to avoid coupling between the input of the OP065 and noisy environments (digital power, burst mode of GSM, etc.) The input capacitor determines the low cut-off frequency with the internal 2.2 kOhms resistor: Fcutt-off = 0.159/(2200. Cin) with Cin: value of the input capacitor Cin.
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12. Power On/Off Procedure
There are two different inputs for supplying AT73C209. The first one, is to apply a cell on IN pin. The DC/DC converter should be activated by the ONOFF pin. The second one, is to apply a USB_Voltage on USB pin. Each power_up is described below.
12.1
DC/DC Power On/Off Operation
The Power-On of the DC/DC boost converter is activated by a push_button. The Power-Off of the DC/DC boost converter is controlled by the micro-controller MCU using 1 signal register. * The DC/DC boost converter is enabled with the ONOFF signal (Push_button activation). If ONOFF is high, the FB output voltage of the DC/DC converter begins to rise. The load resistor in this start-up phase must be higher than 10 KOhms. Once FB reaches the 2.4V threshold voltage, a DC/DC internal low-quiescent voltage supervisor sets the DC/DC internal STARTV signal to high (FB level). Then, the DC/DC output voltage FB rises to 3.3V. * The DC/DC boost converter is kept enabled by the micro-controller by setting the UPONOFF bit to high level (register 0x15, bit # 0). Then, the ONOFF signal can be released to 0. * Once FB reaches 2.4V threshold, a counter is started and after 256 cycles of internal oscillator, a reset signal (high level) is generated on RSTB pin. The reset time should be calculated as follows: (5kHz < F oscillator < 20kHz )
1 * 1 12, 8ms = 256 x ---------------------------------------------- < Reset - Time < 256 x --------------------------------------------- = 51, 2ms f OSCILLATOR - MIN f OSCILLATOR - MAX
* The off mode is entered as soon as the micro-controller resets the UPONOFF bit to 0 (provided ONOFF=0). Then, the DC/DC boost converter is disabled
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Figure 12-1. DC/DC Power On/Off Procedure Diagram
ONOFF With 1 Cell Supply
IN
Time UPONOFF
Time FB/VBOOST
2.4V 2.2V
Time RSTB VBOOST
Time 1 msec. 12.8 msec. up to 51.2 msec.
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12.2
USB Power On/Off Operation (USB Alone)
This paragraph describes the power on/off procedure if only a USB power supply is applied. The DC/DC converter is in Off Mode. When a voltage over 4.5V is applied on the USB pin, the LDO1 starts itself automatically. * The FB/VBOOST output voltage begins to rise. Once the output voltage reaches the 2.4V threshold voltage, an internal low-quiescent voltage supervisor sets the LDO1 enable signal to high. Then, the LDO1 output voltage rises to 3.4V. * Once FB/VBOOST reaches 2.4V threshold, a counter is started and after 256 cycles of internal oscillator, a reset signal (high level) is generated on RSTB pin. The reset time should be calculated as follows
1 * 1 12, 8ms = 256 x ---------------------------------------------- < Reset - Time < 256 x --------------------------------------------- = 51, 2ms f OSCILLATOR - MIN f OSCILLATOR - MAX
* The off mode is entered as soon as USB input voltage is removed or under 4.5V. Figure 12-2. USB Power ON/OFF Procedure Diagram
USB 5.5V 4.5V With USB SUpply
FB/VBOOST
Time
2.4V 2.2V
Time RSTB VBOOST
Time 1 msec. 12.8 msec. up to 51.2 msec.
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12.3 USB vs. DC/DC Power On/Off Operation
AT73C209 has a power selection priority. The USB pin powers the LDO1 and the IN pin powers the DC/DC Converter. If the output value of the DC/DC is higher than the LDO1 output value, then the LDO1 is stopped. If the output value of the LDO1 is higher than the DC/DC output value, then the DC/DC is put in standby mode. Figure 12-3. Power Supply Priority Diagram
USB LDO1 Stop FB/VBOOST DC/DC > LDO1 Standby IN LDO1
Using default values (In the registers), the power-on and power-off sequences when both power supplies are connected, should be as described below. Power On Sequence: A cell is connected to the IN pin. The DC/DC can be started by ONOFF pin activation and latched by UPONOFF bit activation. * FB output rises until 3.3V (default voltage value). * Once FB reaches 2.4V, a counter is launched and after "Reset-Time", a reset is generated on RSTB pin. * DC/DC is running. A USB power supply is connected on the USB pin. The LDO1 starts automatically. * FB/VBOOST rises to 3.4V (default voltage value). * The DC/DC is in Standby Mode Power Off Sequence: The USB power supply is disconnected from the USB pin. * The LDO1 is stopped * The DC/DC is start (in case of UPONOFF bit activated) * FB/VBOOST is falling down until 3.3V (default voltage value). The DC/DC is stopped when the UPONOFF bit is set to Low.
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Figure 12-4. USB vs. DC/DC Power On/Off Procedure Diagram (with Default Values)
IN
USB
Time
ONOFF
Time
UPONOFF
Time
FB/VBOOST 3.4V 3.3V 2.4V 2.2V
Time
RSTB Reset Time DCDC_ON
Time
Time
LDO1_ON
Time
Time
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12.4 Audio DAC Start-up Sequences
The power up of the circuit can be performed independently for several blocks. The figure below presents the sequence carried out for powering up a specific block XX where XX can be any of the several blocks described below0 Figure 12-5. DAC Startup DIagram
Circuit in Reset State (rstz low)
Disable Reset All Blocks are in Power Down (rstz high)
XX Block in Power Down
*Circuit pre-charging
User Controlled
On XX Set to High begin fastcharge
Fastcharge XX Set High
Fastcharge XX Set Low End Fastcharge
XX Block Ready
On XX Set to Low
= Register Write Operation
*Circuit must be in this state for the specified fastcharge interval.
The sequence flow starts by setting to High the block specific fast-charge control bit and subsequently the associated power control bit. Once the power control bit is set to High, the fast charging starts. This action begins a user controlled fast-charge cycle. When the fast-charge period is over, the user must reset the associated fast-charge bit and the block is ready for use. If a power control bit is cleared a new power up sequence is needed. The several blocks with independent power control are identified in Table 12-1 below. The table describes the power-on control and fast-charge bits for each block. Table 12-1. Power-on Control and Fast-charge Bits Table
Power On Control Bit onmstr (reg 0x0C; bit #0) onlnil (reg 0x00; bit #0) onlnir (reg 0x00; bit #1) onlnol (reg 0x00; bit #2) onlnor (reg 0x00; bit #3) ondacl (reg 0x00; bit #4) ondacr (reg 0x00; bit #5) Precharge Control Bit prcharge (reg 0x0C; bit #1) prchargeil (reg 0x0C; bit #2) prchargeir (reg 0x0C; bit #3) prchargeol (reg 0x0C; bit #4) prchargeor (reg 0x0C; bit #5) Not Needed Not Needed Powered Up Block Vref & Vcm generator Left line in amplifier Right line in amplifier Left line out amplifier Right line out amplifier Left D-to-A converter Right D-to-A converter
The power-on settling times for each of the different blocks are described in Table 12-1 below. 51
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Table 12-2.
Power On Signal osmstr onlnil onlnir onlnol onlnor ondacl ondacr Note:
Power On Settling Time
Power On Settling Time 500 ms 50 ms 50 ms 500 ms 500 ms 100 s 100 s Equivalent Charge Capacitance 10 F 2.2 F 2.2 F 100 F to 220 F 100 F to 220 F --Max dV/dt while Charging ---3V/sec. 3V/sec. ---
Powered Up Block Vref generator Left Line In Amplifier Right Line In Amplifier Left Line Out Amplifier Right Line Out Amplifier Left D to A Converter Right D to A Converter
All the blocks can be precharged simultaneously
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13. Interrupts
There are three possible interrupts. Two for USB (for Plugin and Unplug) and one for Headset Short-Circuit. These three interrupts generate a low signal on ITB output pin and are generated as described in the following paragraphs. To see each interrupt, it's necessary to mask it by using the register "INT_MASK" at 0x11 register address.
13.1
USB Interrupt
There are two interrupt generation possibilities for USB. USB Rising interrupt and USB Falling interrupt. The dedicated registers for these interrupts are 0x11 (MISC_STATUS) and 0x12 (INT_MASK). These registers are described below. (Only the used bits for USB interrupt are described. For more details, see Section 8.5.14 on page 23 and Section 8.5.15 on page 23.)
Register (0x11): Miscellaneous Status (MISC_STATUS)
Bit 1 Name USBOK Description USB Supply Flag Reset Value USBOK = 0
Register (0x12): Interrupt Mask (INT_MASK)
Bit 1 2 Name USBRMSK USBFMSK Description USB supply rising interrupt mask (1 to enable interrupt) USB supply falling interrupt mask (1 to enable interrupt) Reset Value USBRMSK = 0 USBFMSK = 0
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13.1.1
USB Rising Interrupt The sequence of USB Rising Interrupt generation, is shown below. Figure 13-1. USB Rising Interrupt DIagram
USB Vusb 4.5V
USBRMSK High Level
Time
USBFMSK High Level
Time
Time USBOK High Level
Time ITB High Level
Time Interrupt Generation
The sequence of the USB Rising Interrupt is described below. * Put bit #1 of register 0x12 to High * Plug USB input USB Mask Rising (USBRMSK) goes to High bit #1 of register 0x11 (USBOK), goes to High Level ITB output goes to Low Level * Put bit #1 of register 0x12 to Low USB Mask Rising (USBRMSK) goes to Low bit #1 of register 0x11 (USBOK), stay to High Level ITB output goes to High Level 54
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13.1.2
USB Falling Interrupt The Falling Interrupt generation sequence is shown below. Figure 13-2. USB Falling Interrupt Diagram
USB Vusb 4.5V
USBRMSK High Level
Time
USBFMSK High Level
Time
USBOK High Level
Time
ITB High Level
Time
Time Interrupt Generation
The sequence of the USB Falling Interrupt is described below.
* Put bit #2 of register 0x12 to High * Unplug USB input
USB Mask Rising (USBRMSK) goes to High bit #1 of register 0x11 (USBOK), goes to Low Level ITB output goes to Low Level USB Mask Rising (USBRMSK) goes to Low bit #1 of register 0x11 (USBOK), stays at Low Level ITB output goes to Low Level
* Put bit #2 of register 0x12 to Low
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13.2
Headset Short-Circuit Interrupt
There is one interrupt generation for Headset Short-Circuit (see diagram below). The dedicated registers for this interrupt are 0x11 (MISC_STATUS) and 0x12 (INT_MASK). These registers are described below. (Only the used bits for Headset Short-Circuit interrupt are described. For more details, see Section 8.5.14 on page 23 and Section 8.5.15 on page 23.)
Register (0x11): Miscellaneous Status (MISC_STATUS)
Register 0x11 0x12 Bit 0 0 Name HSSHORT HSSMSK Description Headset Short Flag Headset short interrupt mask (1 to enable interrupt) Reset Value HSSHORT = 0 HSSMSK = 0
13.2.1
Headset Short-Circuit Sequence
Figure 13-3. Headset Short-Circuit Interrupt Diagram
Headset Driver Output Headset Short Circuit Headset Driver Off
Headset Driver Off
Short-Circuit on Headset Driver
Headset Driver Off
HSSMSK High Level HSSHORT High Level ITB
Time
Time
High Level
Time
Time Debounce
The sequence of the Head Short-Circuit Interrupt is described below. * Put bit #0 of register 0x12 to High. * Power on the headset output driver. After Debounce Time bit #0 of register 0x11 * Make a short circuit on the headset output (right or left channel. (HSSHORT), goes to High Level. Then ITB output goes to High Level. The Headset Short Circuit Flag (HSSHORT) should be removed by switching off the headset driver. Headset Short-Circuit Mask (HSSMSK) goes to High.
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The ITB signal (Interrupt Output) should be removed by putting bit #0 of register 0x12 (HSSMSK) to Low. 13.2.2 Debounce Time The debounce time depends on the internal oscillator deviation. It operates after 512 cycles of internal oscillator period time. It should be calculated as follows: Debounce - Time equation:
1 Debounce - Time = 512 x ------------------------------- f OSCILLATOR
Internal Frequency Oscillator Deviation:
5kHz < f OSCILLATOR < 20kHz
Debounce-Time Min. and Max.:
** 25 ,6ms < Debounce - Time < 104 ,2ms
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14. Current Consumption in Different Modes
Table 14-1.
Mode 0: Off Internal Monitoring Total 1: Standby No Play DC/DC is on MCU & Nand Flash Ready Total 2: Play DC/DC is on MCU Flash Reading Audio DAC Headset 0dB Total 3: Record DC/DC is on MCU Flash Writing Audio DAC Headset 0dB Total TBD 45 TBD 45 TBD 10 TBD 10
Current Consumption with Battery Operation
Current Consumption (typ) Current Consumption (max) Unit A
mA
mA
mA
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15. Package Drawing
Figure 15-1. Package Outline
Package Type: QFN32, 7x7mm
Notes: 1. All dimensions are in mm. 2. Drawing is for general information only. Refer to JEDEC drawing MO-220 for additional information.
Figure 15-2. Package Drawing with Pin 1 and Marking (Bottom View)
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16. Revision History
Table 16-1.
Doc. Rev.
Revision History
Date 12-Mar-08 Comments First issue. Change Request Ref.
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Table of Contents
Features ..................................................................................................... 1 1 2 3 4 5 6 7 8 Description ............................................................................................... 1 Block Diagram .......................................................................................... 3 Application Diagram ................................................................................ 4 Components List ...................................................................................... 5 Pin Description ......................................................................................... 6 Absolute Maximum Ratings .................................................................... 7 Digital IOs ................................................................................................. 7 SPI Interface ............................................................................................. 8
8.1 8.2 8.3 8.4 8.5 SPI architecture .................................................................................................8 SPI Protocol .......................................................................................................8 Timing Diagram for SPI Interface ......................................................................9 SPI Timing .........................................................................................................9 SPI Register Tables ...........................................................................................9
9
Power Supplies ...................................................................................... 28
9.1 9.2 9.3 DC to DC Boost Converter (SW1) ...................................................................28 LDO1: 3.3V From USB Port ............................................................................31 LDO2: 2.4V to 3.0V for Internal Analog Section Supply ..................................33
10 Audio DAC .............................................................................................. 36
10.1 10.2 10.3 10.4 10.5 Description .......................................................................................................36 Functional Diagram .........................................................................................36 Electrical Specifications ...................................................................................37 Data Interface ..................................................................................................40 Timing Specifications .......................................................................................41
11 Microphone Preamplifier (OP065) ........................................................ 42
11.1 11.2 11.3 11.4 11.5 11.6 Features ..........................................................................................................42 Description .......................................................................................................42 Functional Diagram .........................................................................................42 Detailed Description ........................................................................................43 Electrical Specifications ...................................................................................43 Control Modes .................................................................................................44 i
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11.7
Typical Application ...........................................................................................45
12 Power On/Off Procedure ....................................................................... 46
12.1 12.2 12.3 12.4 DC/DC Power On/Off Operation ......................................................................46 USB Power On/Off Operation (USB Alone) .....................................................48 USB vs. DC/DC Power On/Off Operation ........................................................49 Audio DAC Start-up Sequences ......................................................................51
13 Interrupts ................................................................................................ 53
13.1 13.2 USB Interrupt ...................................................................................................53 Headset Short-Circuit Interrupt ........................................................................56
14 Current Consumption in Different Modes ............................................ 58 15 Package Drawing ................................................................................... 59 16 Revision History ..................................................................................... 60 Table of Contents....................................................................................... i
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Headquarters
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