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EN5396QI
9A Synchronous Buck PWM DC-DC Converter with Integrated Inductor External Output Voltage Programming
RoHS Compliant
Description
The EN5396QI is a Power Supply on a Chip (PwrSoC) DC-DC converter. It is specifically designed to meet the precise voltage and fast transient requirements of present and future high-performance, low-power processor, DSP, FPGA, ASIC, memory boards, and system level applications in a distributed power architecture. Advanced circuit techniques, ultra high switching frequency, and innovative, high-density, integrated circuit and proprietary inductor technology deliver high-quality, ultra compact, non-isolated DC-DC conversion. Operating this converter requires as few as five external components that include small value input and output ceramic capacitors and a soft-start capacitor. The Enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. In addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings.
Features
10mm
12mm
* * * * * * * * * * * * * *
Applications
* * * * * * Point of load regulation for low-power processors, network processors, DSPs, FPGAs, and ASICs Notebook computers, servers, workstations Broadband, networking, LAN/WAN, optical Low voltage, distributed power architectures with 2.5V, 3.3V or 5V rails DSL, STB, DVR, DTV, Industrial PC Noise sensitive applications
Integrated Inductor Technology: Integrated Inductor, MOSFETS, Controller in a 10 x 12 x 1.85mm package Low External Part Count. Up to 30W continuous output power. Low output impedance optimized for 90 nm Master/slave configuration for paralleling. 5MHz operating frequency. High efficiency, up to 93%. Wide input voltage range of 2.375V to 5.5V. External resistor divider output voltage select. Output Enable pin and Power OK signal. Programmable soft-start time. Adjustable over-current protection. Thermal shutdown, short circuit, over-voltage and under-voltage protection. RoHS compliant, MSL level 3, 260C reflow.
Typical Application Circuit
VIN 2 x 47F 1
PVIN AVIN ENABLE PGND SS XOV XFB VOUT
VOUT 2 x 47F
15nF
AGND PGND
Ordering Information
Part Number EN5396QI-T EN5396QI-E Temp Rating (C) Package -40 to +85 58-pin QFN T&R QFN Evaluation Board
Figure 1. Simple Layout.
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Pin Configuration
Below is a top view diagram of the EN5396Q package. NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
Figure 2. Pin Diagram, top view.
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Pin Descriptions
PIN
1-3 4-5 6-13 14-20 21-22 23 24-29 30-35 36-37 38 39 40 41-42 43 44 45 46 47 48 49 50 51 52 53 54 55 56-58
NAME
NC NC(SW) NC VOUT NC(SW) NC PGND PVIN NC ROCP AVIN AGND NC XFB XOV NC POK NC SS EAIN EAOUT COMP ENABLE PWM NC M/S NC
FUNCTION
NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally. NO CONNECT - These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally. Regulated converter output. Connect these pins to the load and place output capacitor from these pins the PGND pins 24-26. NO CONNECT - These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally. Output power ground. Refer to layout guideline section. Input power supply. Connect to input power supply. Decouple with input capacitor to PGND. NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally. Optional Over Current Protection adjust pin. Place ROCP resistor between this pin and AGND (pin 40) to adjust the over current trip point. Analog voltage input for the controller circuits. Connect this pin to the input power supply. Analog ground for the controller circuits. NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally. Feedback pin for external voltage divider network. Over voltage programming feedback pin. NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally. Power OK is an open drain transistor for power system state indication. POK is a logic high when VOUT is with -10% to +20% of VOUT nominal. NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally. Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value of this capacitor determines the startup timing. Optional Error Amplifier input. Allows for customization of the control loop. Optional Error Amplifier output. Allows for customization of the control loop. Output of the buffer leading to the error amplifier. Used for external modifications of the compensation network. Input Enable. Applying a logic high, enables the output and initiates a soft-start. Applying a logic low disables the output. PWM input/output. Used for optional master/slave configuration. When M/S pin is asserted "low", PWM will output the gate-drive PWM waveform. When the M/S pin is asserted "high", the PWM pin is configured as an input for PWM signal from the "master" device. PWM pin can drive up to 3 slave devices. NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally. Optional Master/Slave select pin. Asserting pin "low" places device in Master Mode for current sharing. PWM pin (53) will output PWM drive signal. Asserting pin "high" will place the device in Slave Mode. PWM pin (53) will be configured to input (receive) PWM drive signal from "Master" device. NO CONNECT - This pin should not be electrically connected to any external signal, voltage, or ground, but must be soldered to PCB. This pin may be connected internally.
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Block Diagram
POK PVIN
UVLO Thermal Limit ROCP Current Limit Over Voltage XOV Over Voltage VOUT Power Good Logic
P-Drive
NC(SW) VOUT
(-) (+ ) PWM Comp N-Drive PGND
Sawtooth Generator
Compensation Voltage Selector
VSENSE
(-) Error Amp ENABLE
XFB
(+ )
SS
Soft Start
Reference Voltage selector Bandgap Reference
EAOUT
EAIN
COMP AVIN
AGND
Figure 3. System block diagram.
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Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER
Input Supply Voltage Voltages on: ENABLE, VSENSE, XFB, XOV, M/S Voltages on: EAIN, EAOUT, COMP Voltages on: SS, PWM Voltages on: POK Storage Temperature Range Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A ESD Rating (based on Human Body Model)
SYMBOL
VIN
MIN
-0.5 -0.5 -0.5 -0.5 -0.5 -65 2000
MAX
7.0 VIN 2.5 3.0 VIN + 0.3 150 260
UNITS
V V
TSTG
C C V
Recommended Operating Conditions
PARAMETER SYMBOL MIN
2.375 0.75 0 -40 -40
MAX
5.5 VIN - VDROPOUT 9 +85 +125
UNITS
V V A C C
Input Voltage Range VIN Output Voltage Range (NOTE: 1) VOUT Output Current (NOTE 2) IOUT Operating Ambient Temperature TA Operating Junction Temperature TJ Note 1: VDROPOUT = ILOAD x Dropout Resistance Note 2: Reference figures 5 and 6 for the Output Current Derating Curves.
Thermal Characteristics
PARAMETER SYMBOL TYP UNITS
C/W C/W C C Thermal Resistance: Junction to Ambient (0 LFM) (Note 3) JA 18 Thermal Resistance: Junction to Case (0 LFM) JC 1.5 Thermal Overload Trip Point TJ-TP +150 Thermal Overload Trip Point Hysteresis 20 Note 3: Based on four layer board and proper thermal design in line with JEDEC EIJ/JESD 51 standards
Electrical Characteristics
NOTE: VIN=5.5V over operating temperature range unless otherwise noted. Typical values are at TA = 25C. PARAMETER
VOUT Initial Accuracy Overall VOUT Accuracy (Line, Load, and Temperature combined) Transient Response Peak Deviation Under Voltage Lock out threshold
SYMBOL
VOUT_INIT VOUT_ALL
TEST CONDITIONS
TA = 25C, 2.375V VIN 5.5V ILOAD = 1A; TA = 25C 2.4V VIN 5.5V -40C TA +85C 0A ILOAD 9A (IOUT = 0% to 100% or 100% to 0% or rated load) VIN = 5V, 1.2V VOUT 3.3V COUT = 2 x 47 F VIN Increasing VIN Decreasing
MIN
-2 -3%
TYP
MAX
2 +3%
UNITS
%
VOUT VUVLO
3 2.2 2.1
% V
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PARAMETER
Switching Frequency Continuous Output Current
SYMBOL
FSWITCH
TEST CONDITIONS
2.375V VIN 5.5V 0.603 MIN
TYP
5
EN5396QI MAX UNITS
MHz
IOUT
9
A
Current Limit Threshold Shut-Down Supply Current Disable Threshold Enable Threshold Enable Pin Current POK threshold High POK threshold Low POK Low Voltage POK High Voltage Dropout Resistance Current Balance
IOCP_TH IS VDISABLE VENABLE IEN
11 50 0.8 1.8 2.0 50 120 90 0.4 VIN 50
A A V V A % % V V m %
IOUT
With 2 - 4 converters in parallel, the difference between any 2 parts. VIN < 50mV; RTRACE < 10m.
+/-10
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Typical Performance Characteristics
Circuit of Figure 1, VIN = 5 V, VOUT = 1.2 V and TA = 25C, unless otherwise noted.
Efficiency (VIN =3.3V) 95 90 Efficiency (%) 80 75 70 65 60 0 2 4 6 8 10 Load (Amperes)
Efficiency (%) 95 90 85 80 75 70 65 60 55 50 0 2 4 6 8 10 Load (Amperes) Efficiency (Vin = 5.0V)
85
Top to Bottom: VOUT = 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V
Top to Bottom: VOUT = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V
Ripple Voltage, 5.5VIN/1.2VOUT, IOUT=9A, COUT = 5x22uF.
Ripple Voltage, 3.3VIN/1.2VOUT, IOUT=9A, COUT = 5x22uF.
Transient Response: 5VIN/1.2VOUT, 0-9A, 7A/uS. COUT = 5x22uF.
Transient Response: 5VIN/3.3VOUT, 0-9A, 7A/uS. COUT = 5x22uF
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Start up waveforms VIN=5.0V, VOUT=1.2V, CSS=15nF, Ch 1 = VOUT, Ch 3 = ENABLE, Ch 4 = POK.
Start up waveforms VIN=5.0V, VOUT=3.3V, CSS=15nF, Ch 1 = VOUT, Ch 3 = ENABLE, Ch 4 = POK.
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EN5396QI
Functional Description
The EN5396QI is a synchronous, pin programmable power supply with integrated power MOSFET switches and integrated inductor. The nominal input voltage range is 2.375-5.5V. The output voltage is programmed using an external resistor divider network. The feedback control loop is a type III voltage-mode and the part uses a low-noise PWM topology. Up to 9A of output current can be drawn from this converter. The 5MHz operating frequency enables the use of small-size output capacitors. The power supply has the following protection features: * Programmable over-current protection (to protect the IC from excessive load current) * Thermal shutdown with hysteresis. * Over-voltage protection * Under-voltage lockout circuit to disable the converter output when the input voltage is less than approximately 2.2V Additional features include: * Soft-start circuit, limiting the in-rush current when the converter is powered up. * Power good circuit indicating whether the output voltage is within 90%-120% of the programmed voltage.
Ra1 = (Vout - 0.75V ) * Rb1 0.75V
If over-voltage protection is desired, use the following equation to set the resistor Ra2 for the desired OVP trip-point:
Ra 2 = (OVPtrip - 0.90V ) * Rb 2 0.90V
By design, if both resistor dividers are the same, the OV trip-point will be 20% above the nominal output voltage.
VIN
2x 47F CSS
AGND PGND
PVIN
POK
VOUT
VOUT Ra2 Rb2 Ra1
2 x 47F
XOV AVIN SS XFB
Rb1
Figure 4. VOUT and OVP resistor divider networks. NOTE: if no OVP divider is present, there will be no overvoltage protection and POK will remain "high" as long as VOUT remains above 90% of the nominal VOUT setting.
Programming Output Voltage and OVP
The EN5396 output voltage is programmed using a simple resistor divider network. Figure 4 shows the resistor divider configuration. The EN5396 output voltage and over voltage thresholds are determined by the voltages presented at the XFB and XOV pins respectively. These voltages are set by way of resistor dividers between VOUT and AGND with the midpoint going to XFB and XOV. It is recommended that Rb1 and Rb2 resistor values be ~2k. Use the following equation to set the resistor Ra1 for the desired output voltage:
Input Capacitor Selection
The EN5396QI requires approximately 100uF of input capacitance. Low ESR ceramic capacitors are required with X5R or X7R rated dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. In some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling.
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EN5396QI Recommended input capacitors.
Description
47uF, 10V, X5R, 1210 (2 capacitors needed)
MFG
Murata Taiyo Yuden
P/N
GRM32ER61A476KE20L LMK325BJ476MM-T
Output Capacitor Configuration 2 x 47uF 5 x 22 uF
Typical Output Ripple (mVp-p) (as measured on EN5396QI Evaluation Board) 20 12
Output Capacitor Selection
The EN5396QI has been optimized for use with approximately 100F of output capacitance. Low ESR ceramic capacitors are required with X5R or X7R rated dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these loose capacitance with frequency, temperature and bias voltage. Recommended output capacitors.
Description 22uF, 6.3V, 10% X5R, 1206 (5 capacitors needed) 47uF, 10V, 10% X5R, 1210 47uF, 6.3V, 10% X5R, 1210 (2 capacitors needed) MFG Murata Taiyo Yuden Murata AVX P/N GRM31CR60J226KE19L JMK316BJ226KL-T GRM32ER61A476KE20L 12106D476KAT2
Enable Operation
The ENABLE pin provides a means to shut down the device, or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. When the ENABLE pin is asserted high, the device will undergo a normal soft start.
Soft-Start Operation
Soft start is a method to reduce in-rush current when the device is enabled. The output voltage is ramped up slowly upon start-up. The output rise time is controlled by choice of a soft-start capacitor, which is placed between the SS pin (pin 48) and the AGND pin (pin 40). Rise Time: TR = Css* 80K During start-up of the converter, the reference voltage to the error amplifier is gradually increased to its final level by an internal current source of typically 10uA. Typical soft-start rise time is 1mS to 3mS. Typical SS capacitor values are in the range of 15nF to 30 nF.
Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance, denoted as Z, is comprised of effective series resistance, ESR, and effective series inductance, ESL: Z = ESR + ESL. Placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage.
1 Z Total = 1 1 1 + + ... + Z1 Z 2 Zn
POK Operation
The POK signal is an open drain signal from the converter indicating the output voltage is within the specified range. The POK signal will be a logic high when the output voltage is within 90% 120% of the programmed output voltage. If the output voltage goes outside of this range, the POK signal will be a logic low until the output voltage has returned to within this range. In the event of an over-voltage condition the POK signal will go low and will remain in this condition until the output voltage has dropped to 95% of the programmed output voltage before returning to the high state. The internal POK FET is designed to tolerate up to 4mA. The pull-up resistor value should be
Typical ripple versus capacitor arrangement is given below (5.5VIN/1.2VOUT):
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chosen to limit the current from exceeding this value when POK is logic low.
Over-Current Protection
When an over current condition occurs, VOUT is pulled low. This condition is maintained for a period of 1.2 ms and then a normal soft start cycle is initiated. If the over current condition still persists, this cycle will repeat. The OCP trip point is nominally set to 150% of maximum rated load. It is possible to increase the OCP trip point to 200% of the maximum rated load by connecting a 5k resistor between the ROCP pin (pin 38) and AGND (pin 39). This option is intended for startup into capacitive loads such as certain FPGAs and ASICs.
EN5396QI types.) Voltage mode operation provides high noise immunity at light load. In some cases modifications to the compensation may be required. The EN5396QI provides access to the internal compensation network to allow for customization. For more information, contact Enpirion Applications Engineering support.
Parallel Device Operation
In order to power a load that is higher than the rated 9A of the EN5396, from 2 to 4 devices can be placed in parallel for providing a single load with up to 24A of output current. Paralleling more than 1 device is accomplished by selecting a master device and tying that M/S pin to AGND. All slave devices should have their M/S pin tied to AVIN. The PWM pin from the master device is connected to all slave device PWM pins. The PWM signal is a 5 MHz drive signal and must be routed appropriately. (See Figure 4.) 1. All master and slave devices should have identical placement and values of input, output and soft-start capacitors. 2. All master and slave devices should have their ENABLE pins tied together and should be operated simultaneously with a fast rising edge of 10 uSec or less, to ensure that devices start up at the same time. Startup imbalance could lead to OCP condition on first device to startup. 3. The maximum board trace resistance between any 2 devices VOUT pins should be less than 10m. 4. The maximum difference of PVIN between any 2 devices should be less than 50mV.
Over-Voltage Protection
When the output voltage exceeds 120% of the programmed output voltage, the PWM operation stops, the lower N-MOSFET is turned on and the POK signal goes low. When the output voltage drops below 95% of the programmed output voltage, normal PWM operation resumes and POK returns to its high state.
Thermal Overload Protection
Thermal shutdown will disable operation once the Junction temperature exceeds approximately 150C. Once the junction temperature drops by approx 20C, the converter will re-start with a normal soft-start.
Input Under-voltage Lock-out
Circuitry is provided to ensure that when the input voltage is below the specified voltage range, the converter will not start-up. Circuits for hysteresis, input de-glitch and output leading edge blanking are included to ensure high noise immunity and prevent false tripping.
Compensation
The EN5396 is internally compensated through the use of a type 3 compensation network and is optimized for use with about 50F of output capacitance and will provide excellent loop bandwidth and transient performance for most applications. (See the section on Capacitor Selection for details on recommended capacitor
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Figure 4 . Paralleling of two devices.
Figure 5. Output Current Derating Curve, VIN = 5.0V
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Figure 6 . Output Current Derating Curve, VIN = 3.3V
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Layout Recommendations
VIN(+) Plane VOUT(+) Plane Slit separating input local ground from output local ground
Package Outline Output Capacitor Landing Pads Output Local Ground Plane
Vias to System Ground Plane
Local Ground Plane
Input Capacitor Landing Pads Input Local Ground Plane
Figure 7. Layout of power and ground planes.
Figure 8. Use of vias connecting local and system ground.
Recommendation 1: Input and output capacitors should be placed as close to the EN5396QI package as possible to reduce EMI from input and output loop currents. This reduces the physical area of the Input and Output AC current loops. Recommendation 2: Place a slit in the input/output capacitor ground plane just beyond the common connection point of the GND pins of the device as shown in figure 7. Recommendation 3: Multiple small (0.25mm) vias should be used to connect ground terminal of the Input capacitor and the output capacitor to the system ground plane as shown in figure 8. Recommendation 4: The large thermal pad underneath the component must be connected to the system ground plane through as many
vias as possible. The diameter of the vias should be less than 0.3mm. This provides the quiet, or analog ground for the converter and also provides the path for heat dissipation from the converter. A later section of this note makes a recommendation on the PCB footprint. Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input and output capacitors that carry large AC currents. Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or control lines underneath the converter package.
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Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, , and in overall foot print. However, they do require some special considerations. In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package. Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN5396QI should be clear of any metal except for the large thermal pad. The "grayed-out" area in Figure 9 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the PCB. Figure 10 demonstrates the recommended PCB footprint for the EN5396QI. Figure 11 shows the shape and location of the exposed metal pads as well as the mechanical dimension of the large thermal pad and the pins.
Figure 9. Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
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Figure 10. Recommended footprint for PCB.
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Package Dimensions
Figure 11. Package dimensions.
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TAPE AND REEL SPECIFICATION
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Contact Information
Enpirion, Inc. Perryville III 53 Frontage Road, Suite 210 Hampton, NJ 08827 Phone: 908-894-6000 Fax: 908-894-6090
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion.
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