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V e r s i o n 2 .0 , 1 1 S e p 2 00 8
CoolSET -F3R
ICE3BR2565JF
Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS(R) and Startup cell (frequency jitter Mode) in FullPak
(R)
Power Management & Supply
Never
stop
thinking.
CoolSET(R)-F3R ICE3BR2565JF Revision History: Previous Version: Page 15 17,18 19 19 23 24~28 29,30 31 32
2008-09-11 0.2
Datasheet
Subjects (major changes since last revision) Add max. limitation for CBK capacitance Revise description of protection mode. Add constrains of 25.5V Vcc OVP Revise max. voltage for VFB, VCS and VBA Revise ID_Puls to Tj=125C and add the avalanche rating Add Drain Source Avalanche Breakdown Voltage Add typical controller performance characteristics Add typical CoolMOS(R) performance characteristics Add input power curve Revise outline dimension
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOS(R), CoolSET(R) are trademarks of Infineon Technologies AG.
Edition 2008-09-11 Published by Infineon Technologies AG, 81726 Munich, Germany, (c) 2008 Infineon Technologies AG. All Rights Reserved. Legal disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies Office. Infineon Technologies Components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
CoolSET(R)-F3R
ICE3BR2565JF
Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS(R) and Startup cell (frequency jitter Mode) in FullPak
Product Highlights * TO220 FullPak with low Rdson MOSFET for high power application * Active Burst Mode to reach the lowest Standby Power Requirements < 100mW * Auto Restart protection for overload, overtemperature, overvoltage * External auto-restart enable function * Built-in soft start and blanking window * Extendable blanking Window for high load jumps * Built-in frequency jitter and soft driving for low EMI * Green Mould Compound * Pb-free lead plating; RoHS compliant 650V avalanche rugged CoolMOS(R) with built-in Startup Cell Active Burst Mode for lowest Standby Power Fast load jump response in Active Burst Mode 67kHz internally fixed switching frequency Auto Restart Protection Mode for Overload, Open Loop, VCC Undervoltage, Overtemperature & Overvoltage Built-in Soft Start Built-in blanking window with extendable blanking time for short duration high current External auto-restart enable pin Max Duty Cycle 75% Overall tolerance of Current Limiting < 5% Internal PWM Leading Edge Blanking BiCMOS technology provide wide VCC range Built-in Frequency jitter and soft driving for low EMI
PG-TO220FS-6
PG-TO220-6-247
Features
* * * * * * * * * * * * *
Description
The CoolSET(R)-F3R FullPak is the enhanced version of CoolSET(R)-F3 and targets for the Off-Line Adapters and high power range SMPS in DVD R/W, DVD Combi, set top box, etc. It has a wide Vcc range to 25V by adopting the BiCMOS technology. With the merit of Active Burst Mode, it can achieve the lowest Standby Power Requirements (<100mW) at no load and Vin = 270VAC. Since the controller is always active during the Active Burst Mode, it is an immediate response on load jumps and leads to <1% voltage ripple voltage at output. In case of protection for Overtemperature, Overvoltage, Open loop and Overload conditions, it would enter Auto Restart Mode. Thanks for the internal precise peak current limitation, it can provide accurate information to optimize the dimension of the transformer and the output diode. The built-in blanking window can provide sufficient buffer time before entering the Auto Restart Mode. In case of longer blanking time, a simply addition of capacitor to BA pin can serve the purpose. Furthermore, the built-in frequency jitter function can effectively reduce the EMI noise and further reduce the scale of input filter. The component counts can further be reduced with the various built-in functions such as soft start, blanking time and frequency jitter.
Typical Application
+
85 ... 270 VAC
CBulk CVCC VCC
Snubber
Converter DC Output
-
Drain
Startup Cell
Power Management PWM Controller Current Mode Precise Low Tolerance Peak Current Limitation Active Burst Mode Auto Restart Mode CoolMOS(R)
CS RSense FB
GND
Control Unit
BA
CoolSET(R)-F3R
( Jitter )
Type ICE3BR2565JF
1) 2)
Package PG-TO220-6-247
VDS 650V
FOSC 67kHz
RDSon1) 2.56
230VAC 15% 106W
2)
85-265 VAC 81W2)
typ @ Tj=25C Calculated maximum input power in an open frame design at Ta=50C, Tj=125C and RthSA (external heatsink) = 2.7K/W. Refer to input power curve for other Ta.
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CoolSET(R)-F3R ICE3BR2565JF
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 3.3.1 3.3.2 3.4 3.5 3.5.1 3.5.2 3.5.3 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.7.2.1 3.7.2.2 3.7.2.3 3.7.3 3.7.3.1 3.7.3.2 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 5 Page
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Configuration with PG-TO220-6-247 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Auto Restart mode with extended blanking time . . . . . . . . . . . . . . . . .17 Auto Restart without extended blanking time . . . . . . . . . . . . . . . . . . .18 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 CoolMOS(R) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Typical Controller Performance Characteristics . . . . . . . . . . . . . . . . . .24
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CoolSET(R)-F3R ICE3BR2565JF
Table of Contents 6 7 8 9 10 Page
Typical CoolMOS(R) Performance Characteristics . . . . . . . . . . . . . . . . . .29 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .34
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Pin Configuration and Functionality
1
1.1
Pin Configuration and Functionality
Pin Configuration with PG-TO220-6247
1.2
Pin Functionality
Drain (Drain of integrated CoolMOS(R)) Pin Drain is the connection to the Drain of the internal CoolMOS(R) and the HV of the startup cell. CS (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the integrated CoolMOS(R). If CS voltage reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWMComparator to realize the Current Mode. BA (extended Blanking & Auto-restart enable) The BA pin combines the functions of extendable blanking time for over load protection and the external auto-restart enable. The extendable blanking time function is to extend the built-in 20 ms blanking time by adding an external capacitor at BA to ground. The external auto-restart enable function is an external access to stop the gate switching and force the IC to enter auto-restart mode. It is triggered by pulling down the BA pin to less than 0.33V. VCC (Power Supply) The VCC pin is the positive supply of the IC. The operating range is between 10.5V and 25V. GND (Ground) The GND pin is the ground of the controller.
Pin 1 2 3 4 5 6
1)
Symbol Drain CS BA VCC GND FB
Function 650V1) CoolMos(R) Drain Current Sense/ 650V1) CoolMOS(R) Source extended Blanking & external Auto Restart enable Controller Supply Voltage Controller Ground Feedback
at Tj=110C
Package PG-TO220-6-247
1
2
3
4
5
6
Drain
GND
VCC
CS
BA
Figure 1
Pin Configuration PG-TO220-6-247 (front view)
Version 2.0
FB
FB (Feedback) The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal PWM-Comparator to control the duty cycle. The FBSignal is the only control signal in case of light load at the Active Burst Mode.
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2
Figure 2
Version 2.0
+ CBulk Snubber Converter DC Output VOUT CVCC
85 ... 270 VAC
VCC
Power Management Internal Bias Voltage Reference 5.0V
Drain
CoolMOS(R) Startup Cell
3.25k
5.0V
IBK
T2
T3
0.6V
GND
Undervoltage Lockout
18V 0.75 10.5V
Auto-restart BA Enable Signal #1 CBK Power-Down Reset & G1 1 ms counter Soft Start Soft-Start Comparator
Clock Freq. jitter Duty Cycle max
T1 Oscillator PWM Section
#2
Representative Blockdiagram
Tj >130C
TAE
VCC
0.9V
20.7V
C1
VCC
C2 Gate Driver & G9
120us Blanking Time
25.5V Soft Start Block C7 1 G8 PWM Comparator & G5 Propagation-Delay Compensation
0.68V
Thermal Shutdown & G7 FF1 S RQ
0.33V
C9
Representative Blockdiagram
7
C8 Spike Blanking 30us Auto Restart Mode Active Burst Mode C10 x3.3 PWM OP C12 & G11 Current Mode & G10 10k 1pF D1 20ms Blanking Time & G6 Vcsth Leading Edge Blanking 220ns 0.26V Current Limiting
S1
4.0V
C3
1 G2
5.0V
RFB
4.5V
C4
25k
20ms Blanking Time
FB
1.22V
C5
CS
RSense
2pF
3.6V
C6a
Control Unit
3.1V
C6b
ICE3BRxx65JF / CoolSET(R)-F3R ( Jitter Mode & FullPak)
CoolSET(R)-F3R ICE3BR2565JF
Representative Blockdiagram
# : optional external components; #1 : CBK is used to extend the Blanking Time #2 : TAE is used to enable the external Auto-restart feature
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CoolSET(R)-F3R ICE3BR2565JF
Functional Description
3
Functional Description
condition which could otherwise lead to a destruction of the SMPS over time. Once the malfunction is removed, normal operation is automatically recovered after the next Start Up Phase. The internal precise peak current limitation reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage which is required for wide range SMPS. There is no need for an extra over-sizing of the SMPS, e.g. the transformer or the secondary diode. Furthermore, this full package version implements the frequency jitter mode to the switching clock such that the EMI noise will be effectively reduced.
All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered.
3.1
(R)
Introduction
CoolSET -F3R FullPak is the further development of the CoolSET(R)-F3 for high power application. The particular enhanced features are built-in features for soft start, blanking window and frequency jitter. It also provides the flexibility to increase the blanking window by simply adding capacitance in BA pin. However, the proven outstanding features in CoolSET(R)-F3 are remained. The intelligent Active Burst Mode at Standby Mode can effectively obtain the lowest Standby Power at minimum load and no load condition. After entering the burst mode, there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on Vout is minimized. Vout is on well controlled in this mode. The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 18V is exceeded. This Startup Cell is part of the integrated CoolMOS(R). The external startup resistor is no longer necessary as this Startup Cell is connected to the Drain. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically. This version is adopting the BiCMOS technology and it can increase design flexibility as the Vcc voltage range is increased to 25V. For this full package version, the soft start is a built-in function. It is set at 20ms. Then it can save external component counts. There are 2 modes of blanking time for high load jumps; the basic mode and the extendable mode. The blanking time for the basic mode is pre-set at 20ms while the extendable mode will increase the blanking time at basic mode by adding external capacitor at the BA pin. During this time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window. In order to increase the robustness and safety of the system, the IC provides Auto Restart protection mode. The Auto Restart Mode reduces the average power conversion to a minimum under unsafe operating conditions. This is necessary for a prolonged fault
3.2
D rain
Power Management
VC C Startup C ell
C oolM O S (R)
Power M anagem ent Internal Bias U ndervoltage Lockout 18V 10.5V
Pow er-Down Reset
Voltage Reference
5.0V
Auto R estart M ode
Soft Start block
Active Burst M ode
Figure 3
Power Management
The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the VCC pin. This VCC charge current is controlled to 0.9mA by the Startup Cell. When the VVCC exceeds the on-threshold VCCon=18V the bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power
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CoolSET(R)-F3R ICE3BR2565JF
Functional Description
losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on a hysteresis start up voltage is implemented. The switch-off of the controller can only take place after Active Mode was entered and VVCC falls below 10.5V. The maximum current consumption before the controller is activated is about 150A. When VVCC falls below the off-threshold VCCoff=10.5V, the bias circuit is switched off and the soft start counter is reset. Thus it is ensured that at every startup cycle the soft start starts at zero. The internal bias circuit is switched off if Auto Restart Mode is entered. The current consumption is then reduced to 250A. Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require re-cycling the AC line. When Active Burst Mode is entered, the internal Bias is switched off most of the time in order to reduce the current consumption below 500A.
Amplified Current Signal FB 0.68V Driver t
ton t
Figure 5 Pulse Width Modulation
3.3
Improved Current Mode
Soft-Start Comparator PWM-Latch C8
R Q
FB
Driver
S 0.68V Q
PWM OP x3.3 Improved Current Mode
Figure 4 Current Mode
CS
Current Mode means the duty cycle is controlled by the slope of the primary current. This is done by comparing the FB signal with the amplified current sense signal.
In case the amplified current sense signal exceeds the FB signal the on-time ton of the driver is finished by resetting the PWM-Latch (see Figure 5). The primary current is sensed by the external series resistor RSense inserted in the source of the integrated CoolMOS(R). By means of Current Mode regulation, the secondary output voltage is insensitive to the line variations. The current waveform slope will change with the line variation, which controls the duty cycle. The external RSense allows an individual adjustment of the maximum source current of the integrated CoolMOS(R). To improve the Current Mode during light load conditions the amplified current ramp of the PWM-OP is superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (see Figure 6). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by VOSC. When the oscillator triggers the Gate Driver, T2 is opened so that the voltage ramp can start. In case of light load the amplified current ramp is too small to ensure a stable regulation. In that case the Voltage Ramp is a well defined signal for the comparison with the FB-signal. The duty cycle is then controlled by the slope of the Voltage Ramp. By means of the time delay circuit which is triggered by the inverted VOSC signal, the Gate Driver is switched-off until it reaches approximately 156ns delay time (see Figure 7). It allows the duty cycle to be reduced continuously till 0% by decreasing VFB below that threshold.
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Functional Description
3.3.1 PWM-OP
Soft-Start Comparator PWM Comparator FB Oscillator VOSC
time delay circuit (156ns)
C8 PWM-Latch
The input of the PWM-OP is applied over the internal leading edge blanking to the external sense resistor RSense connected to pin CS. RSense converts the source current into a sense voltage. The sense voltage is amplified with a gain of 3.3 by PWM OP. The output of the PWM-OP is connected to the voltage source V1. The voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the PWMComparator C8 and the Soft-Start-Comparator (see Figure 6).
Gate Driver
0.68V 10k T2 R1 V1
3.3.2
PWM-Comparator
X3.3 PWM OP
Voltage Ramp
Figure 6 Improved Current Mode
The PWM-Comparator compares the sensed current signal of the integrated CoolMOS(R) with the feedback signal VFB (see Figure 8). VFB is created by an external optocoupler or external transistor in combination with the internal pull-up resistor RFB and provides the load information of the feedback circuitry. When the amplified current signal of the integrated CoolMOS(R) exceeds the signal VFB the PWM-Comparator switches off the Gate Driver.
5V RFB Soft-Start Comparator PWM-Latch C8 PWM Comparator
VOSC
max. Duty Cycle
FB
Voltage Ramp
0.68V FB
t
0.68V
Optocoupler
PWM OP CS X3.3
Gate Driver
156ns time delay
t
Improved Current Mode
Figure 8
PWM Controlling
t
Figure 7 Light Load Conditions
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Functional Description 3.4 Startup Phase
S o ft S ta rt c o u n te r
When the VVCC exceeds the on-threshold voltage, the IC starts the Soft Start mode (see Figure 10). The function is realized by an internal Soft Start resistor, an current sink and a counter. And the amplitude of the current sink is controlled by the counter (see Figure 11).
Soft Start finish
S o ftS
S o ft S ta rt
5V
S o ft S ta rt S o ft-S ta rt C o m p a ra to r C7 & G7 G a te D riv e r
R SoftS SoftS
0 .6 8 V x 3 .3 PW M OP CS
Soft Start 32I Counter
8I
4I
2I
I
Figure 9
Soft Start Figure 11 Soft Start Circuit After the IC is switched on, the VSOFTS voltage is controlled such that the voltage is increased stepwisely (32 steps) with the increase of the counts. The Soft Start counter would send a signal to the current sink control in every 600us such that the current sink decrease gradually and the duty ratio of the gate drive increases gradually. The Soft Start will be finished in 20ms (tSoft-Start) after the IC is switched on. At the end of the Soft Start period, the current sink is switched off.
In the Startup Phase, the IC provides a Soft Start period to control the primary current by means of a duty cycle limitation. The Soft Start function is a built-in function and it is controlled by an internal counter. .
VSoftS
VSOFTS32
tSoft-Start
V SoftS
VSoftS2 VSoftS1
Gate Driver
t
Figure 10
Soft Start Phase Figure 12
t
Gate drive signal under Soft-Start Phase
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Functional Description
Within the soft start period, the duty cycle is increasing from zero to maximum gradually (see Figure 12). In addition to Start-Up, Soft-Start is also activated at each restart attempt during Auto Restart.
3.5
PWM Section
0.75 Oscillator PWM Section
VSoftS tSoft-Start VSOFTS32
Duty Cycle max Clock Frequency Jitter
VFB 4.5V
t
Soft Start Block Soft Start Comparator 1 G8 S R Q
FF1 Gate Driver & G9
VOUT VOUT tStart-Up
t
PWM Comparator Current Limiting
CoolMOS(R) Gate
t
Figure 13 Start Up Phase
Figure 14
PWM Section Block
The Start-Up time tStart-Up before the converter output voltage VOUT is settled, must be shorter than the SoftStart Phase tSoft-Start (see Figure 13). By means of Soft-Start there is an effective minimization of current and voltage stresses on the integrated CoolMOS(R), the clamp circuit and the output overshoot and it helps to prevent saturation of the transformer during Start-Up.
3.5.1 Oscillator The oscillator generates a fixed frequency of 67KHz with frequency jittering of 4% (which is 2.7KHz) at a jittering period of 4ms. A capacitor, a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.75. Once the Soft Start period is over and when the IC goes into normal operating mode, the switching frequency of the clock is varied by the control signal from the Soft Start block. Then the switching frequency is varied in range of 67KHz 2.7KHz at period of 4ms. 3.5.2 PWM-Latch FF1 The output of the oscillator block provides continuous pulse to the PWM-Latch which turns on/off the internal CoolMOS(R). After the PWM-Latch is set, it is reset by the PWM comparator, the Soft Start comparator or the Current -Limit comparator. When it is in reset mode, the output of the driver is shut down immediately.
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Functional Description
3.5.3 Gate Driver
3.6
PWM Latch FF1
Current Limiting
VCC
Current Limiting
PWM-Latch 1
Gate CoolMOS(R)
Propagation-Delay Compensation Vcsth C10 PWM-OP
Gate Driver
Leading Edge Blanking 220ns
&
Figure 15
Gate Driver
G10
C12 0.26V
The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the internal CoolMOS(R) threshold. This is achieved by a slope control of the rising edge at the driver's output (see Figure 9).
Active Burst Mode
10k D1
1pF
CS
(internal) VGate
Figure 17
Current Limiting Block
ca. t = 130ns 5V
t
Figure 16 Gate Rising Slope Thus the leading switch on spike is minimized. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During power up, when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver is set to low in order to disable power transfer to the secondary side.
There is a cycle by cycle peak current limiting operation realized by the Current-Limit comparator C10. The source current of the integrated CoolMOS(R) is sensed via an external sense resistor RSense. By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth, the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down of the integrated CoolMOS(R) with very short propagation delay. Thus the influence of the AC input voltage on the maximum output power can be reduced to minimal. In order to prevent the current limit from distortions caused by leading edge spikes, a Leading Edge Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. When it is activated, the current limiting is reduced to 0.26V. This voltage level determines the maximum power level in Active Burst Mode.
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Functional Description
3.6.1 Leading Edge Blanking
For example, Ipeak = 0.5A with RSense = 2. The current sense threshold is set to a static voltage level Vcsth=1V without Propagation Delay Compensation. A current ramp of dI/dt = 0.4A/s, or dVSense/dt = 0.8V/s, and a propagation delay time of tPropagation Delay =180ns leads to an Ipeak overshoot of 14.4%. With the propagation delay compensation, the overshoot is only around 2% (see Figure 20).
with compensation without compensation
VSense
Vcsth tLEB = 220ns
V
1,3
t
VSense
Figure 18 Leading Edge Blanking Whenever the internal CoolMOS(R) is switched on, a leading edge spike is generated due to the primaryside capacitances and reverse recovery time of the secondary-side rectifier. This spike can cause the gate drive to switch off unintentionally. In order to avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of tLEB = 220ns.
1,25 1,2 1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
V
dVSense dt
s
3.6.2
Propagation Delay Compensation
Figure 20
Overcurrent Shutdown
In case of overcurrent detection, there is always propagation delay to switch off the internal CoolMOS(R). An overshoot of the peak current Ipeak is induced to the delay, which depends on the ratio of dI/dt of the peak current (see Figure 19).
The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (see Figure 21). In case of a steeper slope the switch off of the driver is earlier to compensate the delay.
VOSC
Signal2 ISense Ipeak2 Ipeak1 ILimit IOvershoot2 Signal1 tPropagation Delay
max. Duty Cycle
off time
VSense
IOvershoot1
Propagation Delay
t
Vcsth
t
Figure 19 Current Limiting The overshoot of Signal2 is larger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense threshold Vcsth and the switching off of the integrated CoolMOS(R) is compensated over temperature within a wide range. Current Limiting is then very accurate.
Signal1
Figure 21
Signal2
t
Dynamic Voltage Threshold Vcsth
3.7
Control Unit
The Control Unit contains the functions for Active Burst Mode and Auto Restart Mode. The Active Burst Mode and the Auto Restart Mode both have 20ms internal Blanking Time. For the Auto Restart Mode, a further extendable Blanking Time is achieved by adding
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Functional Description
external capacitor at BA pin. By means of this Blanking Time, the IC avoids entering into these two modes accidentally. Furthermore those buffer time for the overload detection is very useful for the application that works in low current but requires a short duration of high current occasionally. In order to make the startup properly, the maximum CBK capacitor is restricted to less than 0.65uF. The Active Burst Mode has basic blanking mode only while the Auto Restart Mode has both the basic and the extendable blanking mode.
3.7.1
Basic and Extendable Blanking Mode
BA # CBK
IBK
5.0V
0.9V 1 S1 G2
3.7.2 Active Burst Mode The IC enters Active Burst Mode under low load conditions. With the Active Burst Mode, the efficiency increases significantly at light load conditions while still maintaining a low ripple on VOUT and a fast response on load jumps. During Active Burst Mode, the IC is controlled by the FB signal. Since the IC is always active, it can be a very fast response to the quick change at the FB signal. The Start up Cell is kept OFF in order to minimize the power loss.
C3 4.0V
Internal Bias
Spike Blanking 30us &
20 ms Blanking Time
Auto Restart Mode
4.5V C4
20ms Blanking Time
G5
Current Limiting & G10
4.5V C4
FB
C5 1.22V
20ms Blanking Time
& G6
Active Burst Mode Control Unit
FB
C5 1.22V & G6
Active Burst Mode
C6a
Figure 22
Basic and Extendable Blanking Mode
3.6V & C6b 3.1V Control Unit G11
There are 2 kinds of Blanking mode; basic mode and the extendable mode. The basic mode is just an internal pre-set 20ms blanking time while the extendable mode has extra blanking time by connecting an external capacitor to the BA pin in addition to the pre-set 20ms blanking time. For the extendable mode, the gate G5 is blocked even though the 20ms blanking time is reached if an external capacitor CBK is added to BA pin. While the 20ms blanking time is passed, the switch S1 is opened by G2. Then the 0.9V clamped voltage at BA pin is charged to 4.0V through the internal IBK constant current. Then G5 is enabled by comparator C3. After the 30us spike blanking time, the Auto Restart Mode is activated. For example, if CBK = 0.22uF, IBK = 13.5uA Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 70ms
Figure 23
Active Burst Mode
The Active Burst Mode is located in the Control Unit. Figure 23 shows the related components.
3.7.2.1 Entering Active Burst Mode The FB signal is kept monitoring by the comparator C5. During normal operation, the internal blanking time counter is reset to 0. When FB signal falls below 1.22V, it starts to count. When the counter reach 20ms and FB signal is still below 1.22V, the system enters the Active Burst Mode. This time window prevents a sudden entering into the Active Burst Mode due to large load jumps.
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Functional Description
After entering Active Burst Mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC to approx. 500uA. It needs the application to enforce the VCC voltage above the Undervoltage Lockout level of 10.5V such that the Startup Cell will not be switched on accidentally. Or otherwise the power loss will increase drastically. The minimum VCC level during Active Burst Mode depends on the load condition and the application. The lowest VCC level is reached at no load condition.
VFB
4.5V 3.6V 3.1V 1.22V Blanking Timer
Entering Active Burst Mode
Leaving Active Burst Mode
t
3.7.2.2 Working in Active Burst Mode After entering the Active Burst Mode, the FB voltage rises as VOUT starts to decrease, which is due to the inactive PWM section. The comparator C6a monitors the FB signal. If the voltage level is larger than 3.6V, the internal circuit will be activated; the Internal Bias circuit resumes and starts to provide switching pulse. In Active Burst Mode the gate G10 is released and the current limit is reduced to 0.26V. In one hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. If the load at VOUT is still kept unchanged, the FB signal will drop to 3.1V. At this level the C6b deactivates the internal circuit again by switching off the internal Bias. The gate G11 is active again as the burst flag is set after entering Active Burst Mode. In Active Burst Mode, the FB voltage is changing like a saw tooth between 3.1V and 3.6V (see figure 17). 3.7.2.3 Leaving Active Burst Mode The FB voltage will increase immediately if there is a high load jump. This is observed by the comparator C4. As the current limit is appr. 26% during Active Burst Mode, a certain load jump is needed so that the FB signal can exceed 4.5V. At that time the comparator C4 resets the Active Burst Mode control which in turn blocks the comparator C12 by the gate G10. The maximum current can then be resumed to stabilize VOUT.
20ms Blanking Time
VCS
Current limit level during Active Burst Mode
t
1.0V 0.26V
VVCC
t
10.0V
IVCC
2.4mA
t
500uA
VOUT
Max. Ripple < 1%
t
t
Figure 24
Signals in Active Burst Mode
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Functional Description
3.7.3 Protection Modes The IC provides Auto Restart Mode as the protection feature. Auto Restart mode can prevent the SMPS from destructive states. The following table shows the relationship between possible system failures and the chosen protection modes.
VCC Overvoltage Overtemperature Overload Open Loop VCC Undervoltage Short Optocoupler External auto restart enable Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode
4.0V C3 Spike Blanking 30us & S1 0.9V 1 G2
3.7.3.1
Auto Restart mode blanking time
BA
with
extended
5.0V IBK
#
CBK
Before entering the Auto Restart protection mode, some of the protections can have extended blanking time to delay the protection and some needs to fast react and will go straight to the protection. Overload and open loop protection are the one can have extended blanking time while Vcc Overvoltage, Over temperature, Vcc Undervoltage, short opto-coupler and external auto restart enable will go to protection right away. After the system enters the Auto-restart mode, the IC will be off. Since there is no more switching, the Vcc voltage will drop. When it hits the Vcc turn off threshold, the start up cell will turn on and the Vcc is charged by the startup cell current to Vcc turn on threshold. The IC is on and the startup cell will turn off. At this stage, it will enter the startup phase (soft start) with switching cycles. After the Start Up Phase, the fault condition is checked. If the fault condition persists, the IC will go to auto restart mode again. If, otherwise, the fault is removed, normal operation is resumed.
4.5V
FB
C4
20ms Blanking Time
G5
Auto Restart Mode Control Unit
Figure 25
Auto Restart Mode
In case of Overload or Open Loop, the FB exceeds 4.5V which will be observed by comparator C4. Then the internal blanking counter starts to count. When it reaches 20ms, the switch S1 is released. Then the clamped voltage 0.9V at VBA can increase. When there is no external capacitor CBK connected, the VBA will reach 4.0V immediately. When both the input signals at AND gate G5 is positive, the Auto Restart Mode will be activated after the extra spike blanking time of 30us is elapsed. However, when an extra blanking time is needed, it can be achieved by adding an external capacitor, CBK. A constant current source of IBK will start to charge the capacitor CBK from 0.9V to 4.0V after the switch S1 is released. The charging time from 0.9V to 4.0V are the extendable blanking time. If CBK is 0.22uF and IBK is 13.5uA, the extendable blanking time is around 50ms and the total blanking time is 70ms. In combining the FB and blanking time, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps.
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Functional Description
3.7.3.2 Auto Restart without extended blanking time
a trigger signal to the base of the externally added transistor, TAE at the BA pin. When the function is enabled, the gate drive switching will be stopped and then the IC will enter auto-restart mode if the signal persists. To ensure this auto-restart function will not be mis-triggered during start up, a 1ms delay time is implemented to blank the unstable signal. VCC undervoltage is the Vcc voltage drop below Vcc turn off threshold. Then the IC will turn off and the start up cell will turn on automatically. And this leads to Auto Restart Mode. Short Optocoupler also leads to VCC undervoltage. When the FB pin is pulled low, there is no switching pulse. Then the Vcc will drop to Vcc turn off threshold. And it leads to Auto Restart Mode.
1m s counter
Auto-restart Enable Signal
Auto Restart M Reset ode VVCC < 10.5V UVLO Stop gate drive
BA
0.33V C9 25.5V VCC C2 120us Blanking Time Auto Restart m ode
TAE
VCC 20.7V softs_period 4.5V C4 C1
& G1
Spike Blanking 30us
FB
Therm Shutdown al Tj >130C Control Unit
Voltage Reference
Figure 26
Auto Restart mode
There are 2 modes of VCC overvoltage protection; one is during soft start and the other is at all conditions. The first one is VVCC voltage is > 20.7V and FB is > 4.5V and during soft_start period and the IC enters Auto Restart Mode. The VCC voltage is observed by comparator C1. The fault conditions are to detect the abnormal operating during start up such as open loop during light load start up, etc. The logic can eliminate the possible of entering Auto Restart mode if there is a small voltage overshoots of VVCC during normal operating. The 2nd one is VVCC >25.5V and last for 120us and the IC enters Auto Restart Mode. This 25.5V Vcc OVP protection is inactivated during burst mode. The Thermal Shutdown block monitors the junction temperature of the IC. After detecting a junction temperature higher than 130C, the Auto Restart Mode is entered. In case the pre-defined auto-restart features are not sufficient, there is a customer defined external Autorestart Enable feature. This function can be triggered by pulling down the BA pin to < 0.33V. It can simply add
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Electrical Characteristics
4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 5). The voltage levels are valid if other ratings are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 4 (VCC) is discharged before assembling the application circuit.Ta=25C unless otherwise specified.
Parameter
Switching drain current, pulse width tp limited by max. Tj=150C Pulse drain current, pulse width tp limited by max. Tj=150C
Symbol
Is -
Limit Values min. max.
2.68
Unit
A
Remarks
ID_Puls
-0.3 -0.3 -0.3 -0.3 -40 -55 -
5.3 0.07 1.8 27 5.5 5.5 5.5 150 150 82 5.2 260 24 2 60
A mJ A V V V V C C K/W K/W C W kV Ncm 1.6mm (0.063 in.) from case for 10s Refer to Figure 57 Human body model2) M2.5 screws Controller & CoolMOS(R) ID=1.8A
Avalanche energy, repetitive tAR limited EAR by max. Tj=150C1) Avalanche current, repetitive tAR limited IAR by max. Tj=150C1) VCC Supply Voltage FB Voltage BA Voltage CS Voltage Junction Temperature Storage Temperature Thermal Resistance Junction -Ambient Thermal Resistance Junction -case Soldering temperature, wavesoldering only allowed at leads Power dissipation, Tc=25C ESD Capability (incl. Drain Pin) Mounting torque
1) 2)
VVCC VFB VBA VCS Tj TS RthJA RthJC Tsold Ptot VESD
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
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Electrical Characteristics 4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
VCC Supply Voltage Junction Temperature of Controller Junction Temperature of CoolMOS(R)
Symbol
VVCC TjCon TjCoolMOS
Limit Values min.
VVCCoff -25 -25
Unit
V C C
Remarks
Max. value limited due to Vcc OVP Max value limited due to thermal shut down of controller
max.
25 130 150
4.3
4.3.1 Note:
Characteristics
Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 25 C to 125 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed. Symbol min.
IVCCstart IVCCcharge1 IVCCcharge2 IVCCcharge3 0.55 -
Parameter
Start Up Current VCC Charge Current
Limit Values typ.
150 0.9 0.7 0.2
Unit
A mA mA mA A
Test Condition
VVCC =17V VVCC = 0V VVCC = 1V VVCC =17V VDrain = 600V at Tj=100C 1)
max.
250 5.0 1.60 50
Leakage Current of Start Up Cell and CoolMOS(R) Supply Current with Inactive Gate Supply Current with Active Gate Supply Current in Auto Restart Mode with Inactive Gate Supply Current in Active Burst Mode with Inactive Gate VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis
1)
IStartLeak
IVCCsup1 IVCCsup2 IVCCrestart
-
1.5 2.4 250
2.5 3.7 -
mA mA A IFB = 0A IFB = 0A
IVCCburst1 IVCCburst2 VVCCon VVCCoff VVCChys
17.0 9.8 -
500 500 18.0 10.5 7.5
950 950 19.0 11.2 -
A A V V V
VFB = 2.5V VVCC = 11.5V,VFB = 2.5V
The parameter is not subjected to production test - verified by design/characterization
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Electrical Characteristics
4.3.2 Internal Voltage Reference Symbol min.
Trimmed Reference Voltage VREF 4.90
Parameter
Limit Values typ.
5.00
Unit
V
Test Condition
measured at pin FB IFB = 0
max.
5.10
4.3.3 Parameter
PWM Section Symbol min.
fOSC1 fOSC2 fjitter Tjitter Dmax Dmin AV VOffset-Ramp 58 62 0.70 0 3.1 9
Limit Values typ.
67 67 2.7 4.0 0.75 3.3 0.68 0.5 15.4
Unit
kHz kHz kHz ms
Test Condition
max.
75 74.5 0.80 3.5 4.3 22 V V V k CS=1V, limited by Comparator C41) VFB < 0.3V Tj = 25C Tj = 25C Tj = 25C
Fixed Oscillator Frequency Frequency Jittering Range Frequency Jittering period Max. Duty Cycle Min. Duty Cycle PWM-OP Gain Voltage Ramp Offset
VFB Operating Range Min Level VFBmin VFB Operating Range Max level FB Pull-Up Resistor
1)
VFBmax RFB
The parameter is not subjected to production test - verified by design/characterization
4.3.4
Soft Start time Symbol min.
tSS -
Parameter
Soft Start time
Limit Values typ.
20.0
Unit
ms
Test Condition
VFB > 4.0V
max.
-
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Electrical Characteristics
4.3.5 Parameter
Clamped VBA voltage during Normal Operating Mode Blanking time voltage limit for Comparator C3 Over Load & Open Loop Detection Limit for Comparator C4 Active Burst Mode Level for Comparator C5 Active Burst Mode Level for Comparator C6a Active Burst Mode Level for Comparator C6b Overvoltage Detection Limit for Comparator C1 Overvoltage Detection Limit for Comparator C2 Auto-restart Enable level at BA pin for Comparator C9 Charging current at BA pin
Control Unit Symbol min.
VBAclmp VBKC3 VFBC4 VFBC5 VFBC6a VFBC6b VVCCOVP1 0.85 3.85 4.28 1.13 3.45 2.97 19.6
Limit Values typ.
0.9 4.00 4.50 1.22 3.60 3.10 20.7
Unit
V V V V V V V
Test Condition
VFB = 4V
max.
0.95 4.15 4.72 1.31 3.74 3.22 21.7
After Active Burst Mode is entered After Active Burst Mode is entered VFB = 5V
VVCCOVP2
25.0
25.5
26.3
V
VAE
0.25
0.33
0.42
V
IBK
10.1
13.5
16.1
A
Charge starts after the built-in 20ms blanking time elapsed Controller without external capacitor at BA pin Count when VCC>18V
Thermal Shutdown1) Built-in Blanking Time for Overload Protection or enter Active Burst Mode Inhibit Time for Auto-Restart enable function during start up Spike Blanking Time before Auto Restart Protection
1)
TjSD tBK
130 -
140 20
150 -
C ms
tIHAE tSpike
-
1.0 30
-
ms s
The parameter is not subjected to production test - verified by design/characterization The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP and VVCCPD
Note:
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Electrical Characteristics
4.3.6 Parameter
Peak Current Limitation (incl. Propagation Delay) Peak Current Limitation during Active Burst Mode Leading Edge Blanking CS Input Bias Current
Current Limiting Symbol min.
Vcsth VCS2 tLEB ICSbias 0.88 0.22 -1.5
Limit Values typ.
1.06 0.26 220 -0.2
Unit
V V ns A
Test Condition
dVsense / dt = 0.6V/s (see Figure 13)
max.
1.13 0.29 -
VCS =0V
4.3.7
CoolMOS(R) Section
Symbol min.
V(BR)DSS 650
Parameter
Drain Source Breakdown Voltage
Limit Values typ.
-
Unit
V
Test Condition
Tj = 110C1) (Refer to Figure 65 for other V(BR)DSS in different Tj) VGS=0V, ID=0.25mA VGS=0V, ID=1.8A Tj = 25C Tj=125C1) Tj=150C1) at ID = 1A VDS = 0V to 480V1)
max.
-
Drain Source Avalanche Breakdown Voltage Drain Source On-Resistance
V(BR)DS RDSon
-
700 2.56 5.67 6.91 11 302) 30
2)
2.83 6.26 7.64 -
V pF ns ns
Effective output capacitance, energy related Rise Time Fall Time
1) 2)
Co(er) trise tfall
The parameter is not subjected to production test - verified by design/characterization Measured in a Typical Flyback Converter Application
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Typical Controller Performance Characteristics
5
200 192
Typical Controller Performance Characteristics
0.85
Vcc Charge Current IVCCcharge3 [mA]
0.81 0.77 0.73 0.69 0.65 0.61 0.57 0.53 0.49 0.45 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-004-8889A23
Start Up Current I VCCstart [A]
184 176 168 160 152 144 136 128 120 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-001-8889A23
Junction Temperature [C]
Junction Temperature [C]
Figure 27
1.00
Start Up Current IVCCstart
Figure 30
1.80
VCC Charge Current IVCCcharge3
Vcc Charge Current IVCCcharge1 [mA]
0.92 0.88 0.84
PI-002-8889A23
Vcc Supply Current IVCCsup1 [mA]
0.96
1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-005-8889A23
0.80 0.76 0.72 0.68 0.64 0.60 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 28
1.00
VCC Charge Current IVCCcharge1
Figure 31
2.9
VCC Supply Current IVCCsup1
Vcc Charge Current I VCCcharge2 [mA]
0.92 0.88 0.84 0.80 0.76 0.72 0.68 0.64 0.60 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-003-8889A23
Vcc Supply Current IVCCsup2 [mA]
0.96
2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-006-8888A12 ICE3BR2565JF
Junction Temperature [C]
Junction Temperature [C]
Figure 29
VCC Charge Current IVCCcharge2
Figure 32
VCC Supply Current IVCCsup2
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Typical Controller Performance Characteristics
310 300 290 280 270
PI-007-8889A23
11.0
Vcc Turn-Off Threshold VVCCoff [V]
Vcc Supply Current IVCCrestart [uA]
10.9 10.8 10.7 10.6 10.5 10.4 10.3 10.2 10.1 10.0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-010-8889A23
260 250 240 230 220 210 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 33
600
VCC Supply Current IVCCrestart
Figure 36
5.20 5.16
VCC Turn-Off Threshold VVCCoff
Vcc Supply Current IVCCburst [uA]
580
Reference Voltage VREF [V]
560 540 520
PI-008-8889A23
5.12 5.08 5.04 5.00 4.96 4.92 4.88 4.84 4.80 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-011-8889A23
500 480 460 440 420 400 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 34
VCC Supply Current IVCCburst
Figure 37
70
Reference Voltage VREF
18.5
Vcc Turn-On threshold VVCCon [V]
18.4 18.3 18.2 18.1 18.0 17.9 17.8 17.7 17.6 17.5 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-010-8889A23
Oscillator Frequency fosc1 [kHz]
69 68 67 66 65 64 63 62 61 60 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-012-8889A23
Junction Temperature [C]
Junction Temperature [C]
Figure 35
VCC Turn-On Threshold VVCCon
Figure 38
Oscillator Frequency fOSC1
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Typical Controller Performance Characteristics
3.1
Frequency Jitter Range fjitter [+/-kHz]
0.73
3.0 2.9 2.8 2.7
PI-001-8889A23
Voltage Ramp Offset V Offset-Ramp [V]
0.72 0.71 0.70 0.69 0.68 0.67 0.66 0.65 0.64 0.63 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-016-8889A23
2.6 2.5 2.4 2.3 2.2 2.1 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 39
0.780 0.774 0.768
Frequency Jittering Range fjitter
Figure 42
Feedback Pull-Up resistor RFB [kOhm]
20 19 18 17 16 15 14 13 12 11 10 -25 -15
Voltage Ramp Offset VOffset-Ramp
Max. Duty Cycle Dmax
0.762 0.756 0.750 0.744 0.738 0.732 0.726 0.720 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-014-8889A23
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 40
3.50
Max. Duty Cycle Dmax
Figure 43
0.95
Feedback Pull-Up resistor RFB
Clamped VBA Voltage VBAclmp [V]
0.94 0.93 0.92 0.91 0.90 0.89 0.88 0.87 0.86 0.85 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-020-8889A23
3.45 3.40
PWM OP Gain AV
3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.00 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-015-8889A23
Junction Temperature [C]
Junction Temperature [C]
Figure 41
PWM-OP Gain AV
Figure 44
Clamped VBA voltage VBAclmp
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PI-019-8889A23
CoolSET(R)-F3R ICE3BR2565JF
Typical Controller Performance Characteristics
3.70
4.10
Blanking time voltage limit VBKC3 [V]
Active Burst Model Leve VFBC6a [V]
4.08 4.06 4.04 4.02
PI-021-8889A23
3.68 3.66 3.64 3.62 3.60 3.58 3.56 3.54 3.52 3.50 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-024-8889A23
4.00 3.98 3.96 3.94 3.92 3.90 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 45
4.70
Blanking time voltage limit VBKC3
Figure 48
3.30
Active Burst Mode Level VFBC6a
Active Burst Mode Level VFBC6b [V]
Over Load detection limit VFBC4 [V]
3.25 3.20 3.15 3.10 3.05 3.00 2.95 2.90 2.85 2.80 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-025-8889A23
4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 -25 -15
PI-022-8889A23
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 46
1.40
Over Load Detection Limit VFBC4
Figure 49
Active Burst Mode Level VFBC6b
1.36 1.32 1.28 1.24
PI-023-8889A23
Overvoltage Detection Limit VVCCovp1 [V]
21.0 20.9 20.8 20.7 20.6 20.5 20.4 20.3 20.2 20.1 20.0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-026-8889A23
Active Burst mode Level VFBC5 [V]
1.20 1.16 1.12 1.08 1.04 1.00 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 47
Active Burst Mode Level VFBC5
Figure 50
Overvoltage Detection Limit VVCCOVP1
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CoolSET(R)-F3R ICE3BR2565JF
Typical Controller Performance Characteristics
Overvoltage Detection Level VVCCOVP2 [V]
26.0 25.9 25.8 25.7 25.6
PI-027-8889A23
1.20
Peak Current Limitation VCSth [V]
1.16 1.12 1.08 1.04 1.00 0.96 0.92 0.88 0.84 0.80 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-031-8889A23
25.5 25.4 25.3 25.2 25.1 25.0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 51
0.38
Over Load Detection Limit VVCCOVP2
Figure 54
0.30
Peak Current Limitation Vcsth
Auto-restart Enable Level V AE [V]
0.37 0.36 0.35 0.34 0.33 0.32 0.31 0.30 0.29 0.28 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-028-8889A23
Peak Current Limitation VCS2 [V]
0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-032-8889A23
Junction Temperature [C]
Junction Temperature [C]
Figure 52
15.0
Auto-restart Enable Level VAE
Figure 55
290
Peak Current Limitation VCS2
Charging Current at BA pin IBK [A]
14.5 14.0 13.5 13.0
PI-029-8889A23
Leading Edge Blanking tLEB [ns]
280 270 260 250 240 230 220 210 200 190 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
PI-033-8889A23
12.5 12.0 11.5 11.0 10.5 10.0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 53
Charging Current at BA pin IBK
Figure 56
Leading Edge Blanking tLEB
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CoolSET(R)-F3R ICE3BR2565JF
Typical CoolMOS(R) Performance Characteristics
6
30 25 20
P tot [W]
Typical CoolMOS(R) Performance Characteristics
5 4 3 2 1 0
0 40 80 T C [C] 120 160
Vcc > 10.5V
15 10 5 0
ID [A]
0
5
10 VDS [V]
15
20
Figure 57
Power dissipation; Ptot=f(TC)
Figure 60
Typ. output characteristics; ID=f(VDS),Tj=25C, parameter : VCC
Ugs 8 V, T 150 C
10
1
limited by on-state resistance
2.5
Vcc>10.5V
2
1 s
I D [A]
10
0
100 s 1 ms 10 ms DC
I D [A]
10 s
1.5 1 0.5 0
10
-1
10
0
10
1
V DS [V]
10
2
10
3
0
5
10 V DS [V]
15
20
Figure 58
Safe operation area; ID=f(VDS), parameter : D=0, TC=25C
Figure 61
Typ. output characteristics; ID=f(VDS),Tj=150C, parameter : VCC
101
15 14
0.5
13 12
R DS(on) [ ]
vcc > 10.5 V
ZthJC [K/W]
0.2
11 10 9 8 7 6 5 0 1 2 I D [A] 3 4
10
0
0.1 0.05 0.02 0.01 single pulse
10
-1
10
-5
10
-4
10
-3
tp [s]
10
-2
10
-1
10
0
10
1
Figure 59
Transient thermal impedance; ZthJC=f(tp),parameter: D=tp/T
Figure 62
Typ. drain-source on-state resistance; RDS(on)=f(ID); Tj=150C, parameter : VCC
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CoolSET(R)-F3R ICE3BR2565JF
Typical CoolMOS(R) Performance Characteristics
8 7
Ciss
103
6
R DS(on) [ ]
4 3 2 1 -60 -20
98 %
C [pF]
5
10
2
Coss
1
typ
10
Crss
20
60 T j [C]
100
140
180
10
0
0
100
200
V DS [V]
300
400
500
Figure 63
Drain-source on-state resistance; RDS(on)=f(Tj); ID=1A;, Vcc>10.5V
Figure 66
Typ. capacitances; C=f(VDS),VGS=0V,f=1MHz
50
2
40
1.6
E AS [mJ]
30
Eoss [F]
1.2
20
0.8
10
0.4
0 20 60 100 T j [C] 140 180
0 0 100 200 300 VDS [V] 400 500 600
Figure 64
Avalanche energy; EAS=f(Tj),ID=0.7A,VDD=50V
Figure 67
Typ. Coss stored energy; Eoss=f(VDS)
700
660
V BR(DSS) [V]
620
580
540 -60 -20 20 60 T j [C] 100 140 180
Figure 65
Drain-source breakdown voltage; VBR(DSS)=f(Tj), ID=0.25mA
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CoolSET(R)-F3R ICE3BR2565JF
Input Power Curve
7
Input Power Curve
Two input power curves giving the typical input power versus ambient temperature are showed below; Vin=85Vac~265Vac (Figure 68) and Vin=230Vac+/-15% (Figure 69). The curves are derived based on a typical discontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum secondary to primary reflected voltage (higher priority). The calculation is based on RthSA=2.7K/W as heatsink and RthCS=1.1K/W as thermal grease thermal resistance. The input power already includes the power loss at input common mode choke, bridge rectifier and the CoolMOS. The device saturation current (ID_Puls @ Tj=125C) is also considered. To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 68), operating temperature is 50C, estimated efficiency is 80%, then the estimated output power is 64.8W (81W * 80%).
90 80
Input power (85~265Vac) [W]
70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130
PI-005-ICE3BR2565JF_85Vac
Ambient Temperature [C]
Figure 68 Input power curve Vin=85~265Vac; Pin=f(Ta)
110 100
Input power (230Vac) [W]
90 80
PI-006-ICE3BR2565JF_230Vac
70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Ambient Temperature [C]
Figure 69 Input power curve Vin=230Vac+/-15%; Pin=f(Ta)
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CoolSET(R)-F3R ICE3BR2565JF
Outline Dimension
8
Outline Dimension
PG-TO220-6-247 (PB-free Plating FullPak Package Outline)
Figure 70
PG-TO220-6-247 (PB-free Plating FullPak Package) Dimensions in mm
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CoolSET(R)-F3R ICE3BR2565JF
Marking
9
Marking
Marking
Figure 71
Marking for ICE3BR2565JF
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CoolSET(R)-F3R ICE3BR2565JF
Schematic for recommended PCB layout
10
Schematic for recommended PCB layout
TR1
BR1 Spark Gap 3 FUSE1
R11 C11 bulk cap D11
C12
D21
L
Spark Gap 1
X-CAP C1 L1
Vo
C21
GND
Spark Gap 2 Spark Gap 4 C2 Y-CAP C3 Y-CAP C4 Y-CAP BA GND C13 R12 CS D11 Z11
GND
C16 R21
N
IC11
DRAIN R13 R14 D13
F3 CoolSET VCC
FB C15 C14 NC
R23
R22 C22
*
C23
R24
IC12
IC21 R25
F3 CoolSET schematic for recommended PCB layout
Figure 72
Schematic for recommended PCB layout
General guideline for PCB layout design using F3/F3R CoolSET (refer to Figure 72): 1. "Star Ground "at bulk capacitor ground, C11: "Star Ground "means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device effectively. The primary DC grounds include the followings. a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11. b. DC ground of the current sense resistor, R12 c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of IC12 should be connected to the GND pin of IC11 and then "star "connect to the bulk capacitor ground. d. DC ground from bridge rectifier, BR1 e. DC ground from the bridging Y-capacitor, C4 2. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur. a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm 3. Filter capacitor close to the controller ground: Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 72): 1. Add spark gap Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1: Gap separation is around 1.5mm (no safety concern)
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CoolSET(R)-F3R ICE3BR2565JF
Schematic for recommended PCB layout
b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12: The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148. The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller, IC11.
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Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
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