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25AA512
512 Kbit SPI Bus Serial EEPROM
Device Selection Table
Part Number 25AA512 VCC Range 1.8-5.5V Page Size 128 Byte Temp. Ranges I Packages P, SN, SM, MF
Features:
* 20 MHz max. Clock Speed * Byte and Page-level Write Operations: - 128-byte page - 5 ms max. - No page or sector erase required * Low-Power CMOS Technology: - Max. Write Current: 5 mA at 5.5V, 20 MHz - Read Current: 10 mA at 5.5V, 20 MHz - Standby Current: 1A at 2.5V (Deep powerdown) * Electronic Signature for Device ID * Self-Timed Erase and Write cycles: - Page Erase (5 ms, typical) - Sector Erase (10 ms/sector, typical) - Bulk Erase (10 ms, typical) * Sector Write Protection (16K byte/sector): - Protect none, 1/4, 1/2 or all of array * Built-In Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin * High Reliability: - Endurance: 1 Million erase/write cycles - Data Retention: >200 years - ESD Protection: 4000V * Temperature Ranges Supported: - Industrial (I): -40C to +85C * Pb-free and RoHS Compliant
Description:
The Microchip Technology Inc. 25AA512 is a 512 Kbit serial EEPROM memory with byte-level and page-level serial EEPROM functions. It also features Page, Sector and Chip erase functions typically associated with Flash-based products. These functions are not required for byte or page write operations. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled by a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25AA512 is available in standard packages including 8-lead PDIP, SOIC, and advanced 8-lead DFN package. All packages are Pb-free and RoHS compliant.
Package Types (not to scale)
DFN
25AA512
CS 1 SO 2 WP 3 VSS 4
(MF)
8 7 6 5 VCC HOLD SCK SI
PDIP/SOIC/SOIJ
(P, SN, SM) 25AA512
8 7 6 5 CS SO WP VSS 1 2 3 4 VCC HOLD SCK SI
Pin Function Table
Name CS SO WP VSS SI SCK HOLD VCC Function Chip Select Input Serial Data Output Write-Protect Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage
2010 Microchip Technology Inc.
DS22021F-page 1
25AA512
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings ()
VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................................................................-65C to 150C Ambient temperature under bias ...............................................................................................................-40C to 125C ESD protection on all pins ..........................................................................................................................................4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I)*: TA = 0C to +85C Industrial (I): TA = -40C to +85C *Limited industrial temp range. Min. .7 VCC -0.3 -0.3 -- -- VCC -0.2 -- -- -- Max. VCC +1 0.3 VCC 0.2 VCC 0.4 0.2 -- 1 1 7 Units V V V V V V A A pF VCC2.7V VCC < 2.7V IOL = 2.1 mA IOL = 1.0 mA, VCC < 2.5V IOH = -400 A CS = VCC, VIN = VSS TO VCC CS = VCC, VOUT = VSS TO VCC TA = 25C, CLK = 1.0 MHz, VCC = 5.0V (Note) VCC = 5.5V; FCLK = 20.0 MHz; SO = Open VCC = 2.5V; FCLK = 10.0 MHz; SO = Open VCC = 5.5V VCC = 2.5V CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85C CS = VCC = 2.5V, Inputs tied to VCC or VSS, 85C VCC = 1.8V to 5.5V VCC = 2.0V to 5.5V
DC CHARACTERISTICS Param. No. D001 D002 D003 D004 D005 D006 D007 D008 D009
Sym. VIH1 VIL1 VIL2 VOL VOL VOH ILI ILO CINT
Characteristic High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current Internal capacitance (all inputs and outputs)
Test Conditions
D010
ICC Read Operating current
-- --
10 5
mA mA mA mA A A
D011 D012 D13 Note:
ICC Write ICCS Standby current ICCSPD Deep power-down current
-- -- -- -- --
7 5 10 1
This parameter is periodically sampled and not 100% tested.
DS22021F-page 2
2010 Microchip Technology Inc.
25AA512
TABLE 1-2: AC CHARACTERISTICS
Industrial (I)*: TA = 0C to +85C Industrial (I): TA = -40C to +85C *Limited industrial temp range. Min. -- -- -- 25 50 250 50 100 500 Max. 20 10 2 -- -- -- -- -- -- Units MHz MHz MHz ns ns ns ns ns ns VCC = 1.8V to 5.5V VCC = 2.0V to 5.5V AC CHARACTERISTICS Param. No. 1
Sym. FCLK
Characteristic Clock frequency
Conditions 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C (Note 3) -- 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C (Note 1) (Note 1) 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C -- -- 4.5 VCC 5.5 2.8 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C (Note 1)
2
TCSS
CS setup time
3
TCSH
CS hold time
4 5
TCSD Tsu
CS disable time Data setup time
50 5 10 50 10 20 100 -- -- 25 50 250 25 50 250 50 50 -- -- -- 0
-- -- -- -- -- -- -- 20 20 -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6
THD
Data hold time
7 8 9
TR TF THI
CLK rise time CLK fall time Clock high time
10
TLO
Clock low time
11 12 13
TCLD TCLE TV
Clock delay time Clock enable time Output valid from clock low
-- -- 25 50 250 --
14
THO
Output hold time
Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from Microchip's web site at www.microchip.com. 3: Includes THI time.
2010 Microchip Technology Inc.
DS22021F-page 3
25AA512
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
Industrial (I)*: TA = 0C to +85C Industrial (I): TA = -40C to +85C *Limited industrial temp range. Min. -- -- -- Max. 25 50 250 Units ns ns ns VCC = 1.8V to 5.5V VCC = 2.0V to 5.5V AC CHARACTERISTICS Param. No. 15
Sym. TDIS
Characteristic Output disable time
Conditions 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C (Note 1) 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C (Note 1) 4.5 VCC 5.5 2.5 VCC 5.5 1.8 VCC <2.5 at 0C to +85C 2.0 VCC <2.5 at -40C to +85C VCC = 1.8V to 5.5V VCC = 1.8V to 5.5V VCC = 1.8V to 5.5V VCC = 1.8V to 5.5V Byte or Page mode and Page Erase
16
THS
HOLD setup time
10 20 100 10 20 100 15 30 150
-- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns
17
THH
HOLD hold time
18
THZ
HOLD low to output High-Z
19
THV
HOLD high to output valid
15 30 150 -- -- -- -- -- 1M
-- -- -- 100 100 10 10 5 --
ns ns ns s s ms ms ms
20 21 22 23 24 25
TREL TPD TCE TSE TWC --
CS High to Standby mode CS High to Deep powerdown Chip erase cycle time Sector erase cycle time Internal write cycle time Endurance
E/W Page mode, 25C, 5.5V (Note 2) Cycles
Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from Microchip's web site at www.microchip.com. 3: Includes THI time.
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25AA512
TABLE 1-3:
AC Waveform: VLO = 0.2V VHI = VCC - 0.2V VHI = 4.0V CL = 30 pF Timing Measurement Reference Level Input Output Note 1: For VCC 4.0V 2: For VCC > 4.0V 0.5 VCC 0.5 VCC -- (Note 1) (Note 2) --
AC TEST CONDITIONS
FIGURE 1-1:
CS
HOLD TIMING
16 SCK
17
16
17
16
17
16
17
SO
n+1
18 n
High-Impedance
19 n 5 n n-1 n-1
18
High-Impedance
19 n-2
Don't Care SI HOLD n+1 n
Don't Care n-2
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS 2 Mode 1,1 SCK Mode 0,0 5 SI 6 LSB in 7 8 3
12 11
MSB in
SO
High-Impedance
2010 Microchip Technology Inc.
DS22021F-page 5
25AA512
FIGURE 1-3: SERIAL OUTPUT TIMING
CS 9 SCK 13 SO MSB out Don't Care 14 15 LSB out 10 3 Mode 1,1 Mode 0,0
SI
DS22021F-page 6
2010 Microchip Technology Inc.
25AA512
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
BLOCK DIAGRAM
STATUS Register HV Generator
The 25AA512 is a 65,536 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular microcontroller families, including Microchip's PIC(R) microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 25AA512 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25AA512 in `HOLD' mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted.
I/O Control Logic
Memory Control Logic
X Dec
EEPROM Array
Page Latches
SI SO CS SCK HOLD WP VCC VSS
Y Decoder
Sense Amp. R/W Control
TABLE 2-1:
READ WRITE WREN WRDI RDSR WRSR PE SE CE RDID DPD
INSTRUCTION SET
Instruction Format 0000 0011 0000 0010 0000 0110 0000 0100 0000 0101 0000 0001 0100 0010 1101 1000 1100 0111 1010 1011 1011 1001 Description Read data from memory array beginning at selected address Write data to memory array beginning at selected address Set the write enable latch (enable write operations) Reset the write enable latch (disable write operations) Read STATUS register Write STATUS register Page Erase - erase one page in memory array Sector Erase - erase one sector in memory array Chip Erase - erase all sectors in memory array Release from Deep power-down and read electronic signature Deep Power-Down mode
Instruction Name
2010 Microchip Technology Inc.
DS22021F-page 7
25AA512
Read Sequence
The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25AA512 followed by the 16-bit address. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (FFFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The READ instruction is terminated by raising the CS pin (Figure 2-1).
FIGURE 2-1:
CS 0 SCK 1 2
READ SEQUENCE
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
Instruction SI 0 0 0 0 0 0 1
16-bit Address 1 15 14 13 12 2 1 0 Data Out 7 6 5 4 3 2 1 0
High-Impedance SO
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2010 Microchip Technology Inc.
25AA512
2.2 Write Sequence
Prior to any attempt to write data to the 25AA512, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25AA512. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. A write sequence includes an automatic, self timed erase cycle. It is not required to erase any portion of the memory prior to issuing a WRITE instruction. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, and then the data to be written. Up to 128 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Note: When doing a write of less than 128 bytes the data in the rest of the page is refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size'), and end at addresses that are integer multiples of page size - 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. Note:
FIGURE 2-2:
CS 0 SCK 1 2
BYTE WRITE SEQUENCE
Twc 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 Data Byte 2 1 0 7 6 5 4 3 2 1 0
Instruction SI 0 0 0 0 0 0 1
16-bit Address 0 15 14 13 12
High-Impedance SO
2010 Microchip Technology Inc.
DS22021F-page 9
25AA512
FIGURE 2-3:
CS 0 SCK Instruction SI 0 0 0 0 0 01 16-bit Address 0 15 14 13 12 2 1 0 7 6 Data Byte 1 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
PAGE WRITE SEQUENCE
CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 Data Byte 3 5 4 3 2 1 0 7 Data Byte n (128 max) 6 5 4 3 2 1 0
DS22021F-page 10
2010 Microchip Technology Inc.
25AA512
2.3 Write Enable (WREN) and Write Disable (WRDI)
* * * * * * * Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed PE instruction successfully executed SE instruction successfully executed CE instruction successfully executed
The 25AA512 contains a write enable latch. See Table 2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. The following is a list of conditions under which the write enable latch will be reset:
FIGURE 2-4:
WRITE ENABLE SEQUENCE (WREN)
CS 0 SCK 1 2 3 4 5 6 7
SI
0
0
0
0
0
1
1
0
SO
High-Impedance
FIGURE 2-5:
WRITE DISABLE SEQUENCE (WRDI)
CS 0 SCK 1 2 3 4 5 6 7
SI
0
0
0
0
0
1
0 1
0
High-Impedance SO
2010 Microchip Technology Inc.
DS22021F-page 11
25AA512
2.4 Read Status Register Instruction (RDSR)
The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a `1', the latch allows writes to the array, when set to a `0', the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 2-4 and Figure 2-5. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile, and are shown in Table 2-3. See Figure 2-6 for the RDSR timing sequence.
The Read Status Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows:
TABLE 2-2:
STATUS REGISTER
0 R WIP
7 654 3 2 1 W/R - - - W/R W/R R WPEN X X X BP1 BP0 WEL W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the 25AA512 is busy with a write operation. When set to a `1', a write is in progress, when set to a `0', no write is in progress. This bit is read-only.
FIGURE 2-6:
CS 0 SCK
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register 7 6 5 4 3 2 1 0
High-Impedance SO
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2010 Microchip Technology Inc.
25AA512
2.5 Write Status Register Instruction (WRSR)
The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 2-4 for a matrix of functionality on the WPEN bit. See Figure 2-7 for the WRSR timing sequence.
The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 2-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 2-3.
TABLE 2-3:
BP1
ARRAY PROTECTION
BP0 Array Addresses Write-Protected none Upper 1/4 (Sector 3) (C000h-FFFFh) Upper 1/2 (Sectors 2 & 3) (8000h-FFFFh) All (Sectors 0, 1, 2 & 3) (0000h-FFFFh) Array Addresses Unprotected All (Sectors 0, 1, 2 & 3) (0000h-FFFFh) Lower 3/4 (Sectors 0, 1 & 2) (0000h-BFFFh) Lower 1/2 (Sectors 0 & 1) (0000h-7FFFh) none
0 0 1 1
0 1 0 1
FIGURE 2-7:
CS 0 SCK
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Instruction SI 0 0 0 0 0 0 0 1 7 6
Data to STATUS Register 5 4 3 2 1 0
High-Impedance SO
2010 Microchip Technology Inc.
DS22021F-page 13
25AA512
2.6 Data Protection 2.7 Power-On State
The following protection has been implemented to prevent inadvertent writes to the array: * The write enable latch is reset on power-up * A write enable instruction must be issued to set the write enable latch * After a byte write, page write or STATUS register write, the write enable latch is reset * CS must be set high after the proper number of clock cycles to start an internal write cycle * Access to the array during an internal write cycle is ignored and programming is continued The 25AA512 powers on in the following state: * The device is in low-power Standby mode (CS = 1) * The write enable latch is reset * SO is in high-impedance state * A high-to-low-level transition on CS is required to enter active state
TABLE 2-4:
WEL (SR bit 1)
WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN (SR bit 7) WP (pin 3) Protected Blocks Protected Protected Protected Protected Unprotected Blocks Protected Writable Writable Writable STATUS Register Protected Writable Protected Writable
0 1 1 1 x = don't care
x 0 1 1
x x 0 (low) 1 (high)
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25AA512
2.8 PAGE ERASE
CS must then be driven high after the last bit of the address or the PAGE ERASE will not execute. Once the CS is driven high the self-timed PAGE ERASE cycle is started. The WIP bit in the STATUS register can be read to determine when the PAGE ERASE cycle is complete. If a PAGE ERASE instruction is given to an address that has been protected by the Block Protect bits (BP0, BP1) then the sequence will be aborted and no erase will occur. The PAGE ERASE instruction will erase all bits (FFh) inside the given page. A Write Enable (WREN) instruction must be given prior to attempting a PAGE ERASE. This is done by setting CS low and then clocking out the proper instruction into the 25AA512. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. The PAGE ERASE instruction is entered by driving CS low, followed by the instruction code (Figure 2-8) and two address bytes. Any address inside the page to be erased is a valid address.
FIGURE 2-8:
PAGE ERASE SEQUENCE
CS 0 SCK Instruction SI 1 1 0 1 1 0 0 16-bit Address 0 15 14 13 12 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23
High-Impedance SO
2010 Microchip Technology Inc.
DS22021F-page 15
25AA512
2.9 SECTOR ERASE
CS must then be driven high after the last bit of the address or the SECTOR ERASE will not execute. Once the CS is driven high the self-timed SECTOR ERASE cycle is started. The WIP bit in the STATUS register can be read to determine when the SECTOR ERASE cycle is complete. If a SECTOR ERASE instruction is given to an address that has been protected by the Block Protect bits (BP0, BP1) then the sequence will be aborted and no erase will occur. See Table 2-3 for Sector Addressing. The SECTOR ERASE instruction will erase all bits (FFh) inside the given sector. A Write Enable (WREN) instruction must be given prior to attempting a SECTOR ERASE. This is done by setting CS low and then clocking out the proper instruction into the 25AA512. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. The SECTOR ERASE instruction is entered by driving CS low, followed by the instruction code (Figure 2-9) and two address bytes. Any address inside the sector to be erased is a valid address.
FIGURE 2-9:
SECTOR ERASE SEQUENCE
CS 0 SCK Instruction SI 0 1 0 0 0 0 1 16-bit Address 0 15 14 13 12 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23
High-Impedance SO
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2010 Microchip Technology Inc.
25AA512
2.10 CHIP ERASE
The CS pin must be driven high after the eighth bit of the instruction code has been given or the CHIP ERASE instruction will not be executed. Once the CS pin is driven high the self-timed CHIP ERASE instruction begins. While the device is executing the CHIP ERASE instruction the WIP bit in the STATUS register can be read to determine when the CHIP ERASE instruction is complete. The CHIP ERASE instruction is ignored if either of the Block Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or all of the array is protected. The CHIP ERASE instruction will erase all bits (FFh) in the array. A Write Enable (WREN) instruction must be given prior to executing a CHIP ERASE. This is done by setting CS low and then clocking out the proper instruction into the 25AA512. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. The CHIP ERASE instruction is entered by driving the CS low, followed by the instruction code (Figure 2-10) onto the SI line.
FIGURE 2-10:
CHIP ERASE SEQUENCE
CS 0 SCK 1 2 3 4 5 6 7
SI
1
1
0
0
0
1
1
1
High-Impedance SO
2010 Microchip Technology Inc.
DS22021F-page 17
25AA512
2.11 DEEP POWER-DOWN MODE
All instructions given during Deep Power-Down mode are ignored except the Read Electronic Signature command (RDID). The RDID command will release the device from Deep power-down and outputs the electronic signature on the SO pin, and then returns the device to Standby mode after delay (TREL) Deep Power-Down mode automatically releases at device power-down. Once power is restored to the device it will power-up in the Standby mode. Deep Power-Down mode of the 25AA512 is its lowest power consumption state. The device will not respond to any of the Read or Write commands while in Deep Power-Down mode, and therefore it can be used as an additional software write protection feature. The Deep Power-Down mode is entered by driving CS low, followed by the instruction code (Figure 2-11) onto the SI line, followed by driving CS high. If the CS pin is not driven high after the eighth bit of the instruction code has been given, the device will not execute Deep power-down. Once the CS line is driven high there is a delay (TDP) before the current settles to its lowest consumption.
FIGURE 2-11:
DEEP POWER-DOWN SEQUENCE
CS 0 SCK 1 2 3 4 5 6 7
SI
1
0
1
1
1
0
0
1
High-Impedance SO
DS22021F-page 18
2010 Microchip Technology Inc.
25AA512
2.12 RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE
Release from Deep Power-Down mode and Read Electronic Signature is entered by driving CS low, followed by the RDID instruction code (Figure 2-12) and then a dummy address of 16 bits (A15-A0). After the last bit of the dummy address is clock in, the 8-bit Electronic Signature is clocked out on the SO pin. After the signature has been read out at least once, the sequence can be terminated by driving CS high. The device will then return to Standby mode and will wait to be selected so it can be given new instructions. If additional clock cycles are sent after the electronic signature has been read once, it will continue to output the signature on the SO line until the sequence is terminated.
Once the device has entered Deep Power-Down mode all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature command. This command can also be used when the device is not in Deep power-down to read the electronic signature out on the SO pin unless another command is being executed such as Erase, Program or Write Status Register.
FIGURE 2-12:
CS 0 SCK 1
RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
Instruction SI 1 0 1 0 1 0 1
16-bit Address 1 15 14 13 12 2 1 0 Electronic Signature Out 7 0 6 0 5 1 4 0 3 1 2 0 1 0 0 1
High-Impedance SO
Manufacturer's ID = 0x29 Driving CS high after the 8-bit RDID command but before the Electronic Signature has been transmitted will still ensure the device will be taken out of Deep Power-Down mode. However, there is a delay TREL that occurs before the device returns to Standby mode (ICCS), as shown in Figure 2-13.
FIGURE 2-13:
CS
RELEASE FROM DEEP POWER-DOWN
0 SCK
1
2
3
4
5
6
7
TREL
Instruction SI 1 0 1 0 1 0 1 1
High-Impedance SO
2010 Microchip Technology Inc.
DS22021F-page 19
25AA512
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1. The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25AA512 in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high.
TABLE 3-1:
Name CS SO WP VSS SI SCK HOLD VCC
PIN FUNCTION TABLE
Pin Number 1 2 3 4 5 6 7 8 Function Chip Select Input Serial Data Output Write-Protect Pin Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage
3.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock.
3.5
Serial Clock (SCK)
3.1
Chip Select (CS)
The SCK is used to synchronize the communication between a master and the 25AA512. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.
A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated.
3.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the 25AA512 while in the middle of a serial sequence without having to re-transmit the entire sequence over again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin should be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 25AA512 must remain selected during this sequence. The SI and SCK levels are "don't cares" during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD should be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-tolow transition of the HOLD pin, and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK.
3.2
Serial Output (SO)
The SO pin is used to transfer data out of the 25AA512. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.
3.3
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write.
DS22021F-page 20
2010 Microchip Technology Inc.
25AA512
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN XXXXXXX T/XXXXX YYWW NNN Example: 25AA512 I/MF e3 0728 1L7
8-Lead PDIP
XXXXXXXX T/XXXNNN YYWW
Example:
25AA512 I/P e3 1L7 0728
8-Lead SOIC
Example:
XXXXXXXT XXXXYYWW NNN
25AA512I SN e3 0728 1L7
8-Lead SOIJ
Example:
XXXXXXXX T/XXXXXX YYWWNNN
25AA512 I/SM e3 07281L7
Legend: XX...X T Y YY WW NNN
e3
Part number or part number code Temperature (I) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
Note:
2010 Microchip Technology Inc.
DS22021F-page 21
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2010 Microchip Technology Inc.
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2010 Microchip Technology Inc.
DS22021F-page 25
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DS22021F-page 26
2010 Microchip Technology Inc.
25AA512
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2010 Microchip Technology Inc.
DS22021F-page 27
25AA512
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS22021F-page 28
2010 Microchip Technology Inc.
25AA512
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
2010 Microchip Technology Inc.
DS22021F-page 29
25AA512
APPENDIX A:
Revision A
Original release.
REVISION HISTORY
Revision B (06/2007)
Revised Device Selection Table; Revised Features section; Revised Table 1-1 DC Characteristics; Revised Table 1-2 AC Characteristics; Replaced Package Drawings (Rev. AP); Revised Package Marking (SOIC, SOIJ); Revised Product ID section.
Revision C (10/2007)
Removed 25LC512 part number; New data sheet created for 25LC512 (DS22065); Revised Tables; Updates throughout.
Revision D (03/2008)
Revise Figures 2-11 and 2-12; Revise title to Figure 2-13; Update Package Drawings.
Revision E (5/2008)
Modified parameter D006 in Table 1-1; Revised Package Marking Information; Replaced Package Drawings; Revised Product ID section.
Revision F (05/10)
Revised Table 1-2, Param. No. 25 Conditions; Revised Section 2.2, added note; Added SOIC Land Pattern and updated SOIJ package drawings.
DS22021F-page 30
2010 Microchip Technology Inc.
25AA512
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
2010 Microchip Technology Inc.
Preliminary
DS22021F-page 31
25AA512
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: 25AA512 Questions: 1. What are the best features of this document? Y N Literature Number: DS22021F FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS22021F-page 32
2010 Microchip Technology Inc.
25AA512
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Tape & Reel
-
X Temp Range
/XX Package
Examples:
a) b) 25AA512-I/SN = 512 Kbit, 1.8V Serial EEPROM, Industrial temp., SOIC package 25AA512T-I/SM = 512 Kbit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, SOIJ package 25AA512T-I/MF = 512 Kbit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, DFN package
Device: Tape & Reel: Temperature Range: Package:
25AA512 Blank T I = = =
512 Kbit, 1.8V, 128-Byte Page SPI Serial EEPROM Standard packaging (tube) Tape & Reel -40C to+85C
c)
MF P SN SM
= = = =
Micro Lead Frame (6 x 5 mm body), 8-lead Plastic DIP (300 mil body), 8-lead Plastic SOIC (3.90 mm body), 8-lead Plastic SOIJ (5.28 mm body), 8-lead
2010 Microchip Technology Inc.
DS22021F-page 33
25AA512
NOTES:
DS22021F-page 34
2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-225-0
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc.
DS22021F-page 35
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/05/10
DS22021F-page 36
2010 Microchip Technology Inc.

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