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VND830-E
DOUBLE CHANNEL HIGH SIDE DRIVER
Table 1. General Features
Type VND830-E
(*) Per each channel
Figure 1. Package
Iout 6A (*) VCC 36V
RDS(on) 60m (*)
CMOS COMPATIBLE INPUTS OPEN DRAIN STATUS OUTPUTS ON STATE OPEN LOAD DETECTION OFF STATE OPEN LOAD DETECTION SHORTED LOAD PROTECTION UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN LOSS OF GROUND PROTECTION VERY LOW STAND-BY CURRENT

SO-16L
REVERSE BATTERY PROTECTION (**) IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE
DESCRIPTION The VND830-E is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active V CC pin voltage clamp protects the devices against low energy spikes (see ISO7637 transient compatibility table).
Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both is on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection.
Table 2. Order Codes
Package Tube VND830-E Tape and Reel VND830TR-E
SO-16L
Note: (*) See application schematic at page 9
Rev. 3 February 2005 1/20
VND830-E
Figure 2. Block Diagram
VCC
VCC CLAMP
OVERVOLTAGE UNDERVOLTAGE
GND INPUT1 STATUS1
CLAMP 1 OUTPUT1 DRIVER 1 CLAMP 2 CURRENT LIMITER 1 LOGIC OVERTEMP. 1 OPENLOAD ON 1 CURRENT LIMITER 2 DRIVER 2 OUTPUT2
INPUT2 OPENLOAD OFF 1 STATUS2 OPENLOAD OFF 2 OVERTEMP. 2 OPENLOAD ON 2
Table 3. Absolute Maximum Ratings
Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge (Human R=1.5K; C=100pF) VESD - INPUT - STATUS - OUTPUT - VCC Maximum Switching Energy EMAX Ptot Tj Tc Tstg (L=1.8mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=9A) Power Dissipation Tlead=25C Junction Operating Temperature Case Operating Temperature Storage Temperature 102 8.3 Internally Limited - 40 to 150 - 55 to 150 mJ W C C C Body Model: 4000 4000 5000 5000 V V V V Parameter Value 41 - 0.3 - 200 Internally Limited -6 +/- 10 +/- 10 Unit V V mA A A mA mA
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Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
VCC N.C. GND INPUT 1 STATUS 1 STATUS 2 INPUT 2 VCC
1
16
VCC OUTPUT 1 OUTPUT 1 OUTPUT 1 OUTPUT 2 OUTPUT 2 OUTPUT 2
8
9
VCC
Connection / Pin Status Floating X To Ground
N.C. X X
Output X
Input X Through 10K resistor
Figure 4. Current and Voltage Conventions
IS IIN1 INPUT 1 VIN1 VSTAT1 VIN2 ISTAT1 STATUS 1 IIN2 INPUT 2 ISTAT2 STATUS 2 VSTAT2 GND IGND OUTPUT 2 IOUT2 VOUT2 OUTPUT 1 VOUT1 VCC IOUT1
VF1 (*)
VCC
(*) VFn = VCCn - VOUTn during reverse battery condition
Table 4. Thermal Data
Symbol Rthj-lead Rthj-amb Parameter Thermal resistance junction-lead Thermal resistance junction-ambient (MAX) (MAX) Value 15 65 (*) 48 (**) Unit C/W C/W
Note: (*) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. Note: (**) When mounted on a standard single-sided FR-4 board with 6 cm 2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.
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ELECTRICAL CHARACTERISTICS (8VSymbol VCC (**) VUSD (**) VOV (**) RON Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance IOUT =2A; Tj =25 C IOUT =2A; VCC> 8V Off State; VCC=13V; VIN=VOUT=0V IS (**) Supply Current Off State; VCC=13V; VIN=VOUT=0V; 12 12 5 0 -75 Test Conditions Min. 5.5 3 36 60 120 40 25 7 50 0 5 3 Typ. 13 4 Max. 36 5.5 Unit V V V m m A A mA A A A A
Tj=25C
On State; VCC=13V; VIN=5V; IOUT=0A VIN=VOUT=0V VIN=0V; VOUT =3.5V VIN=VOUT=0V; VCC=13V; Tj =125C VIN=VOUT=0V; VCC=13V; Tj =25C
IL(off1) IL(off2) IL(off3) IL(off4)
Off State Output Current Off State Output Current Off State Output Current Off State Output Current
Note: (**) Per device.
Table 6. Protection (Per each channel) (See note 1)
Symbol TTSD TR Thyst TSDL Ilim Vdemag Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status Delay in Overload Conditions Current limitation Turn-off Output Clamp Voltage Test Conditions Min. 150 135 7 15 20 6 9 15 15 VCC-41 VCC-48 VCC-55 Typ. 175 Max. 200 Unit C C C s A A V
Tj>TTSD
VCC=13V 5.5V < VCC < 36V IOUT =2A; L= 6mH
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles
Table 7. VCC - Output Diode
Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=1.3A; Tj=150C Min Typ Max 0.6 Unit V
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ELECTRICAL CHARACTERISTICS (continued) Table 8. Status Pin
Symbol Parameter Test Conditions VSTAT Status Low Output Voltage ISTAT = 1.6 mA ILSTAT Status Leakage Current Normal Operation; VSTAT= 5V Status Pin Input Normal Operation; VSTAT= 5V CSTAT Capacitance ISTAT = 1mA VSCL Status Clamp Voltage ISTAT = - 1mA Min Typ Max 0.5 10 100 6 6.8 -0.7 8 Unit V A pF V V
Table 9. Switching (V CC=13V)
Symbol td(on) td(off) dV/dt(on) Parameter Turn-on Delay Time Turn-off Delay Time Turn-on Voltage Slope Test Conditions RL=6.5 from VIN rising edge to VOUT =1.3V RL=6.5 from VIN falling edge to VOUT =11.7V RL=6.5 from VOUT=1.3V to VOUT =10.4V RL=6.5 from VOUT=11.7V to VOUT =1.3V Min Typ 30 30 See relative diagram See relative diagram Max Unit s s V/s
dV/dt(off)
Turn-off Voltage Slope
V/s
Table 10. Openload Detection
Symbol IOL tDOL(on) VOL tDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V IOUT=0A VIN=0V 1.5 2.5 Min 50 Typ 100 Max 200 200 3.5 1000 Unit mA s V s
Table 11. Logic Input
Symbol VIL IIL VIH IIH Vhyst VICL Parameter Test Conditions Input Low Level Low Level Input Current VIN = 1.25V Input High Level High Level Input CurVIN = 3.25V rent Input Hysteresis Voltage IIN = 1mA Input Clamp Voltage IIN = -1mA Min 1 3.25 10 0.5 6 6.8 -0.7 8 Typ Max 1.25 Unit V A V A V V V
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Table 12. Truth Table
CONDITIONS Normal Operation INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H SENSE H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L
Current Limitation
Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL
Figure 5. Switching time Waveforms
VOUTn 90% 80%
dVOUT/dt(on)
dVOUT/dt(off)
10% t VINn
td(on)
td(off)
t
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Table 13. Electrical Transient Requirements On V CC Pin
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2
I C C C C C C
IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
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Figure 6. Waveforms
NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VCC VUSD INPUTn OUTPUT VOLTAGEn STATUSn undefined VUSDhyst
OVERVOLTAGE VCCVOL VOL
OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj INPUTn OUTPUT CURRENTn STATUSn TTSD TR
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VND830-E
Figure 7. Application Schematic
+5V +5V +5V VCC Rprot STATUS1 Dld C Rprot INPUT1 OUTPUT1 Rprot STATUS2
Rprot
INPUT2
GND
OUTPUT2
RGND VGND
DGND
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / IS(on)max. 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggest to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
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VND830-E
.C I/Os PROTECTION: If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RLOPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to
Figure 8. Open Load detection in off state
V batt.
VPU
VCC RPU INPUT DRIVER + LOGIC OUT + R STATUS VOL RL IL(off2)
GROUND
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Figure 9. Off State Output Current
IL(off1) (uA)
2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 175
Figure 12. High Level Input Current
Iih (uA)
5 4.5
Off state Vcc=36V Vin=Vout=0V
Vin=3.25V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 10. Input Clamp Voltage
Vicl (V)
8 7.8
Figure 13. Status Leakage Current
Ilstat (uA)
0.05
Iin=1mA
7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 0 -50 -25 0 25 50 75 100 125 150 175 0.01 0.02 0.03 0.04
Vstat=5V
Tc (C)
Tc (C)
Figure 11. Status Low Output Voltage
Vstat (V)
0.8 0.7
Figure 14. Status Clamp Voltage
Vscl (V)
8 7.8
Istat=1.6mA
0.6
Istat=1mA
7.6 7.4
0.5 0.4 0.3 0.2
7.2 7 6.8 6.6 6.4
0.1 0 -50 -25 0 25 50 75 100 125 150 175
6.2 6 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VND830-E
Figure 15. Overvoltage Shutdown
Vov (V)
50 48 46 44 42 40 38 36 34 32 30 -50 -25 0 25 50 75 100 125 150 175
Figure 18. ILIM Vs Tcase
Ilim (A)
20 18
Vcc=13V
16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 16. Turn-on Voltage Slope
dVout/dt(on) (V/ms)
800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 19. Turn-off Voltage Slope
dVout/dt(off) (V/ms)
600 550 500 450 400 350 300 250 200 -50 -25 0 25 50 75 100 125 150 175
Vcc=13V Rl=6.5Ohm
Vcc=13V Rl=6.5Ohm
Tc (C)
Tc (C)
Figure 17. On State Resistance Vs Tcase
Ron (mOhm)
160 140 120 100
Figure 20. On State Resistance Vs VCC
Ron (mOhm)
120 110
Tc=150C
Iout=2A Vcc=8V; 13V & 36V
100 90 80 70
80 60
60 50 40
Tc=25C
Tc= - 40C
40 20
30 20 10
Iout=5A
0 -50 -25 0 25 50 75 100 125 150 175
0 5 10 15 20 25 30 35 40
Tc (C)
Vcc (V)
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VND830-E
Figure 21. Input High Level
Vih (V)
3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 -50 -25 0 25 50 75 100 125 150 175
Figure 24. Input Low Level
Vil (V)
2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 22. Openload On State Detection Threshold
Iol (mA)
150 140
Figure 25. Openload Off State Detection Threshold
Vol (V)
5 4.5
Vin=0V
4
130 120 110 100
Vcc=13V Vin=5V
3.5 3 2.5 2 1.5
90 80 70 -50 -25 0 25 50 75 100 125 150 175
1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
T (C) c
Tc (C)
Figure 23. Input Hysteresis Voltage
Vhyst (V)
1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
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VND830-E
Figure 26. SO-16L Maximum turn off current versus load inductance
ILMAX (A) 100
10
A B C
1 0.1 1 L(mH)
A = Single Pulse at TJstart=150C B= Repetitive pulse at T Jstart=100C C= Repetitive Pulse at T Jstart=125C Conditions: VCC=13.5V Values are generated with R L=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.
10
100
VIN, IL Demagnetization Demagnetization Demagnetization
t
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VND830-E
SO-16L Thermal Data Figure 27. SO-16L PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 41mm x 48mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.5cm2, 6cm2).
Figure 28. Rthj-amb Vs PCB copper area in open box free air condition
70 65 60 55 50 45 40
RTH j-amb (C/W)
0
1
2
3
4
5
6
7
PCB Cu heatsink area (cm^2)
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VND830-E
Figure 29. SO-16L Thermal Impedance Junction Ambient Single Pulse
ZT H (C/W) 1000
100
Footprint 6 cm2
10
1
0.1
0.01 0.0001 0.001 0.01 0.1 1 T ime (s) 10 100 1000
Figure 30. Thermal fitting model of a double channel HSD in SO-16L
Pulse calculation formula
Z TH = R TH + Z THtp ( 1 - )
where
= tp T
Table 14. Thermal Parameter
Tj_1
Pd1 C1 C2 C1 C2 C3 C4 C5 C6
R1
R2
R3
R4
R5
R6
Tj_2
R1 Pd2
R2
T_amb
R1 R2 R3 R4 R5 R6 C1 C2 C3 C4 C5 C6
Area/island (cm2) (C/W) (C/W) ( C/W) (C/W) (C/W) (C/W) (W.s/C) (W.s/C) (W.s/C) (W.s/C) (W.s/C) (W.s/C)
Footprint 0.05 0.3 2.2 12 15 37 0.001 5.00E-03 0.02 0.3 1 3
6
22
5
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VND830-E
PACKAGE MECHANICAL Table 15. SO-16L Mechanical Data
Symbol A a1 a2 b b1 C c1 D E e e3 F L M S millimeters Min 0.1 0.35 0.23 0.5 45 (typ.) 10.1 10.0 1.27 8.89 7.4 0.5 8 (max.) 7.6 1.27 0.75 10.5 10.65 Typ Max 2.65 0.2 2.45 0.49 0.32
Figure 31. SO-16L Package Dimensions
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VND830-E
Figure 32. SO-16L Tube Shipment (No Suffix)
C B
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1)
All dimensions are in mm.
50 1000 532 3.5 13.8 0.6
A
Figure 33. Tape And Reel Shipment (Suffix "TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max)
1000 1000 330 1.5 13 20.2 16.4 60 22.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 16 4 12 1.5 1.5 7.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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REVISION HISTORY
Date Nov. 2004 Feb. 2005 Revision Description of Changes 2 - RDS(on) value correction: 60m instead of 35m. 3 - Iol curve changed.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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