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| TECHNICAL NOTE Ultra Small Headphone Amplifier Series Digital Input Hi-Fi Class-D Headphone Amplifier BU7839GVW Description Most suitable for long duration reproduction of digital audio because digital audio data is taken as its input and low power consumption is realized. BU7839GVW has Stereo Audio DAC and HP amp functions for digital audio playback. Pop sound in ramp-up period is reduced due to built-in start-up sound reduction circuit or transistor for mute. Also, Built-in digital volume which can control L-ch & R-ch separately. Features 1) With Stereo Audio DAC and HP amp functions 2) Most suitable for long duration reproduction of digital audio because digital audio data is taken as its input and low power consumption is realized 3) Pop sound in ramp-up period is reduced due to built-in start-up sound reduction circuit or transistor for mute 4) Built-in digital volume which can control L-ch & R-ch separately Immediate switching and zero cross switching for reduction of clicking sound at the time of gain change Gain change methods of soft switching can be selected with registers 5) Sampling frequency compatible with 8kHz-48kHz 6) Compatible with master slave with built-in PLL 7) Built-in soft mute function 8) Compatible with full front and full back formats 9) Compatible with 16, 18 & 24bit formats 10) Compatible with fs=32kHz,44.1kHz,48kHz with de-emphasis function 11) 2wire CPU I/F (2 addresses selectable 33h, 36h) Function Stereo Audio DAC + HPamp 2wire CPU I/F Serial audio I//F Interpolator Modulator Level Shifter PLL Aug. 2008 Absolute maximum rating Parameter Analog power supply voltage Digital power supply voltage Digital IO power supply voltage Terminal applied voltage 1 Terminal applied voltage 2 *1 Symbol AVDD DVDD DVDDI O VIN1 VIN2 Pd Tstg Topr rating -0.3 4.5 -0.3 2.1 -0.3 4.5 DVSS-0.3 DVDDIO+0.3 DVSS-0.3 4.5 520 *2 -50 125 -30 85 Unit V V V V V mW degree degree Allowance loss Storage temperature range Operation temperature range Fig.1 Absolute maximum rating *1 SDA,SCL terminal *2 When you use at above Ta = 25 degree, 52mW are reduced concerning 1degree When you mount 114.6mm x 76.2mm x 1.6mm Note:When you use under the conditions which exceed this value, there are times when the device is destroyed. In addition usual operation is not guaranteed. Recommended operating range Parameter Analog power supply voltage Digital IO power supply voltage Digital power supply voltage Symbol AVDD DVDDIO DVDD Min 2.5 DVDD 1.35 Limit Typ 2.8 1.50 Max 3.0 3.0 1.65 Unit V V V Fig.2 Recommended operating range 2 / 15 External size figure 7839 LOT No. Fig.3 External size figure 3 / 15 Block diagram MUTE_R MCLK Interpolator BCLK LRCLK SDI Audio I/F VDD_R Modulator Level Shifter OUT_R VSS_R MUTE_L VDD_L DVDDIO DVSSIO 256fs Interpolator Modulator Level Shifter OUT_L VSS_L PLLVDD SCL SDA NRST 2wire CPU I/F Register Power on/off control PLL PLLCAP DVSS ADR TEST DVDD DVSS REFCLK 12MHz in Fig. 4 Block diagram Description of each block 2wire CPU I/F Interface with CPU, 2-wire control Write/read possible Device address is 2-address selectable (33h,36h) with ADR terminal Register This LSI is controlled all by register Write/read by 2wire CPU I/F Audio I/F Compatible with three modes of full front, full back and IIS Sampling frequency compatible with 8kHz48kHz Interpolator,Modulator Variable over sampling, Order-variable modulator Optimum value is selected internally and automatically Level Shifter Level conversion in 3V series of analogue output Built-in mute transistor for start-up sound reduction PLL REFCLK terminal is taken as reference clock and 256fs is created It becomes the default setting when 12MHz is inputted to REFCLK Please change each setting if any frequency other than 12MHz is inputted to REFCLK 4 / 15 Terminal table No A1 B3 A2 C2 C1 B4 A5 B2 A3 C3 D1 A4 B5 D5 C5 C4 D4 E4 E5 D3 E1 E2 D2 E3 Terminal name MCLK BCLK LRCLK SDI DVDDIO SCL SDA NRST ADR TEST DVDD DVSS REFCLK PLLVDD PLLCAP DVSS VDD_R OUT_R MUTE_R VSS_R VDD_L OUT_L MUTE_L VSS_L Function Audio I/F Master clock Audio I/F Bit clock Audio I/F LR clock Audio I/F Serial data Digital IO VDD 2wire CPU I/F serial clock 2wire CPU I/F serial data Reset Device address select test pin Digital core VDD Digital core VSS reference clock PLL VDD PLL capacitor PLL, Digital VSS Analog VDD Rch output Rch mute Analog VSS Analog VDD Lch output Lch mute Analog VSS Classificati on Digital/ Analog In/Out Rest middle/rear Initial value Note 256fs 64fs fs I/O power supply A B B E C D E E E H F G I G I - D D D D D D D D D D D D D A A D A A A A A A A A In/Out In/Out In/Out In In In/Out In In In In Out Out Out Out Out - in in in in Hiz Hiz Hiz Hiz Hiz - L: reset L:33h or H:36h Please connect to the ground Digital power supply Digital ground Input 10M20MHz PLL power supply PLL, Digital ground Rch power supply For starting sound decrease Rch ground Lch power supply For starting sound decrease Lch ground Table 5 Terminal table Terminal equivalent circuit figure A DVDDIO B LVS DVDDIO C LVS LVS DVSSIO DVSSIO DVSSIO D LVS E DVDDIO F LVS PLLVDD DVSSIO DVSSIO PLLVSS G VDD_R VDD_R VDD_L VDD_L H DVDDIO I LVS VDD_R VDD_L DVSSIO VSS_R VSS_R VSS_L VSS_L VSS_R VSS_R VSS_L VSS_L Table 6 Terminal equivalent circuit figure 5 / 15 Application circuit chart MUTE_R VDD_R MCLK BCLK DSP LRCLK SDI DVDD2.8V 2.8V 220uF 16 Interpolator Modulator Level Shifter OUT_R VSS_R 100uH 0.1uF Audio I/F MUTE_L VDD_L 2.8V 220uF 100uH 0.1uF 16 DVDDIO Interpolator Modulator Level Shifter OUT_L VSS_L 256fs PLLVDD SCL CPU SDA 2wire CPU I/F Register Power on/off control 0.068uF 2.8V PLL PLLCAP DVSS NRST L: reset ADR Device address L: 33h H: 36h TEST DVDD 1.5V DVSS REFCLK 12MHz in Recommended parts Coil : murata Manufacturing LQH32CN101K23 Schottky diode : ROHM RSX201L-30 Capacitor : Rohm TCTAL0G227M8R-D2 Fig.7 Application circuit chart Measurement circuit chart MUTE_R VDD_R MCLK BCLK DSP LRCLK SDI DVDD2.8V 2.8V 220uF 100uH 0.1uF Interpolator Modulator Level Shifter OUT_R VSS_R 20KHz LPF A-Weight Audio Analyzer 16 Audio I/F MUTE_L VDD_L 2.8V 220uF 100uH 20KHz LPF A-Weight 16 Audio Analyzer DVDDIO Interpolator Modulator Level Shifter OUT_L VSS_L 0.1uF 2.8V 256fs PLLVDD SCL CPU SDA 2wire CPU I/F Register Power on/off control 0.068uF PLL PLLCAP DVSS NRST L: reset ADR Device address L: 33h H: 36h TEST DVDD 1.5V DVSS REFCLK 12MHz in Fig.8 Measurement circuit chart 6 / 15 Electrical Characteristic Ta=25degree,DVDD=DVDDIO=1.5V,VDD_R=VDD_L=PLLVDD=2.8V,REFCLK=12MHz,fs=44.1kHz,f=1kHz,Load=16,A-weight, 20kHzLPF,Slave mode Item Static consumption DVDD Static consumption VDD_R+VDD_L Static consumption PLLVDD current current current Symbol IDDst ICCst IPLLst IDD ICC IPLL Vout Gerr SN THD Iso Psrr Standardized values MIN -2 -1 60 -40 65 TYP 0.6 2.0 0.8 80 -60 80 0 MAX 10 10 10 2.0 6.0 2.5 2 1 - Unit Note uA uA uA mA mA mA At the time of standby At the time of standby At the time of standby At the time of 0.1mW output (in slave mode) At the time of 0.1mW output Consumption current DVDD Consumption VDD_R+VDD_L current Consumption current PLL Output amplitude error Channel-to-channel gain error S/N THD+N Channel-to-channel isolation PSRR Errors with reference to dB dB dB dB dB dB standard values at the time of 0dBFS output are as follows Lch-Rch 0dBFS, A-Weight -3dBFS, A-Weight 0dBFS, 1kHz BPF Table 9 Electrical characteristic Output amplitude error Output amplitude is determined by the equivalent series resistance of external coil. Let Lr, VDD and Z respectively stand for the equivalent series resistance, the power supply voltage value of VDD_R,VDD_L and the load impedance, the standard value of output amplitude becomes the following equation: Standard value of output amplitude [Vpp] = VDD x 0.5 x Z / ( Lr + Z + 2 ) OUT_R OUT_L Level Shifter 2 Lr 100uH 0.1uF 220uF Z (16) Shown in the following table is the standard values of output amplitude if VDD=2.8V, Load impedance Z=16, and Equivalent series resistance is 0.7, 4 or 7. Equivalent series resistance [] Standard value of Standard value of output amplitude [Vpp] output amplitude [dBv] Output power [mW] 0.0 0.7 4.0 7.0 1.24 1.20 1.02 0.90 -7.13 -7.46 -8.87 -9.98 12.10 11.21 8.10 6.27 7 / 15 DC characteristic Ta=25degree,DVDD=DVDDIO=1.5V, VDD_R=VDD_L=PLLVDD=2.8V Item Input 'H' Level Input 'L' Level Output 'H' Level Output 'L' Level 1 Output 'L' Level 2 (SDA terminal) Symbol VIH VIL VOH VOL1 VOL2 Standardized values MIN 0.7x DVDDIO 0.8x DVDDIO TYP MAX 0.3x DVDDIO 0.2x DVDDIO 0.2x DVDDIO Unit V V V V V Io=-1mA Io=1mA Io=3mA Note Table 10 DC characteristic 2wire CPU I/F Part Device address is "0110011"(33h) or "0110110"(36h), i.e. 33h when ADR terminal is L or 36h when ADR terminal is H. Please don't switch the ADR terminal while 2wire CPU I/F is operating. The transmission rate is compatible with a maximum of 400kbps 2wire CPU I/F device address ADR 0 1 Bit transmission A7 0 0 A6 1 1 A5 1 1 A4 0 0 A3 0 1 A2 1 1 A1 1 0 W/R 0/1 0/1 The data of 1bit is transmitted while SCL is H. In case of bit transmission, the signal transition of SDA can not be implemented while SCL is H. If SDA changes while SCL is H, START condition or STOP condition is generated, it is interpreted as control signal. SDA SCL SDA SDA stable state: SDA SDA change is Data is effective Possible START condition/STOP condition Data transmission on bus is not implemented while SDA and SCL are H. At this time, if SCL remains to be H and SDA is transited from H to L, then the START condition (S) is attained and so the access is started, and if SCL remains to be H and SDA is transited from L to H, then the STOP condition (P) is attained and so the access is terminated, which is shown below. SDA SCL S START START condition P STOP STOP condition This device accepts the continuous START condition and the continuous STOP condition. 8 / 15 Acknowledge After START condition is generated, data is transmitted at 8 bits once. After 8 bit transmission, the transmitter opens SDA, and the receiver returns the acknowledge signal with SDA taken as L. SDA output by transmitter SDA SDA output by receiver Non-acknowledge SDA acknowledge SCL S 1 2 8 Clock pulse for acknowledge 9 START CONDITION START Write protocol Write protocol is shown below. Register address is transmitted by 1 byte after device address and write command have been transmitted. Third byte writes the data, which is written in by second byte, into internal register, and for fourth byte and subsequent bytes, the register address is incremented automatically. But, the register address becomes 00h by the transmission of 1 byte after the register address has become the final address (6Ch). The address is incremented after the transmission is over. S0110 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A Register address R/W=0 () (Write D7 D6 D5 D4 D3 D2 D1 D0 A P Data Device address Data in) Transmitting set is on Master side Register address increment Register address increment Transmitting set is on Slave side A= Acknowledge A= Non-acknowledge S= START condition P= STOP condition Sr= starting condition Retransmission Readout protocol Readout starts from 1 byte after device address and R/W bit have been written in. For the address after the readout register is finally accessed and the subsequent addresses, the data of the addresses that have been incremented is read out. As the readout of 1 byte after the address has become the final address, 00h is read out. The address is incremented after the transmission is over. S0110 011 0 A D7 D6 D5 D4 D3 D2 D1 D0 A Data R/W=0 () in) (Write Register address increment D7 D6 D5 D4 D3 D2 D1 D0 A P Data Device address Register address increment Transmitting set is on Master side Transmitting set is on Slave side A= Acknowledge A= Non-acknowledge START condition S= STOP condition P= Retransmission Sr= starting condition 9 / 15 Compound readout protocol After internal address is specified, create the retransmission starting condition, change the data transmitting direction and implement the readout. Subsequently, the data of the address that has been incremented is read out. As the readout of 1 byte after the address has become the final address, 00h is read out. The address is incremented after the transmission is over. After retransmission starting condition, compound write is possible with R/W=0 (write in). S01 10 01 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr 0 Register address (Write in) R/W=0 (White in) 11 0 01 11 A Device address Slave address (Readout) R/W=1(Readout) D7 D6 D5 D4 D3 D2 D1 D0 A Data D7 D6 D5 D4 D3 D2 D1 D0 A P Data Register address increment Transmitting set is on Master side Register address increment Transmitting set is on slave side A= Acknowledge Non-acknowledge A= START condition S= STOP condition P= Retransmission starting condition Sr= Timing diagram (Repeated) START START condition BIT 7 BIT 6 Acknowledge STOP STOP condition t SU;STA SCL SDA tLOW t HIGH 1/fSCLK t BUF t HD;STA tSU;DAT t HD;DAT tSU;STO Ta=25 degree,DVDD=DVDDIO=1.8V, VDD_R=VDD_L=PLLVDD=3.0V Standard mode Item Symbol min max SCL clock frequency Hold time of START condition "" Level time of SCL "H" Level time of SCL Setup time of repeated START condition Data hold time Data setup time Setup time of STOP condition Bus opening time between STOP condition and START condition 1 fSCLK HD;STA ;STA High-speed mode min max 0 0.6 1.3 0.6 0.6 0.1 100 0.6 1.3 400 0.9 - Unit kHz s s s s s ns s s 0 4.0 4.7 4.0 4.7 0.1 250 4.0 4.7 100 3.45 - tHD;DAT tSU;DAT tSU;STO tBUF *1 The maximum tHD;DAT is not allowed to exceed the "L" level time tLOW of SCL signal 10 / 15 Audio I/F part At slave mode. Ta=25degree ,DVDD=DVDDIO=1.5V, VDD_R=VDD_L=PLLVDD=2.8 V Parameter MCLK frequency *1 MCLK Duty Cycle BCLK frequency BCLK Duty Cycle LRCLK frequency LRCLK Hold Time SDI Setup Time SDI Hold Time Symbol Fmclk Dmclk Fbclk Dbclk Flrclk Thdlr Tsusdi Thdsdi MIN 2.048 40 0.512 40 8 80 80 80 Limit TYP MAX 18.432 60 3.072 60 48 Unit MHz % MHz % kHz ns ns ns Flrclk = 1fs Fbclk = 64fs Fmclk 384fs Condition = 256fs or *1 It is not necessary to adjust the phase of MCLK and BCLK and LRCLK, but it is necessary to be something related to synchronization Table.11 Audio I/F AC characteristic(at slave mode) Flrclk LRCLK Thdlr Thdlr BCLK Fbclk SDI Tsusdi Thdsdi Fig.12 Audio I/F AC timing(at slave mode) At master mode Ta=25degree,DVDD=DVDDIO=1.5V, VDD_R=VDD_L=PLLVDD=2.8V Parameter BCLK frequency LRCLK frequency SDI Setup Time SDI Hold Time Symbol Fbclk Flrclk Tsusdi Thdsdi MIN 0.512 8 80 80 Limit TYP MAX 3.072 48 Unit MHz kHz ns ns Condition Fbclk = 64fs Flrclk = 1fs Table.13 Audio I/F AC characteristic(at master mode) Flrclk LRCLK BCLK Fbclk SDI Tsusdi Thdsdi Fig.14 Audio I/F AC timing(at master mode) 11 / 15 Audio I/F format At bit[1:0]="00" (16bit length) Rear stuffing format LRCLK 0 1 2 3 13 14 Lch 15 16 17 18 29 30 31 0 1 2 3 13 14 15 Rch 16 17 18 29 30 31 0 BCLK SDI Don't care Don't care 15 14 13 2 1 0 Don't care Don't care 15 14 13 2 1 0 Don't care Front stuffing format LRCLK 0 1 2 3 13 14 Lch 15 16 17 18 29 30 31 0 1 2 3 13 14 15 Rch 16 17 18 29 30 31 0 BCLK SDI Format IIS 15 14 13 2 1 0 Don't care Don't care 15 14 13 2 1 0 Don't care Don't care 15 LRCLK 0 1 2 3 4 14 Lch 15 16 17 18 19 30 31 0 1 2 3 13 14 15 Rch 16 17 18 19 30 31 0 BCLK SDI Don't care 15 14 13 2 1 0 Don't care Don't care 15 14 13 2 1 0 Don't care Don't care At bit[1:0]="01" (18bit length) Rear stuffing Format LRCLK 0 1 2 3 11 12 Lch 13 14 15 16 29 30 31 0 1 2 3 11 12 13 Rch 14 15 16 29 30 31 0 BCLK SDI Don't care Don't care 17 16 15 2 1 0 Don't care Don't care 17 16 15 2 1 0 Don't care Front stuffing format LRCLK 0 1 2 3 15 16 Lch 17 18 19 20 29 30 31 0 1 2 3 15 16 17 Rch 18 19 20 29 30 31 0 BCLK SDI Format IIS 17 16 15 2 1 0 Don't care Don't care 17 16 15 2 1 0 Don't care Don't care 15 LRCLK 0 1 2 3 4 16 Lch 17 18 19 20 21 30 31 0 1 2 3 13 16 17 Rch 18 19 20 21 30 31 0 BCLK SDI Don't care 17 16 15 2 1 0 Don't care Don't care 17 16 15 2 1 0 Don't care Don't care 12 / 15 At bit[1:0]="10" (20bit length) Rear stuffing format LRCLK 0 1 2 3 10 11 Lch 12 13 14 15 29 30 31 0 1 2 3 13 14 15 Rch 16 17 18 29 30 31 0 BCLK SDI Don't care Don't care 19 18 17 2 1 0 Don't care Don't care 19 18 17 2 1 0 Don't care Front stuffing format LRCLK 0 1 2 3 17 18 Lch 19 20 21 22 29 30 31 0 1 2 3 17 18 19 Rch 20 21 22 29 30 31 0 BCLK SDI format IIS 19 18 17 2 1 0 Don't care Don't care 19 18 17 2 1 0 Don't care Don't care 19 LRCLK 0 1 2 3 4 18 Lch 19 20 21 22 23 30 31 0 1 2 3 13 18 19 Rch 20 21 22 23 30 31 0 BCLK SDI Don't care 19 18 17 2 1 0 Don't care Don't care 19 18 17 2 1 0 Don't care Don't care At bit[1:0]="11" (24bit length) Rear stuffing format LRCLK 0 1 2 3 4 5 6 Lch 7 8 9 10 29 30 31 0 1 2 3 4 5 6 7 Rch 8 9 10 29 30 31 0 BCLK SDI Don't care 23 24 2 1 0 Don't care 23 22 2 1 0 Don't care Front stuffing format LRCLK 0 1 2 3 22 23 Lch 24 25 26 27 28 29 30 31 0 1 2 3 22 23 Rch 24 25 26 27 28 29 30 31 0 BCLK SDI format IIS 23 22 21 1 0 Don't care 23 22 21 1 0 Don't care 23 LRCLK 0 1 2 3 4 23 Lch 24 25 26 27 28 29 30 31 0 1 2 3 13 23 24 Rch 25 26 27 28 29 30 31 0 BCLK SDI Don't care 23 22 21 1 0 Don't care 23 22 21 1 0 Don't care Fig.15 Audio I/F Format 13 / 15 PLL Part Ta=25degree,DVDD=DVDDIO=1.5V, VDD_R=VDD_L=PLLVDD=2.8V, REFCLK=12MHz, fs=44.1kHz Item Lock up time BCLK Duty Cycle Symbol Tlock Dbclk MIN 40 specification TYP MAX 15 60 Unit msec % Condition Table 16 Electric characteristic PLLCAP 0.068uF REFCLK 12MHz 1/N PD VCO 1/M div_vco fs=48k,44.1k,32k fs 1/2 n32 n44 n48 refclk_enb p_pll m32 m44 m48 fs=24k,22.05k,16k 1/4 slave MCLK 0 1 256fs/384fs mclk_enb 1/4 1/256 fs=12k,11.025k,8k BCLK 64fs LRCLK fs slave D-Class Logic Fig.17 Block diagram of PLL part 14 / 15 SBGA024T040 Tape Quantity 1Pin MARK 5 4 3 21 A B C D E Embossed carrier tape(with dry pack) 2500pcs E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand.) P=0.65x4 0.65 B 4.00.1 Direction of feed 24-0.330.05 0.08 M S A B 0.70.1 4.00.1 0.70.1 A 0.65 P=0.65x4 S 0.10 S 1.2MAX 1234 1234 1234 1234 1234 1234 Reel 1Pin When you order , please order in times the amount of package quantity. (Unit:mm) 15 / 15 Catalog No.08T337A '08.8 ROHM (c) Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright (c) 2009 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster @ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix-Rev4.0 |
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