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| PSMN059-150Y N-channel TrenchMOS standard level FET Rev. 01 -- 5 May 2008 Product data sheet 1. Product profile 1.1 General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features I Low body Qr I Fast switching 1.3 Applications I Industrial DC motor control I DC-to-DC converters I Class D audio I Switched-mode power supplies 1.4 Quick reference data I VDS 150 V I RDSon 59 m I ID 43 A I QGD = 9.1 nC (typ) 2. Pinning information Table 1. Pin 1, 2, 3 4 mb Pinning Description source (S) gate (G) mounting base; connected to drain (D) 1234 mb D Simplified outline Symbol G mbb076 S NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 3. Ordering information Table 2. Ordering information Package Name PSMN059-150Y LFPAK Description plastic single-ended surface-mounted package; 4 leads Version SOT669 Type number 4. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 12.1 A; tp = 0.21 ms; VDS 150 V; RGS = 50 ; VGS = 10 V; starting at Tj = 25 C Tmb = 25 C; VGS = 10 V; see Figure 2 and 3 Tmb = 100 C; VGS = 10 V; see Figure 2 Tmb = 25 C; pulsed; tp 10 s; see Figure 3 Tmb = 25 C; see Figure 1 Conditions 25 C Tj 150 C 25 C Tj 150 C; RGS = 20 k Min -55 -55 Max 150 150 20 43 27.7 129 113 +150 +150 52 208 255 Unit V V V A A A W C C A A mJ Source-drain diode Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 2 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 120 Pder (%) 80 003aab937 120 Ider (%) 80 003aac023 40 40 0 0 50 100 150 Tmb (C) 200 0 0 50 100 150 Tmb (C) 200 P tot P der = ----------------------- x 100 % P tot ( 25C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature 103 ID (A) 102 Limit RDSon = VDS / ID ID I der = ------------------- x 100 % I D ( 25C ) Fig 2. Normalized continuous drain current as a function of mounting base temperature 003aab749 tp = 10 s 10 100 s 1 ms DC 1 10 ms 100 ms 10-1 1 10 102 VDS (V) 103 Tmb = 25 C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 3 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 5. Thermal characteristics Table 4. Rth(j-mb) [1] Thermal characteristics Conditions [1] Symbol Parameter Min - Typ - Max 1.1 Unit K/W thermal resistance from junction to mounting base see Figure 4 Mounted on a printed-circuit board; vertical in still air. 10 Zth(j-mb) (K/W) 1 d = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 single shot tp P 003aac268 = tp T t T 10-3 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 4 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 6. Characteristics Table 5. Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 C Tj = 150 C Tj = -55 C IDSS drain leakage current VDS = 120 V; VGS = 0 V Tj = 25 C Tj = 150 C IGSS RG RDSon gate leakage current gate resistance drain-source on-state resistance VGS = 20 V; VDS = 0 V f = 1 MHz VGS = 10 V; ID = 12 A; see Figure 6 and 8 Tj = 25 C Tj = 150 C Dynamic characteristics QG(tot) QGS QGD VGS(pl) Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 12 A; VGS = 0 V; see Figure 13 IS = 12 A; dIS/dt = -100 A/s; VGS = 0 V VDS = 75 V; RL = 3 ; VGS = 10 V; RG = 5.6 VGS = 0 V; VDS = 30 V; f = 1 MHz; see Figure 14 ID = 12 A; VDS = 75 V; VGS = 10 V; see Figure 11 and 12 27.9 6.3 9.1 4.8 1529 208 66 14.2 42 54.2 11.1 0.9 114 175 1.2 nC nC nC V pF pF pF ns ns ns ns V ns nC 46 101 59 135 m m 1.1 1 100 100 A A nA 2 1 3 4 4.4 V V V 150 133 V V Conditions Min Typ Max Unit Source-drain diode PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 5 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 50 ID (A) 40 10 7 003aab751 150 RDSon (m) 120 4.5 5 5.5 003aab752 6 VGS (V) = 6 30 VGS (V) = 5.5 90 7 10 20 5 10 4.5 0 0 1 2 3 4 VDS (V) 5 0 0 10 20 30 40 ID (A) 50 30 60 Tj = 25 C Tj = 25 C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 60 ID (A) 45 VDS > ID x RDSon 003aab753 Fig 6. Drain-source on-state resistance as a function of drain current; typical values 3 a 03al51 2 30 Tj = 150 C 15 25 C 1 0 0 2 4 6 VGS (V) 8 0 -75 -25 25 75 125 Tj (C) 175 Tj = 25 C and 150 C; VDS > ID x RDSon R DSon a = ----------------------------R DSon ( 25C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 6 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 5 VGS(th) (V) 4 max 003aab852 10-1 ID (A) 10-2 min typ 003aab853 max 3 typ 10-3 2 min 10-4 1 10-5 0 -60 10-6 0 60 120 Tj (C) 160 0 2 4 VGS (V) 6 ID = 1 mA; VDS = VGS Tj = 25 C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature 10 VGS (V) 8 75 6 VDS = 120 V 4 ID = 12 A Tj = 25 C 30 003aab754 Fig 10. Sub-threshold drain current as a function of gate-source voltage VDS ID VGS(pl) VGS(th) 2 VGS QGS1 QGS2 QGD QG(tot) 003aaa508 QGS 0 0 7.5 15 22.5 QG (nC) 30 ID = 12 A; VDS = 30, 75 and 120 V Fig 11. Gate-source voltage as a function of gate charge; typical values Fig 12. Gate charge waveform definitions PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 7 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 80 IS (X) 60 003aab756 104 C (pF) 003aab755 Ciss 103 40 150 C Tj = 25 C 102 Coss 20 Crss 0 0 0.3 0.6 0.9 VSD (V) 1.2 10 10-1 1 10 VDS (V) 102 Tj = 25 C and 150 C; VGS = 0 V VGS = 0 V; f = 1 MHz Fig 13. Source current as a function of source-drain voltage; typical values Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 8 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 E b2 L1 A c2 A2 C E1 b3 mounting base D1 H D b4 L2 1 e 2 3 b 1/2 e 4 wM A c X A A1 C (A 3) detail X L yC 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 0.25 0.30 4.10 4.20 0.19 0.24 3.80 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 Fig 15. Package outline SOT669 (LFPAK) PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 9 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 8. Revision history Table 6. Revision history Release date 20080505 Data sheet status Product data sheet Change notice Supersedes Document ID PSMN059-150Y_1 PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 10 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 9.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PSMN059_150Y_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 5 May 2008 11 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 May 2008 Document identifier: PSMN059_150Y_1 |
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