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SSTUM32866
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
Rev. 01 -- 29 June 2007 Product data sheet
1. General description
The SSTUM32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUM32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM. The SSTUM32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. The SSTUM32866 is the high-output drive version of SSTUG32866. The SSTUM32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).
2. Features
I I I I I I I I I I I I I I I Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Meets or exceeds SSTUM32866 JEDEC standard speed performance High output drive Supports up to 550 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports SSTL_18 data inputs Checks parity on the DIMM-independent data inputs Partial parity output and input allows cascading of two SSTUM32866s for correct parity error processing Differential clock (CK and CK) inputs Supports LVCMOS switching levels on the control and RESET inputs Single 1.8 V supply operation (1.7 V to 2.0 V) Available in 96-ball, 13.5 mm x 5.5 mm, 0.8 mm ball pitch LFBGA package
NXP Semiconductors
SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
3. Applications
I 400 MT/s to 800 MT/s and higher DDR2 registered DIMMs desiring parity checking functionality
4. Ordering information
Table 1. Ordering information Solder process Package Name Description Version Type number
SSTUM32866EC/G Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1 ball compound) 96 balls; body 13.5 x 5.5 x 1.05 mm SSTUM32866EC/S Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1 ball compound) 96 balls; body 13.5 x 5.5 x 1.05 mm
4.1 Ordering options
Table 2. Ordering options Temperature range Tamb = 0 C to +70 C Tamb = 0 C to +85 C Type number SSTUM32866EC/G SSTUM32866EC/S
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
5. Functional diagram
RESET
CK CK VREF DCKE
SSTUM32866
1D C1 R
QCKEA QCKEB(1)
DODT
1D C1 R
QODTA QODTB(1)
DCS
1D C1 R
QCSA QCSB(1)
CSR
D2
0 1 1D C1 R Q2A Q2B(1)
to 10 other channels (D3, D5, D6, D8 to D14)
002aad083
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUM32866; 1 : 2 Register A configuration with C0 = 0 and C1 = 1 (positive logic)
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
RESET CK CK LPS0 (internal node) D2, D3, D5, D6, D8 to D14 VREF
11
D CLK R D2, D3, D5, D6, D8 to D14
11
CE
D2, D3, D5, D6, 11 D8 to D14
11 11
Q2A, Q3A, Q5A, Q6A, Q8A to Q14A Q2B, Q3B, Q5B, Q6B, Q8B to Q14B
PARITY CHECK C1 0 D CLK R PAR_IN QERR 1 D CLK R CE D CLK R 1 PPO 0
C0
CLK 2-BIT COUNTER R
LPS1 (internal node)
0 D CLK R 1
002aaa650
Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUM32866EC/G
ball A1 SSTUM32866EC/S index area 123456 A B C D E F G H J K L M N P R T
002aad084
Transparent top view
Fig 3. Pin configuration for LFBGA96
1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 PAR_IN CK CK D8 D9 D10 D11 D12 D13 D14
2 PPO D15 D16 QERR D17 D18 RESET DCS CSR D19 D20 D21 D22 D23 D24 D25
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS n.c. Q8 Q9 Q10 Q11 Q12 Q13 Q14
6 DNU Q15 Q16 DNU Q17 Q18 C0 DNU n.c. Q19 Q20 Q21 Q22 Q23 Q24 Q25
002aab108
Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 PAR_IN CK CK D8 D9 D10 D11 D12 D13 D14
2 PPO DNU DNU QERR n.c. n.c. RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA n.c. Q8A Q9A Q10A Q11A Q12A Q13A Q14A
6 QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB n.c. Q8B Q9B Q10B Q11B Q12B Q13B Q14B
002aab109
Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1)
1 A B C D E F G H J K L M N P R T D1 D2 D3 D4 D5 D6 PAR_IN CK CK D8 D9 D10 DODT D12 D13 DCKE
2 PPO DNU DNU QERR DNU DNU RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA n.c. Q8A Q9A Q10A QODTA Q12A Q13A QCKEA
6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB n.c. Q8B Q9B Q10B QODTB Q12B Q13B QCKEB
002aab110
Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1)
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Product data sheet
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
6.2 Pin description
Table 3. Symbol GND Pin description Pin Type Description ground B3, B4, D3, D4, F3, F4, ground input H3, H4, K3, K4, M3, M4, P3, P4 A4, C3, C4, E3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 A3, T3 H1 J1 G6 G5 G2 J2 H2
[2]
VDD
1.8 V nominal
power supply voltage
VREF CK CK C0 C1 RESET CSR DCS D1 to D25 DODT DCKE PAR_IN Q1 to Q25, Q1A to Q14A, Q1B to Q14B PPO QCS, QCSA, QCSB QODT, QODTA, QODTB QCKE, QCKEA, QCKEB QERR n.c. DNU
0.9 V nominal differential input differential input LVCMOS inputs LVCMOS input SSTL_18 input SSTL_18 input SSTL_18 input SSTL_18 input SSTL_18 input 1.8 V CMOS outputs 1.8 V CMOS output 1.8 V CMOS output 1.8 V CMOS output 1.8 V CMOS output open-drain output -
input reference voltage positive master clock input negative master clock input Configuration control inputs; Register A or Register B and 1 : 1 mode or 1 : 2 mode select. Asynchronous reset input (active LOW). Resets registers and disables VREF data and clock. Chip select inputs (active LOW). Disables D1 to D25[1] outputs switching when both inputs are HIGH. Data input. Clocked in on the crossing of the rising edge of CK and the falling edge of CK. The outputs of this register bit will not be suspended by the DCS and CSR control. The outputs of this register bit will not be suspended by the DCS and CSR control. Parity input. Arrives one clock cycle after the corresponding data input. Data outputs that are suspended by the DCS and CSR control.[3] Partial parity out. Indicates odd parity of inputs D1 to D25.[1] Data output that will not be suspended by the DCS and CSR control. Data output that will not be suspended by the DCS and CSR control. Data output that will not be suspended by the DCS and CSR control. Output error bit (active LOW). Generated one clock cycle after the corresponding data output. Not connected. Ball present but no internal connection to the die. Do not use. Inputs are in standby-equivalent mode and outputs are driven LOW.
[2]
[2]
G1
[2]
A2
[2]
[2]
[2]
D2
[2]
[2]
[1]
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0. Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1. Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1. Depends on configuration. See Figure 4, Figure 5, and Figure 6 for ball number.
(c) NXP B.V. 2007. All rights reserved.
[2]
SSTUM32866_1
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
[3]
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0. Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1. Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
7. Functional description
The SSTUM32866 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity, designed for 1.7 V to 2.0 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18 specifications. The error (QERR) output is 1.8 V open-drain driver. The SSTUM32866 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The C0 input controls the pinout configuration for the 1 : 2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH). The SSTUM32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration, parity is checked on the PAR_IN input which arrives one cycle after the input data to which it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after the corresponding data inputs. When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the first device. The PPO and QERR signals are produced on the second device three clock cycles after the corresponding data inputs. The PPO output of the first register is cascaded to the PAR_IN of the second register. The QERR output of the first register is left floating and the valid error information is latched on the QERR output of the second register. If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity check computation. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level.
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn and PPO outputs will function normally. The RESET input has priority over the DCS and CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can be hard-wired to ground, in which case, the setup time requirement for DCS would be the same as for the other Dn data inputs. To control the low-power mode with DCS only, then the CSR input should be pulled up to VDD through a pull-up resistor. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the Qn outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUM32866 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output.
7.1 Function table
Table 4. Function table (each flip-flop) L = LOW voltage level; H = HIGH voltage level; X = don't care; = LOW-to-HIGH transition; = HIGH-to-LOW transition. Inputs RESET H H H H H H H H H H H H L
[1]
Outputs[1] CK CK L or H L or H L or H L or H X or floating Dn, DODTn, DCKEn L H X L H X L H X L H X X or floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L QCS L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L
DCS L L L L L L H H H H H H X or floating
CSR L L L H H H L L L H H H X or floating
L or H L or H L or H L or H X or floating
Q0 is the previous state of the associated output.
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
Table 5. Parity and standby function table L = LOW voltage level; H = HIGH voltage level; X = don't care; = LOW-to-HIGH transition; = HIGH-to-LOW transition. Inputs RESET H H H H H H H H H H L
[1] [2]
Outputs[1] CK L or H of inputs = H (D1 to D25) even odd even odd even odd even odd X X X or floating PAR_IN[2] L L H H L L H H X X X or floating PPO[3] L H H L L H H L PPO0 PPO0 L QERR[4] H L L H H L L H QERR0 QERR0 H
DCS L L L L H H H H H X
CSR X X X X L L L L H X
CK L or H
X or floating X or floating X or floating X or floating
PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR. Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0. Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1. Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1. PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies. This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
[3] [4]
8. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI VO IIK IOK IO IDDC Tstg Vesd Parameter supply voltage input voltage output voltage input clamping current output clamping current output current continuous current through each VDD or GND pin storage temperature electrostatic discharge voltage Human Body Model (HBM); 1.5 k; 100 pF Machine Model (MM); 0 ; 200 pF receiver driver VI < 0 V or VI > VDD VO < 0 V or VO > VDD continuous; 0 V < VO < VDD Conditions Min -0.5 -0.5[1] -0.5[1] -65 2 200 Max +2.5 +2.5[2] VDD + -50 50 50 100 +150 0.5[2] Unit V V V mA mA mA mA C kV V
[1] [2]
The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed. This value is limited to 2.5 V maximum.
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
9. Recommended operating conditions
Table 7. Symbol VDD Vref VT VI VIH(AC) VIL(AC) VIH(DC) VIL(DC) VIH VIL VICR VID IOH IOL Tamb Recommended operating conditions Parameter supply voltage reference voltage termination voltage input voltage AC HIGH-level input voltage AC LOW-level input voltage DC HIGH-level input voltage DC LOW-level input voltage HIGH-level input voltage LOW-level input voltage common mode input voltage range differential input voltage HIGH-level output current LOW-level output current ambient temperature operating in free air SSTUM32866EC/G SSTUM32866EC/S
[1] [2]
Conditions
Min 1.7 0.49 x VDD Vref - 0.040 0
Typ 0.50 x VDD Vref -
Max 2.0 0.51 x VDD Vref + 0.040 VDD Vref - 0.250 Vref - 0.125 0.35 x VDD 1.125 -8 8 70 85
Unit V V V V V V V V V V V mV mA mA C C
data (Dn), CSR, and PAR_IN inputs data (Dn), CSR, and PAR_IN inputs data (Dn), CSR, and PAR_IN inputs data (Dn), CSR, and PAR_IN inputs RESET, Cn RESET, Cn CK, CK CK, CK
[1] [1] [2]
Vref + 0.250 Vref + 0.125 0.65 x VDD 0.675 600 0 0
[2]
The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW.
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
10. Characteristics
Table 8. Characteristics At recommended operating conditions (see Table 7); unless otherwise specified. Symbol VOH VOL II IDD Parameter HIGH-level output voltage LOW-level output voltage input current supply current Conditions IOH = -6 mA; VDD = 1.7 V IOL = 6 mA; VDD = 1.7 V all inputs; VI = VDD or GND; VDD = 2.0 V static Standby mode; RESET = GND; IO = 0 mA; VDD = 2.0 V static Operating mode; RESET = VDD; IO = 0 mA; VDD = 2.0 V; VI = VIH(AC) or VIL(AC) IDDD dynamic operating current per clock only; RESET = VDD; MHz VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle; IO = 0 mA; VDD = 1.8 V per each data input, 1 : 1 mode; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle; IO = 0 mA; VDD = 1.8 V per each data input, 1 : 2 mode; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle; IO = 0 mA; VDD = 1.8 V Ci input capacitance data and CSR inputs; VI = Vref 250 mV; VDD = 1.8 V CK and CK inputs; VICR = 0.9 V; Vi(p-p) = 600 mV; VDD = 1.8 V RESET input; VI = VDD or GND; VDD = 1.8 V Zo output impedance instantaneous steady-state
[1] Instantaneous is defined as within < 2 ns following the output data transition edge.
[1]
Min 1.2 -
Typ -
Max 0.5 5 2 40
Unit V V A mA mA
-
16
-
A
-
11
-
A
-
19
-
A
2.5 2 3 -
7 53
3.5 3 4 -
pF pF pF
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
Table 9. Timing requirements At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.1. Symbol fclock tW tACT tINACT tsu Parameter clock frequency pulse width differential inputs active time differential inputs inactive time setup time DCS before CK, CK, CSR HIGH; CSR before CK, CK, DCS HIGH DCS before CK, CK, CSR LOW DODT, DCKE and data (Dn) before CK, CK PAR_IN before CK, CK th hold time DCS, DODT, DCKE and data (Dn) after CK, CK PAR_IN after CK, CK
[1] [2] [3] This parameter is not necessarily production tested. VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken HIGH. VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Conditions CK, CK HIGH or LOW
[1][2] [1][3]
Min 1 0.6 0.5 0.5 0.5 0.4 0.4
Typ -
Max 550 10 15 -
Unit MHz ns ns ns ns ns ns ns ns ns
Table 10. Switching characteristics At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.1. Symbol fmax tPDM tPD tLH tHL tPDMSS tPHL tPLH
[1] [2]
Parameter maximum input clock frequency peak propagation delay propagation delay LOW-to-HIGH delay HIGH-to-LOW delay simultaneous switching peak propagation delay HIGH-to-LOW propagation delay LOW-to-HIGH propagation delay
Conditions single bit switching; from CK and CK to Qn from CK and CK to PPO from CK and CK to QERR from CK and CK to QERR from CK and CK to Qn from RESET to Qn from RESET to PPO from RESET to QERR
[1][2] [1]
Min 550 1.0 0.5 1.2 1 -
Typ -
Max 1.4 1.7 3 2.4 1.5 3 3 3
Unit MHz ns ns ns ns ns ns ns ns
Includes 350 ps of test load transmission line delay. This parameter is not necessarily production tested.
Table 11. Data output edge rates At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.2. Symbol dV/dt_r dV/dt_f dV/dt_ Parameter rising edge slew rate falling edge slew rate Conditions from 20 % to 80 % from 80 % to 20 % Min 1 1 Typ Max 4 4 1 Unit V/ns V/ns V/ns
absolute difference between dV/dt_r from 20 % or 80 % and dV/dt_f to 80 % or 20 %
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
10.1 Timing diagrams
RESET
DCS
CSR
m CK
m+1
m+2
m+3
m+4
CK tsu D1 to D25 tPD CK to Q Q1 to Q25 tsu th th
PAR_IN tPD CK to PPO PPO tPD CK to QERR QERR
002aaa655
tPD CK to QERR
Fig 7. Timing diagram for SSTUM32866 used as a single device; C0 = 0, C1 = 0
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1.8 V DDR2-1G configurable registered buffer with parity
RESET
DCS
CSR
m CK
m+1
m+2
m+3
m+4
CK tsu D1 to D14 tPD CK to Q Q1 to Q14 tsu th th
PAR_IN tPD CK to PPO PPO tPD CK to QERR QERR (not used) tPD CK to QERR
002aaa656
Fig 8. Timing diagram for the first SSTUM32866 (1 : 2 Register A configuration) device used in pair; C0 = 0, C1 = 1
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SSTUM32866
1.8 V DDR2-1G configurable registered buffer with parity
RESET
DCS
CSR
m CK
m+1
m+2
m+3
m+4
CK tsu D1 to D14 tPD CK to Q Q1 to Q14 tsu th th
PAR_IN(1) tPD CK to PPO PPO (not used) tPD CK to QERR QERR
002aaa657
tPD CK to QERR
(1) PAR_IN is driven from PPO of the first SSTUM32866 device.
Fig 9. Timing diagram for the second SSTUM32866 (1 : 2 Register B configuration) device used in pair; C0 = 1, C1 = 1
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11. Test information
11.1 Parameter measurement information for data output load circuit
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified. The outputs are measured one at a time with one transition per measurement.
VDD DUT
50
CK inputs
CK CK test point
RL = 100
delay = 350 ps Zo = 50
RL = 1000
OUT
CL = 30 pF(1) RL = 1000
test point
002aaa371
(1) CL includes probe and jig capacitance.
Fig 10. Load circuit, data output measurements
LVCMOS RESET 0.5VDD tINACT IDD(1) 0.5VDD
VDD 0V tACT 90 % 10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 11. Voltage and current waveforms; inputs active and inactive times
tW VIH input VICR VICR VID VIL
002aaa373
VID = 600 mV. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 12. Voltage waveforms; pulse duration
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1.8 V DDR2-1G configurable registered buffer with parity
CK VICR CK tsu input Vref th VIH Vref VIL
002aaa374
VID
VID = 600 mV. Vref = 0.5VDD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; setup and hold times
CK VICR CK tPLH tPHL VOH output VT VOL 002aaa375 VICR Vi(p-p)
tPLH and tPHL are the same as tPD.
Fig 14. Voltage waveforms; propagation delay times (clock to output)
LVCMOS VIH RESET 0.5VDD VIL tPHL VOH output VT VOL 002aaa376
tPLH and tPHL are the same as tPD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 15. Voltage waveforms; propagation delay times (reset to output)
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11.2 Data output slew rate measurement information
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 50
OUT
CL = 10 pF(1)
test point
002aaa377
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, HIGH-to-LOW slew measurement
output 80 % dv_f 20 % dt_f
002aaa378
VOH
VOL
Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
CL = 10 pF(1)
test point
RL = 50
002aaa379
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, LOW-to-HIGH slew measurement
dt_r VOH 80 % dv_r 20 % output
002aaa380
VOL
Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
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1.8 V DDR2-1G configurable registered buffer with parity
11.3 Error output load circuit and voltage measurement information
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 1 k
OUT
CL = 10 pF(1)
test point
002aaa500
(1) CL includes probe and jig capacitance.
Fig 20. Load circuit, error output measurements
LVCMOS RESET 0.5VDD
VDD
0V tPLH VOH output waveform 2 0.15 V
0V
002aaa501
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET input.
timing inputs
VICR tHL
VICR
Vi(p-p)
VDD output waveform 1 0.5VDD
002aaa502
VOL
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs
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1.8 V DDR2-1G configurable registered buffer with parity
timing inputs
VICR tLH
VICR
Vi(p-p)
VOH output waveform 2 0.15 V
002aaa503
0V
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs
11.4 Partial parity out load circuit and voltage measurement information
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
DUT
OUT
CL = 5 pF(1)
test point
RL = 1 k
002aaa654
(1) CL includes probe and jig capacitance.
Fig 24. Partial parity out load circuit
CK VICR CK tPLH tPHL VOH output VT VOL 002aaa375 VICR Vi(p-p)
VT = 0.5VDD. tPLH and tPHL are the same as tPD. Vi(p-p) = 600 mV.
Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock inputs
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1.8 V DDR2-1G configurable registered buffer with parity
LVCMOS VIH RESET 0.5VDD VIL tPHL VOH output VT VOL 002aaa376
VT = 0.5VDD. tPLH and tPHL are the same as tPD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to RESET input
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1.8 V DDR2-1G configurable registered buffer with parity
12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
D
B
A
ball A1 index area
A E
A2 A1 detail X
e1
1/2 e
C
v M C A B
e T R P N M L K J H G F E D C B A ball A1 index area
y1 C
y
b
w M C
e
e2
1/2 e
123456 X 0 5 scale 10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 13.6 13.4 e 0.8 e1 4 e2 12 v 0.15 w 0.1 y 0.1 y1 0.2
OUTLINE VERSION SOT536-1
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 00-03-04 03-02-05
Fig 27. Package outline SOT536-1 (LFBGA96)
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13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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1.8 V DDR2-1G configurable registered buffer with parity
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28.
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1.8 V DDR2-1G configurable registered buffer with parity
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 14. Acronym CMOS DDR DIMM DUT LVCMOS PPO PRR RDIMM SSTL Abbreviations Description Complementary Metal Oxide Semiconductor Double Data Rate Dual In-line Memory Module Device Under Test Low Voltage Complementary Metal Oxide Semiconductor Partial Parity Out Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic
15. Revision history
Table 15. Revision history Release date 20070629 Data sheet status Product data sheet Change notice Supersedes Document ID SSTUM32866_1
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16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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1.8 V DDR2-1G configurable registered buffer with parity
18. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 8 9 10 10.1 11 11.1 11.2 11.3 11.4 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 8 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Recommended operating conditions. . . . . . . 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 17 Parameter measurement information for data output load circuit . . . . . . . . . . . . . . . . . . 17 Data output slew rate measurement information . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Error output load circuit and voltage measurement information . . . . . . . . . . . . . . . . 20 Partial parity out load circuit and voltage measurement information . . . . . . . . . . . . . . . . 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Introduction to soldering . . . . . . . . . . . . . . . . . 24 Wave and reflow soldering . . . . . . . . . . . . . . . 24 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Contact information. . . . . . . . . . . . . . . . . . . . . 27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
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