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| GSG Gunter Semiconductor GmbH TFB3869 EDITION 09/00 One Chip Subscriber Line Interface (SLIC) For inquiry please contact : China Tel: 0086-755-3200442 Fax: 0086-755-3355520 Hong Kong Tel : 00852-26190748 Fax: 00852-24948080 e-mail sales@gsg-asia.com Edition 09/00 Subscriber Line Interface Circuit (SLIC) Features * High balance without external precession devices * Low supply current * Direct coupling with standard CODECs * Subscriber feeding by integrated constant current sources * Programmable constant current by external resistor * Hybrid function, programmable via external components * Logic output for ground key detection * Logic output for loop current detection Package * SOP 20 0.1 2.30 + 0.05 - 12.85 0.1 10.4 0.2 7.4 + 0.2 2.65 0...10 0.2 0.1 0.15 0.42 0.07 0.82 1.27 0.25 M 0.3 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 09/00 0.27 +0.05 -0.04 1 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - HK n. c. ISET ZOUT ZIN ET LD LA n. c. VBAT LB n. c. GND n.c. +CR -CR +MIC - MIC VCC +HK Negative output for transmitter direction This pin is internally used. It is not permitted to connect any external components. Control input for loop current Output, network for hybrid function Input, network for hybrid funktion Output, ground key detection Output, loop current detection Line output This pin is internally used. It is not permitted to connect any external components. Negative supply voltage Line output This pin is internally used. It is not permitted to connect any external components. Ground This pin is internally used. It is not permitted to connect any external components. External capacitor for AC/DC selction External capacitor for AC/DC selction Positive input for receive direction Negative input for receive direction Positive supply voltage Positive output for transmitter direction Pin Description VBAT VCC GND ISET Supply voltage -24 V Supply voltage +5 V Ground Control input for loop current Voltage drop on grounded resistor of 23,3 V. 23.3 V Subscriber line, ILA/LB = 120 (ISET) = 120 . R SET The subscriber line current is determined by the ISET current. +MIC; -MIC Differential input for the receive direction The input resistance is 10 k per pin, the output voltage in receive direction line is four times the MIC voltage. Differential output for the transmitter direction with unit gain of the input signal of the subscriber line with common mode offset voltage of + 2.5 V Current node input for hybrid amplifier ZNB = 50 (sum) Driver output for hybrid function Logic output for ground key detection (low-aktiv) Logic output for loop current detection (low-aktiv) External capacitor for hybrid function LA, LB +HK; -HK ZIN ZOUT ET LD +CR; -CR All Pin are ESD protected except PIN 2, 9, 12 and 14. 2 09/00 TFB3869T Pin 1 Symbol -HK Circuit Pin 7 VCC Symbol LD Circuit VCC -HK LD GND VBAT 3 ISET 8 LA 8 LA VBAT 3 ISET VBAT 4 ZOUT 11 LB GND LB VBAT 4 ZOUT 11 5 ZIN 17 18 +MIC - MIC +MIC -MIC GND VBAT 5 ZIN VBAT 6 ET VCC 20 +HK VCC ET +HK VBAT GND 09/00 TFB3869T 3 Block Diagram Hybrid-C +5V 19 VCC 15 16 - CR 6 ET 7 LD 13 GND x + CR x LB 11 20 CODEC TRANSMIT 1 +5 V +HK -HK VBAT 2 x LA 8 17 + MIC TFB 3869 T 18 CODEC RECEIVER - MIC ISET 3 RSET ZOUT 4 ZIN 5 x VBAT 10 - 24 V IMITATION LINE IMPEDANCE Absolute Maximum Ratings Absolute maximum ratings Ta = 0C up to 70C Positive supply voltage Negative supply voltage All other pins Junction temperature Tj Symbol Min. Max. Unit +5V -24V 0 -25.25 Pin10 - 0.3 - 5.25 0 Pin19 + 0.3 150 V V V C 4 09/00 TFB3869T Electrical Characteristics DC Characteristics VBAT = -24 V, VCC = +5 V, Ta = 25 C Parameter Supply current Loop current Supply current Symmetrical voltage Biaspoint +HK Biaspoint -HK Offset HK LD-detection (low) ILD = 200 A LD-detection (high) VLD = 5 V ET-detection (low) IET = 200 A ET-detection (high) VET = 5 V Symbol ICC ISCHL IBAT-ISCHL VSYM V+HK V-HK V+HK - V-HK VLD Min. 20 -3 11 2 2 -250 - Max. 1.0 24 13 3 3 250 0.4 Unit mA mA mA V V V mV V ILD - 2 A VET - 0.4 V IET - 2 A AC Characteristics VBAT = -24 V, VCC = +5 V, Ta = 25 C Parameter Balance two wire Balance two wire to four wire Loss MIC/HK Gain for receiver direction Gain for transmitter direction Symbol a2-2 a2-4 aMIC/HK GR GT Min. 54 58 12 10.5 -7.5 Max. 13.5 -4.5 Unit dB dB dB dB dB 09/00 TFB3869T 5 Application Circuit +5V MIC 10k 10k 20 +HK 19 VCC 18 -MIC 17 +MIC 16 -CR 10 15 +CR 14 N.C. 13 GND 12 N.C. LB 11 221 LB HK TFB 3869 T -HK 1 N.C. 2 120k 5.4k 4.7n ET LD - 24V ISET 3 ZOUT 4 ZIN 5 20k ET 6 LD 7 LA 8 N.C. 9 VBAT 115n 909 10 10 LA Test Circuit, Base Block MIC +5V 10k 10k 20 +HK 19 VCC 18 -MIC 17 +MIC 16 -CR 10 15 +CR 14 N.C. 13 GND 12 N.C. LB 11 221 LB 1:1 HK TFB 3869 T -HK 1 N.C. 2 120k 5.4k 4.7n ET LD -24V ISET 3 ZOUT 4 ZIN 5 20k ET 6 LD 7 LA 8 N.C. 9 VBAT 115n 909 10 10 LA 6 09/00 TFB3869T Test Circuit, Balance, Two Wire LB 300 10 ~ EL VL 300 base block LA a 2-2 = 20 log EL VL Balance two wire a2-2 80 a2 - 2 ( dB ) 60 50 40 30 20 0.1 0.2 0.3 0.6 1 2 3 6 10 f ( kHz ) 09/00 TFB3869T 7 Test Circuit, Balance Two Wire To Four Wire LB +HK 300 10 5k VHK -HK base block LA 300 ~ EL a 2-4 = 20 log EL VHK Balance two wire to four wire a2-4 80 a2 - 4 ( dB ) 60 50 40 30 20 0.1 0.2 0.3 0.6 1 2 3 6 10 f ( kHz ) 8 09/00 TFB3869T Test Circuit, Return Loss LB MIC 221 ~ EMIC 909 base block +HK -HK LA 115 n aR = 20 log E MIC VHK 5k VHK Return loss aR 0 aR ( dB ) 10 15 20 25 30 35 40 0.1 0.2 0.3 0.6 1 2 3 6 10 f ( kHz ) 09/00 TFB3869T 9 Test Circuit, Receiver Gain LB MIC 221 ~ EMIC 909 base block LA 115 n Va/b GR = Va / b E MIC Receiver gain GR 14 GR ( dB ) 12 11 10 9 8 7 6 0.1 0.2 0.3 0.6 1 2 3 6 10 f ( kHz ) 10 09/00 TFB3869T Test Circuit, Transmitter Gain LB +HK 221 5k VHK -HK base block LA 909 115 n ~ Ea/b GT = VHK Ea/b Transmitter gain GT -4 GT ( dB ) -5 -5.5 -6 -6.5 -7 -7.5 -8 0.1 0.2 0.3 0.6 1 2 3 6 10 f ( kHz ) 09/00 TFB3869T 11 Loop Conditions Loop conditions Loop connected, no gound key Loop connected, ground key aktiv Loop disconnected, no ground key LD High High Low ET High Low High Loop Detection Condition for switching of the logic output LD: ISCHL * RL = VBAT - 5V Status of the logic output LD depending on loop current: LD = Low ISCHL * RL > VBAT - 5V LD = High ISCHL * RL < VBAT - 5V Loop Resistance The useable loop resistance can be calculated as follows: RL < (VBAT - 5V) ISCHL RL < (VBAT - 5V) RSET 120 * 23.3V * In accordance with the conditions menioned above a reliable loop detection will be guaranteed for a closed loop resistance value lower than 815 . 12 09/00 TFB3869T Ground Key Detection For ground key detection the LA or LB outputs have to be connected to ground. In this case the voltage drop on an internal differential amplifier reaches 1 V in minimum for switching the ET output from high to low. Protection Circuit GND < 1n 13 GND 8 LB a < 1n TFB 3869 T 11 LA b V BAT 10 V BAT |
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