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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
PO54G74A, PO74G74A
10/10/07
54, 74 Series GHz Logic
FEATURES:
. Patented technology . Specified From -40C to 85C, -40C to 125C, and -55C to 125C . Operating frequency is faster than 600MHz . VCC Operates from 1.65V to 3.6V . Propagation delay < 2ns max with 15pf load . Low input capacitance: 4pf typical . Latch-Up Performance Exceeds 250 mA Per JESD 17 . ESD Protection Exceeds JESD 22 . 5000-VHuman-BodyModel (A114-A) . 200-VMachineModel (A115-A) . Available in 14pin 150mil wide SOIC package . Available in 14pin Ceramic Dual Flatpack . Available in 20pin Leadless Ceramic Chip Carrier
DESCRIPTION:
Potato Semiconductor's PO74G74A is designed for world top performance using submicron CMOS technology to achieve higher than 600MHz TTL /CMOS output frequency with less than 2ns propagation delay. This dual D flip-flop is designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment.
Pin Configuration
1CLR NC VCC
1CLR 1D 1CLK 1PRE 1Q 1Q GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 2CLR 2D 2CLK 2PRE 2Q 2Q
1CLK NC 1PRE NC 1Q
4 5 6 7 8
3
2 1 20 19 18 17 16 15
2CLR 2D NC 2CLK NC 2PRE
14 Vcc 2CLR 2D 2CLK 2PRE 2Q 2Q 13 12 11 10 9 8
1Q GND NC
Q L H H L H Q0
1PRE 1Q 1Q GND 4 5 6 CLR 7 D PRE 1D 1CLR 1CLR 1 2 3 D PRE
1D
14 9 10 11 12 13
Pin Description
INPUTS PRE L H L H H H CLR H L L H H H CLK X X X L D X X X H L X OUTPUTS Q H L H H L Q0
Logic Block Diagram
1
CLR
2
2Q 2Q
Q Q Q Q
1
Copyright (c) Potato Semiconductor Corporation
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
PO54G74A, PO74G74A
10/10/07
54, 74 Series GHz Logic
Maximum Ratings
Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -55 to 125 -0.5 to +4.6 -0.5 to +5.5 -0.5 to Vcc+0.5 Unit C C V V V Note:
stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied.
DC Electrical Characteristics
Symbol Description
Output High voltage Output Low voltage Input High voltage Input Low voltage Input High current Input Low current Clamp diode voltage
Test Conditions
Vcc=3V Vin=VIH or VIL, IOH= -12mA Vcc=3V Vin=VIH or VIL, IOH=12mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vin = 5.5V Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA
Min
Typ
Max
Unit
VOH VOL VIH VIL IIH IIL VIK
Notes:
1. 2. 3. 4. 5.
2.4 2 -0.5 -
3 0.3 -0.7
0.5 5.5 0.8 1 -1 -1.2
V V V V uA uA V
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 C ambient.
This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc - 0.6V at rated current
2
Copyright (c) Potato Semiconductor Corporation
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
PO54G74A, PO74G74A
10/10/07
54, 74 Series GHz Logic
Power Supply Characteristics
Symbol Description
Quiescent Power Supply Current
Test Conditions (1)
Vcc=Max, Vin=Vcc or GND
Min
Typ
Max
Unit
IccQ
Notes:
1. 2. 3. 4.
-
0.1
40
uA
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Capacitance
Parameters (1) Description
Input Capacitance Output Capacitance
Test Conditions
Vin = 0V Vout = 0V
Typ
Unit
Cin Cout
Notes:
4 6
pF pF
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol Description
Setup time before CLK Hold time, data after CLK Propagation Delay CLK to Q Propagation Delay CLK to Q Rise/Fall Time Input Frequency CL = 15pF CL = 15pF 0.8V - 2.0V CL=2pF - 15pF
Test Conditions (1)
M ax
tsu th tPLH tPHL tr/tf fmax
Notes:
-
Min
Unit
0.5 0.5
ns ns ns ns ns MHz
2 2 0.8
-
600
1. See test circuits and waveforms. 2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 500MHz
3
Copyright (c) Potato Semiconductor Corporation
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
PO54G74A, PO74G74A
10/10/07
54, 74 Series GHz Logic
Test Waveforms
VI Timing Input tw VI Input VM VM 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tsu VM th VI VM 0V VM 0V
VI Input tPLH Output tPHL Output VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
Output Control tPZL
VI VM VM 0V tPLZ VLOAD/2 VM tPZH VOL + V tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL
Output Waveform 1 S1 at V LOAD (see Note B) Output Waveform 2 S1 at GND (see Note B)
Test Circuit
Vcc
Pulse Generator
D.U.T
50
15pF to 2pF
4
Copyright (c) Potato Semiconductor Corporation
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
PO54G74A, PO74G74A
10/10/07
54, 74 Series GHz Logic
Packaging Mechanical Drawing: 14 pin 150mil SOIC
0.244 6.20 0.228 5.80
0.010 0.007 0.25 0.17
0.050 1.27 0.016 0.40
X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX
Packaging Mechanical Drawing: 14pin Leadless Ceramic Chip Carrier
X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX
5
Copyright (c) Potato Semiconductor Corporation
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
PO54G74A, PO74G74A
10/10/07
54, 74 Series GHz Logic
Packaging Mechanical Drawing: 20pin Ceramic Dual Flatpack
0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.080 (2,03) 0.064 (1,63)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
3
2
1
13
12
4 0.358 (9,09) 0.342 (8,69) 5 6 0.358 (9,09) 7 0.307 (7,80) 8
18 17 16 15 14
X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX
9
10
11
12
13
Ordering Information
Ordering Code
PO74G74ASU PO74G74ASR PO74G74ASiU PO74G74ASIR PO54G74ALU PO54G74AFU 14pin SOIC 14pin SOIC 14pin SOIC 14pin SOIC
14pin Leadless Ceramic Chip Carrier 20pin Ceramic Dual Flatpack
Package
Tube Tape and reel Tube Tape and reel Tube Tube Pb-free & Green Pb-free & Green Pb-free & Green Pb-free & Green Pb-free & Green Pb-free & Green
Top-Marking
PO74G74AS PO74G74AS PO74G74ASi PO74G74ASi PO54G74AL PO54G74AF
TA -40C to 85C -40C to 85C -40C to 125 C -40C to 125 C -55C to 125 C -55C to 125 C
IC Package Information
PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE
S L F
SOIC 14 LCCC 20 CFP 14
16 N/A N/A
8 N/A N/A
Top Left Corner N/A N/A
39 (12") N/A N/A
3000 N/A N/A
64 (20") N/A N/A
55 55 150
6
Copyright (c) Potato Semiconductor Corporation

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