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Multiphase PWM Regulator for IMVP-6.5TM Mobile CPUs and GPUs
ISL62883C
The ISL62883C is a multiphase PWM buck regulator for miroprocessor or graphics processor core power supply. The multiphase buck converter uses interleaved phase to reduce the total output voltage ripple with each phase carrying a portion of the total load current, providing better system performance, superior thermal management, lower component cost, reduced power dissipation, and smaller implementation area. The ISL62883C uses two integrated gate drivers and an external gate driver to provide a complete solution. The PWM modulator is based on Intersil's Robust Ripple Regulator (R3) technologyTM. Compared with traditional modulators, the R3TM modulator commands variable switching frequency during load transients, achieving faster transient response. With the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. The ISL62883C can be configured as CPU or graphics Vcore controller and is fully compliant with IMVP-6.5TM specifications. It responds to PSI# and DPRSLPVR signals by adding or dropping PWM3 and Phase 2 respectively, adjusting overcurrent protection threshold accordingly, and entering/exiting diode emulation mode. It reports the regulator output current through the IMON pin. It senses the current by using either discrete resistor or inductor DCR whose variation over temperature can be thermally compensated by a single NTC thermistor. It uses differential remote voltage sensing to accurately regulate the processor die voltage. The adaptive body diode conduction time reduction function minimizes the body diode conduction loss in diode emulation mode. User-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress. In 2-Phase configuration, the ISL62883C offers the FB2 function to optimize 1-Phase performance.
ISL62883C
Features
* Programmable 1, 2- or 3-Phase CPU or GPU Mode of Operation * Precision Multiphase Core Voltage Regulation - 0.5% System Accuracy Over-Temperature - Enhanced Load Line Accuracy * Microprocessor Voltage Identification Input - 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps - Supports VID Changes On-The-Fly * Supports Multiple Current Sensing Methods - Lossless Inductor DCR Current Sensing - Precision Resistor Current Sensing * * * * * * * * Supports PSI# and DPRSLPVR modes Superior Noise Immunity and Transient Response Current Monitor and Thermal Monitor Differential Remote Voltage Sensing High Efficiency Across Entire Load Range Two Integrated Gate Drivers Excellent Dynamic Current Balance FB2 Function Optimizes 1-Phase Mode Performance
* Adaptive Body Diode Conduction Time Reduction * User-selectable Overshoot Reduction Function * Small Footprint 40 Ld 5x5 TQFN Packages * Pb-Free (RoHS Compliant)
Applications*(see page 42)
* Notebook Core Voltage Regulator * Notebook GPU Voltage Regulator
Related Literature*(see page 42)
* See AN1460 for ISL62883/ISL62883C Evaluation Board Application Note "ISL62883EVAL2Z User Guide"
Load Line Regulation
1.10 1.08 1.06 1.04 VOUT (V) 1.02 1.00 0.98 0.96 0.94 0.92 0 5 10 15 20 25 30 35 40 IOUT (A) 45 50 55 60 65 VIN = 8V VIN = 12V VIN = 19V
March 18, 2010 FN7557.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL62883C
Ordering Information
PART NUMBER (Note 3) ISL62883CIRTZ (Note 2) ISL62883CIRTZ-T (Notes 1, 2) ISL62883CHRTZ (Note 2) ISL62883CHRTZ-T (Notes 1, 2) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62883C. For more information on MSL please see techbrief TB363. PART MARKING 62883C IRTZ 62883C IRTZ 62883C HRTZ 62883C HRTZ TEMP. RANGE (C) -40 to +100 -40 to +100 -10 to +100 -10 to +100 PACKAGE (Pb-Free) 40 Ld 5x5 TQFN 40 Ld 5x5 TQFN 40 Ld 5x5 TQFN 40 Ld 5x5 TQFN PKG. DWG. # L40.5x5 L40.5x5 L40.5x5 L40.5x5
Pin Configuration
ISL62883C (40 LD TQFN) TOP VIEW
CLK_EN# DPRSLPVR VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
40 39 38 37 36 35 34 33 32 31 PGOOD 1 PSI# 2 RBIAS 3 VR_TT# 4 NTC 5 VW 6 COMP 7 FB 8 ISEN3/FB2 9 ISEN2 10 11 12 13 14 15 16 17 18 19 20 ISUM+ BOOT1 UGATE1 ISEN1 VDD ISUMIMON VSEN RTN VIN GND PAD (BOTTOM) 30 BOOT2 29 UGATE2 28 PHASE2 27 VSSP2 26 LGATE2 25 VCCP 24 PWM3 23 LGATE1 22 VSSP1 21 PHASE1
2
VID0
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ISL62883C
Functional Pin Descriptions
ISL62883C 1 2 3 SYMBOL GND PGOOD PSI# RBIAS DESCRIPTION Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. Power-Good open-drain output indicating when the regulator is able to supply regulated voltage. Pull up externally with a 680 resistor to VCCP or 1.9k to 3.3V. Low load current indicator input. When asserted low, indicates a reduced load-current condition. A resistor to GND sets internal current reference. Use 147k or 47k. The choice of Rbias value, together with the ISEN2 pin configuration and the external resistance from the COMP pin to GND, programs the controller to enable/disable the overshoot reduction function and to select the CPU/GPU mode. Thermal overload output indicator. Thermistor input to VR_TT# circuit. A resistor from this pin to COMP programs the switching frequency (8k gives approximately 300kHz). This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the overcurrent threshold. This pin is the inverting input of the error amplifier. When the ISL62883C is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual current sensing for phase 3. When the ISL62883C is configured in 2-phase mode, this pin is FB2. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is off in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase mode to achieve optimum performance. Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will disable Phase 2. Individual current sensing for phase 1. Remote core voltage sense input. Connect to microprocessor die. Remote voltage sensing return. Connect to ground at microprocessor die. Droop current sense input. 5V bias power. Battery supply voltage, used for feed-forward. An analog output. IMON outputs a current proportional to the regulator output current. Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot diode. Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the Phase-1 high-side MOSFET. Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase-1. Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1 lowside MOSFETs. Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the Phase-1 low-side MOSFET. PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase-3 and allow other phases to operate.
4 5 6 7 8 9
VR_TT# NTC VW COMP FB INSE3/FB2
10 11 12 13 14, 15 16 17 18 19
ISEN2 ISEN1 VSEN RTN ISUM- and ISUM+ VDD VIN IMON BOOT1
20 21
UGATE1 PHASE1
22
VSSP1
23 24
LGATE1 PWM3
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ISL62883C
Functional Pin Descriptions (Continued)
ISL62883C 25 26 27 SYMBOL VCCP LGATE2 VSSP2 DESCRIPTION Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1F of an MLCC capacitor to VSSP1 and VSSP2 pins respectively. Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the Phase-2 low-side MOSFET. Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2 pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET. Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase-2. Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the Phase-2 high-side MOSFET. Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot diode. VID input with VID0 = LSB and VID6 = MSB. Voltage regulator enable input. A high level logic signal on this pin enables the regulator. Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor is in deeper sleep mode. Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is within 10% of Vboot. The bottom pad of ISL62883C is electrically connected to the GND pin inside the IC.It should also be used as the thermal pad for heat removal.
28
PHASE2
29 30
UGATE2 BOOT2
31 thru 37 38 39 40 pad
VID0 thru VID6 VR_ON DPRSLPVR CLK_EN# BOTTOM
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ISL62883C
Block Diagram
VIN VSEN ISEN1 ISEN3 ISEN2 PGOOD CLK_EN# 6A 54A 1.20V MODE CONTROL IBAL2 IBAL3 IBAL1 CURRENT BALANCE IBAL PROTECTION VID0 VID1 VID2 VID3 VID4 VID5 VID6 + RTN FB COMP VW + VIN DAC AND SOFTSTART IBAL2 VIN VDAC WOC OC MODULATOR CLOCK VDAC COMP VW IBAL3 VIN VDAC MODULATOR + _ E/A COMP PWM CONTROL LOGIC DRIVER COMP FLT PWM CONTROL LOGIC DRIVER PGOOD & CLK_EN# LOGIC 1.24V NTC BOOT2 UGATE2 PHASE2 SHOOT-THROUGH PROTECTION VDD
VR_ON PSI# DPRSLPVR RBIAS
VR_TT#
DRIVER
LGATE2 VSSP2 PWM3 BOOT1 UGATE1 PHASE1
IBAL1 VIN VDAC MODULATOR + _ 2.5X + _ CURRENT SENSE + _ WOC COMP 60A
IDROOP IMON
SHOOT-THROUGH PROTECTION VCCP DRIVER LGATE1 VSSP1
IMON ISUM+ ISUM-
CURRENT COMPARATORS NUMBER OF OC PHASES GAIN SELECT
+
+
ADJ. OCP THRESHOLD
COMP
GND
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ISL62883C
Table of Contents
Ordering Information ......................................................................................................................... 2 Pin Configuration ................................................................................................................................ 2 Functional Pin Descriptions ................................................................................................................ 3 Block Diagram .................................................................................................................................... 5 Table of Contents ............................................................................................................................... 6 Absolute Maximum Ratings ................................................................................................................ 7 Thermal Information .......................................................................................................................... 7 Recommended Operating Conditions .................................................................................................. 7 Electrical Specifications ...................................................................................................................... 7 Gate Driver Timing Diagram ............................................................................................................. 10 Simplified Application Circuits .......................................................................................................... 10 Theory of Operation .......................................................................................................................... 13 Diode Emulation and Period Stretching ............................................................................................... 14 Start-up Timing .............................................................................................................................. 15 Voltage Regulation and Load Line Implementation ............................................................................... 15 Differential Sensing ......................................................................................................................... 17 Phase Current Balancing .................................................................................................................. 18 Modes of Operation ......................................................................................................................... 20 Dynamic Operation .......................................................................................................................... 20 Protections ..................................................................................................................................... 21 FB2 Function .................................................................................................................................. 22 Adaptive Body Diode Conduction Time Reduction ................................................................................. 22 Overshoot Reduction Function ........................................................................................................... 22 Key Component Selection ................................................................................................................. 23 RBIAS ............................................................................................................................................ Inductor DCR Current-Sensing Network ............................................................................................. Resistor Current-Sensing Network .................................................................................................... Overcurrent Protection..................................................................................................................... Current Monitor .............................................................................................................................. Compensator .................................................................................................................................. Optional Slew Rate Compensation Circuit For 1-Tick VID Transition ........................................................ Voltage Regulator Thermal Throttling ................................................................................................. Current Balancing ........................................................................................................................... 23 23 25 25 26 27 29 30 30
Layout Guidelines ............................................................................................................................. 30 1-PHASE GPU Application Reference Design Bill of Materials ............................................................ 34 2-PHASE CPU Application Reference Design Bill of Materials ............................................................ 35 Typical Performance ......................................................................................................................... 37 Products ........................................................................................................................................... 42 Package Outline Drawing ................................................................................................................. 43
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Absolute Maximum Ratings
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . .-0.3V to +7V Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . +28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT-PHASE) . . . . -0.3V to +7V(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns) Phase Voltage (PHASE) . . . . . -7V (<20ns Pulse Width, 10J) UGATE Voltage (UGATE) . . . . . . . PHASE-0.3V (DC) to BOOT . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10J) to BOOT LGATE Voltage . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5J) to VDD+0.3V All Other Pins. . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Open Drain Outputs, PGOOD, VR_TT#, CLK_EN# . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 40 Ld TQFN Package (Notes 4, 5). . 31 2 Maximum Junction Temperature . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . -65C to +150C Maximum Junction Temperature (Plastic Package). . . +150C Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . Battery Voltage, VIN . Ambient Temperature ISL62883CHRTZ. . . ISL62883CIRTZ . . . Junction Temperature ISL62883CHRTZ. . . ISL62883CIRTZ . . . . . . . . . . . . . . . . . . . . . . . +5V 5% . . . . . . . . . . . . . . . . . . +4.5V to 25V . . . . . . . . . . . . . . . -10C to +100C . . . . . . . . . . . . . . . -40C to +100C . . . . . . . . . . . . . . . -10C to +125C . . . . . . . . . . . . . . . -40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +100C. SYMBOL IVDD IVIN RVIN PORr PORf TEST CONDITIONS VR_ON = 1V VR_ON = 0V VR_ON = 0V VR_ON = 1V VDD rising VDD falling No load; closed loop, active mode range VID = 0.75V to 1.50V, VID = 0.5V to 0.7375V VID = 0.3V to 0.4875V IRTZ %Error (VCC_CORE) No load; closed loop, active mode range VID = 0.75V to 1.50V VID = 0.5V to 0.7375V VID = 0.3V to 0.4875V 4.00 900 4.35 4.15 4.5 MIN (Note 6) TYP 4 MAX (Note 6) 4.6 1 1 UNITS mA A A k V V
PARAMETER INPUT POWER SUPPLY +5V Supply Current Battery Supply Current VIN Input Resistance Power-On-Reset Threshold SYSTEM AND REFERENCES System Accuracy
HRTZ %Error (VCC_CORE)
-0.5 -8 -15
+0.5 +8 +15
% mV mV
-0.8 -10 -18 1.0945 1.0912 1.100 1.100 1.500 0.300 1.45 1.47
+0.8 +10 +18 1.1055 1.1088
% mV mV V V V V
VBOOT Maximum Output Voltage Minimum Output Voltage RBIAS Voltage
ISL62883CHRTZ ISL62883CIRTZ VCC_CORE(max) VID = [0000000] VCC_CORE(min) VID = [1100000] RBIAS = 147k
1.49
V
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ISL62883C
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +100C. (Continued) SYMBOL fSW(nom) TEST CONDITIONS Rfset = 7k, 3-channel operation, VCOMP = 1V MIN (Note 6) 285 200 IFB = 0A Av0 GBW CL = 20pF -0.15 90 18 TYP 300 MAX (Note 6) 315 500 +0.15 UNITS kHz kHz mV dB MHz
PARAMETER CHANNEL FREQUENCY Nominal Channel Frequency Adjustment Range AMPLIFIERS Current-Sense Amplifier Input Offset Error Amp DC Gain (Note 7) Error Amp Gain-Bandwidth Product (Note 7) ISEN Imbalance Voltage Input Bias Current
Maximum of ISENs - Minimum of ISENs 20 VOL IOH tpgd RUGPU IUGSRC RUGPD IUGSNK RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR VF IR OVH OVHS IPGOOD = 4mA PGOOD = 3.3V CLK_ENABLE# LOW to PGOOD HIGH -1 6.3 7.6 0.26
1
mV nA
POWER-GOOD AND PROTECTION MONITORS PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay GATE DRIVER UGATE Pull-Up Resistance (Note 7) UGATE Source Current (Note 7) UGATE Sink Resistance (Note 7) UGATE Sink Current (Note 7) LGATE Pull-Up Resistance (Note 7) LGATE Source Current (Note 7) LGATE Sink Resistance (Note 7) LGATE Sink Current (Note 7) UGATE to LGATE Deadtime LGATE to UGATE Deadtime BOOTSTRAP DIODE Forward Voltage Reverse Leakage PROTECTION Overvoltage Threshold Severe Overvoltage Threshold OC Threshold Offset at Rcomp = Open Circuit VSEN rising above setpoint for >1ms VSEN rising for >2s 3-phase configuration, ISUM- pin current 2-phase configuration, ISUM- pin current 1-phase configuration, ISUM- pin current Current Imbalance Threshold Undervoltage Threshold UVf One ISEN above another ISEN for >1.2ms VSEN falling below setpoint for >1.2ms -355 150 1.525 28.4 18.3 8.2 195 1.55 30.3 20.2 10.1 9 -295 -235 240 1.575 32.2 22.1 12.0 mV V A A A mV mV PVCC = 5V, IF = 2mA VR = 25V 0.58 0.2 V A 200mA Source Current UGATE - PHASE = 2.5V 250mA Sink Current UGATE - PHASE = 2.5V 250mA Source Current LGATE - VSSP = 2.5V 250mA Sink Current LGATE - VSSP = 2.5V UGATE falling to LGATE rising, no load LGATE falling to UGATE rising, no load 1.0 2.0 1.0 2.0 1.0 2.0 0.5 4.0 23 28 0.9 1.5 1.5 1.5 A A A A ns ns 0.4 1 8.9 V A ms
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ISL62883C
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +100C. (Continued) SYMBOL VIL VIH VIH VID0-VID6, PSI#, and DPRSLPVR Input Low VID0-VID6, PSI#, and DPRSLPVR Input High PWM PWM3 Output Low PWM3 Output High PWM Tri-State Leakage THERMAL MONITOR NTC Source Current Over-Temperature Threshold VR_TT# Low Output Resistance CLK_EN# OUTPUT LEVELS CLK_EN# Low Output Voltage CLK_EN# Leakage Current CURRENT MONITOR IMON Output Current IIMON ISUM- pin current = 20A ISUM- pin current = 10A ISUM- pin current = 5A IMON Clamp Voltage Current Sinking Capability INPUTS VR_ON Leakage Current VIDx Leakage Current PSI# Leakage Current DPRSLPVR Leakage Current SLEW RATE Slew Rate (For VID Change) NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits established by characterization and are not production tested. SR 5 6.5 mV/s IVR_ON IVIDx IPSI# IDPRSLPVR VR_ON = 0V VR_ON = 1V VIDx = 0V VIDx = 1V PSI# = 0V PSI# = 1V DPRSLPVR = 0V DPRSLPVR = 1V -1 -1 -1 -1 0 0 0 0.45 0 0.45 0 0.45 1 1 1 1 A A A A A A A A VIMONCLAMP 114 54 25.5 120 60 30 1.1 275 126 66 34.5 1.15 A A A V A VOL IOH I = 4mA CLK_EN# = 3.3V -1 0.26 0.4 1 V A RTT NTC = 1.3V V (NTC) falling I = 20mA 53 1.18 60 1.2 6.5 67 1.22 9 A V V0L V0H Sinking 5mA Sourcing 5mA PWM = 2.5V 3.5 2 1.0 V V A VIL VIH 0.7 ISL62883CHRTZ ISL62883CIRTZ 0.7 0.75 0.3 TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) 0.3 UNITS V V V V V
PARAMETER LOGIC THRESHOLDS VR_ON Input Low VR_ON Input High
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ISL62883C
Gate Driver Timing Diagram
PWM
tLGFUGR
tRU 1V
tFU
UGATE
LGATE tFL
1V tRL
tUGFLGR
Simplified Application Circuits
V+5 Rbias Rntc
o
V+5
Vin
V+5
VCC UGATE FCCM PHASE
Vin L3
VDD VCCP VIN RBIAS PWM3 ISEN3 BOOT2 UGATE2 PHASE2 LGATE2 VSSP2
ISL6208
C
NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset
PWM
BOOT LGATE GND
Rs3 Cs3 L2 Vo
PGOOD VR_TT# CLK_EN# VID<0:6> PSI# DPRSLPVR VR_ON
Rs2 Cs2 L1
ISEN2 ISL62883C BOOT1 UGATE1 PHASE1 COMP FB LGATE1 VSSP1 ISEN1 VSEN ISUM+
Rs1 Cs1 Rsum3 Rsum2
Rdroop
VCCSENSE VSSSENSE Rimon
RTN
Rn Cn Ri
o
C
Rsum1
IMON
IMON
(Bottom Pad) VSS
ISUM-
FIGURE 1. TYPICAL 3-PHASE APPLICATION CIRCUIT USING DCR SENSING
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ISL62883C
Simplified Application Circuits (Continued)
V+5 Rbias Rntc
o
V+5
Vin
V+5
VCC UGATE FCCM PHASE BOOT PWM LGATE GND
Vin L3 Rsen3
VDD VCCP VIN RBIAS PWM3 ISEN3 BOOT2 UGATE2 PHASE2 LGATE2 VSSP2
ISL6208
C
NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset
Rs3 Cs3 L2 Rsen2 Vo
PGOOD VR_TT# CLK_EN# VID<0:6> PSI# DPRSLPVR VR_ON
Rs2 Cs2 L1 Rsen1
ISEN2 ISL62883C BOOT1 UGATE1 PHASE1 COMP FB LGATE1 VSSP1 ISEN1 VSEN ISUM+
Rs1 Cs2 Rsum3 Rsum2
Rdroop
VCCSENSE VSSSENSE Rimon
RTN
Cn Ri
Rsum1
IMON
IMON
(Bottom Pad) VSS
ISUM-
FIGURE 2. TYPICAL 3-PHASE APPLICATION CIRCUIT USING RESISTOR SENSING
V+5 Rbias Rntc
o
V+5
Vin
VDD VCCP VIN RBIAS PWM3 BOOT2 UGATE2 PHASE2 LGATE2 VSSP2 ISEN2 Cs2 BOOT1 L1 Vin L2 Vo
C
NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset
PGOOD VR_TT# CLK_EN# VID<0:6> PSI# DPRSLPVR VR_ON
Rs2
ISL62883C
UGATE1 PHASE1
COMP Rdroop FB2 FB VSEN
LGATE1a VSSP1 ISEN1 Cs1 ISUM+
Rs1
Rsum2 VCCSENSE VSSSENSE Rimon IMON IMON (Bottom Pad) VSS ISUMRn RTN Cn Ri
o
C
Rsum1
FIGURE 3. TYPICAL 2-PGHASE APPLICATION CIRCUIT USING DCR SENSING
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ISL62883C
Simplified Application Circuits (Continued)
V+5 Rbias Rntc
o
V+5
Vin
VDD VCCP VIN RBIAS PWM3 BOOT2 UGATE2 PHASE2 LGATE2 VSSP2 ISEN2 BOOT1 Vin L Vo
C
NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset
PGOOD VR_TT# CLK_EN# VID<0:6> PSI# DPRSLPVR VR_ON
ISL62883C
UGATE1 PHASE1
COMP Rdroop FB2 FB VSEN
LGATE1a VSSP1 ISEN1 ISUM+ Rsum
VCCSENSE VSSSENSE Rimon IMON
Rn RTN IMON ISUMCn Ri (Bottom Pad) VSS
o
C
FIGURE 4. TYPICAL 1-PHASE APPLICATION CIRCUIT USING DCR SENSING
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Theory of Operation
Multiphase R3TM Modulator
VW MASTER CLOCK gmVo MASTER CLOCK CIRCUIT MASTER CLOCK COMP Phase Vcrm Sequencer Crm SLAVE CIRCUIT 1 VW Clock1 S R Q PWM1 Phase1 L1 IL1 Vcrs1 Crs1 SLAVE CIRCUIT 2 VW Clock2 S R Q PWM2 Phase2 L2 IL2 gm Vo Co Clock1 Clock2 Clock3
VW
COMP Vcrm
Master Clock Clock1 PWM1 Clock2 PWM2 Clock3 PWM3 VW
Vcrs2 Crs2
gm
SLAVE CIRCUIT 3 VW Clock3 S R Q PWM3 Phase3 L3 IL3 Vcrs3 Crs3 gm
Vcrs1 Vcrs3 Vcrs2
FIGURE 7. R3TM MODULATOROPERATION PRINCIPLES IN LOAD INSERTION RESPONSE
FIGURE 5. R3TM MODULATOR CIRCUIT
VW Vcrm COMP Master Clock Clock1 PW M1 Clock2 PW M2 Clock3 PW M3 VW Hysteretic W indow
The ISL62883C is a multiphase regulators implementing IntelTM IMVP-6.5TM protocol. It can be programmed for 1-, 2- or 3-phase operation. It uses Intersil patented R3TM (Robust Ripple RegulatorTM) modulator. The R3TM modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. Figure 5 conceptually shows the ISL62883C multiphase R3TM modulator circuit, and Figure 6 shows the operation principles. A current source flows from the VW pin to the COMP pin, creating a voltage window set by the resistor between the two pins. This voltage window is called VW window in the following discussion. Inside the IC, the modulator uses the master clock circuit to generate the clocks for the slave circuits. The modulator discharges the ripple capacitor Crm with a current source equal to gmVo, where gm is a gain factor. Crm voltage Vcrm is a sawtooth waveform traversing between the VW and COMP voltages. It resets to VW when it hits COMP, and generates a one-shot master clock signal. A phase sequencer distributes the master clock signal to the slave circuits. If the ISL62883C is in 3-phase mode, the master clock signal will be distributed to the three phases, and the Clock1~3 signals will be 120 out-of-phase. If the ISL62883C is in 2-phase mode, the master clock signal will be distributed to Phases 1 and 2, and the Clock1 and Clock2 signals will be 180 out-of-phase. If the
Vcrs2 Vcrs3
Vcrs1
FIGURE 6. R3TM MODULATOR OPERATION PRINCIPLES IN STEADY STATE
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ISL62883C is in 1-phase mode, the master clock signal will be distributed to Phases 1 only and be the Clock1 signal. Each slave circuit has its own ripple capacitor Crs, whose voltage mimics the inductor ripple current. A gm amplifier converts the inductor voltage into a current source to charge and discharge Crs. The slave circuit turns on its PWM pulse upon receiving the clock signal, and the current source charges Crs. When Crs voltage VCrs hits VW, the slave circuit turns off the PWM pulse, and the current source discharges Crs. Since the ISL62883C works with Vcrs, which are large-amplitude and noise-free synthesized signals, the ISL62883C achieves lower phase jitter than conventional hysteretic mode and fixed PWM mode controllers. Unlike conventional hysteretic mode converters, the ISL62883C has an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. Figure 7 shows the operation principles during load insertion response. The COMP voltage rises during load insertion, generating the master clock signal more quickly, so the PWM pulses turn on earlier, increasing the effective switching frequency, which allows for higher control loop bandwidth than conventional fixed frequency PWM controllers. The VW voltage rises as the COMP voltage rises, making the PWM pulses wider. During load release response, the COMP voltage falls. It takes the master clock circuit longer to generate the next master clock signal so the PWM pulse is held off until needed. The VW voltage falls as the VW voltage falls, reducing the current PWM pulse width. This kind of behavior gives the ISL62883C excellent response speed. The fact that all the phases share the same VW window voltage also ensures excellent dynamic current balance among phases. ISL62883C can operate in diode emulation (DE) mode to improve light load efficiency. In DE mode, the lowside MOSFET conducts when the current is flowing from source to drain and doesn't not allow reverse current, emulating a diode. As Figure 8 shows, when LGATE is on, the low-side MOSFET carries current, creating negative voltage on the phase node due to the voltage drop across the ON-resistance. The ISL62883C monitors the current through monitoring the phase node voltage. It turns off LGATE when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. If the load current is light enough, as Figure 8 shows, the inductor current will reach and stay at zero before the next phase node pulse, and the regulator is in discontinuous conduction mode (DCM). If the load current is heavy enough, the inductor current will never reach 0A, and the regulator is in CCM although the controller is in DE mode. Figure 9 shows the operation principle in diode emulation mode at light load. The load gets incrementally lighter in the three cases from top to bottom. The PWM on-time is determined by the VW window size, therefore is the same, making the inductor current triangle the same in the three cases. The ISL62883C clamps the ripple capacitor voltage Vcrs in DE mode to make it mimic the inductor current. It takes the COMP voltage longer to hit Vcrs, naturally stretching the switching period. The inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. The reduced switching frequency helps increase light load efficiency.
CCM/DCM BOUNDARY VW Vcrs
Diode Emulation and Period Stretching
iL VW LIGHT DCM
Phase
Vcrs
UG ATE
iL DEEP DCM
LG ATE
Vcrs
VW
IL
iL
FIGURE 8. DIODE EMULATION FIGURE 9. PERIOD STRETCHING
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Start-up Timing
With the controller's VDD voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 1.1V logic high threshold. Figure 10 shows the typical start-up timing when the ISL62883C is configured for CPU VR application. The ISL62883C uses digital soft-start to ramp-up DAC to the boot voltage of 1.1V at about 2.5mV/s. Once the output voltage is within 10% of the boot voltage for 13 PWM cycles (43s for frequency = 300kHz), CLK_EN# is pulled low and DAC slews at 5mV/s to the voltage set by the VID pins. PGOOD is asserted high in approximately 7ms. Similar results occur if VR_ON is tied to VDD, with the soft-start sequence starting 120s after VDD crosses the POR threshold. Figure 11 shows the typical start-up timing when the ISL62883C is configured for GPU VR application. The ISL62883C uses digital soft start to ramp up DAC to the voltage set by the VID pins. The slew rate is 5mV/s when there is DPRSLPVR = 0, and is doubled when there is DPRSLPVR = 1. Once the output voltage is within 10% of the target voltage for 13 PWM cycles (43s for frequency = 300kHz), CLK_EN# is pulled low. PGOOD is asserted high in approximately 7ms. Similar results occur if VR_ON is tied to VDD, with the soft-start sequence starting 120s after VDD crosses the POR threshold.
VDD VR_ON 5mV/s 2.5mV/s 90% Vboot 800s DAC 13 SWITCHING CYCLES VID COMMAND VOLTAGE
Voltage Regulation and Load Line Implementation
After the start sequence, the ISL62883C regulates the output voltage to the value set by the VID inputs per Table 1. The ISL62883C will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75V to 1.5V. A differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die.
TABLE 1. VID TABLE VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125
CLK_EN# ~7ms PGOOD
0 0 0 0 0
FIGURE 10. SOFT-START WAVEFORMS FOR CPU VR APPLICATION
VDD VR_ON SLEW RATE 90% 120s
0 0
VID COMMAND VOLTAGE
0 0 0 0
DAC
13 SWITCHING CYCLES
CLK_EN# ~7ms PGOOD
0 0 0 0 0
FIGURE 11. SOFT-START WAVEFORMS FOR GPU VR APPLICATION
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TABLE 1. VID TABLE (Continued) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VO (V) 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TABLE 1. VID TABLE (Continued) VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375
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TABLE 1. VID TABLE (Continued) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000
load line implementation, current monitor and overcurrent protection. Figure 12 shows the load line implementation. The ISL62883C drives a current source Idroop out of the FB pin, described by Equation 1.
2xV Cn I droop = ----------------Ri (EQ. 1)
When using inductor DCR current sensing, a single NTC element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. Idroop flows through resistor Rdroop and creates a voltage drop as shown in Equation 2.
V droop = R droop x I droop (EQ. 2)
Vdroop is the droop voltage required to implement load line. Changing Rdroop or scaling Idroop can both change the load line slope. Since Idroop also sets the overcurrent protection level, it is recommended to first scale Idroop based on OCP requirement, then select an appropriate Rdroop value to obtain the desired load line slope.
Differential Sensing
Figure 12 also shows the differential voltage sensing scheme. VCCSENSE and VSSSENSE are the remote voltage sensing signals from the processor die. A unity gain differential amplifier senses the VSSSENSE voltage and add it to the DAC output. The error amplifier regulates the inverting and the non-inverting input voltages to be equal as shown in Equation 3:
VCC SENSE + V
droop
Rdroop FB Vdroop
VCCSENSE VR LOCAL "CATCH" VO RESISTOR VIDs RTN VID<0:6> VSSSENSE
= V DAC + VSS SENSE
(EQ. 3)
Idroop COMP E/A
Rewriting Equation 3 and substitution of Equation 2 gives
VCCSENSE - VSS SENSE = V DAC - R droop x I droop (EQ. 4)
VDAC DAC
X1
INTERNAL TO IC
VSS "CATCH" RESISTOR
Equation 4 is the exact equation required for load line implementation. The VCCSENSE and VSSSENSE signals come from the processor die. The feedback will be open circuit in the absence of the processor. As Figure 12 shows, it is recommended to add a "catch" resistor to feed the VR local output voltage back to the compensator, and add another "catch" resistor to connect the VR local output ground to the RTN pin. These resistors, typically 10~100, will provide voltage feedback if the system is powered up without a processor installed.
FIGURE 12. DIFFERENTIAL SENSING AND LOAD LINE IMPLEMENTATION
As the load current increases from zero, the output voltage will droop from the VID table value by an amount proportional to the load current to achieve the load line. The ISL62883C can sense the inductor current through the intrinsic DC Resistance (DCR) of the inductors as shown in Figure 1 on page 10 or through resistors in series with the inductors as shown in Figure 2 on page 11. In both methods, capacitor Cn voltage represents the inductor total currents. A droop amplifier converts Cn voltage into an internal current source with the gain set by resistor Ri. The current source is used for
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Phase Current Balancing
L3 Phase3 ISEN3 INTERNAL TO IC ISEN2 Rs Cs Phase2 Rs Cs Phase1 Rs Cs L1 L2 IL3 Rdcr2 Rpcb2 Vo Rdcr3 Rpcb3
ISEN3 INTERNAL TO IC ISEN2
Rpcb1
Phase3 Rs Cs Rs Rs
V3p
L3
Rdcr3 IL3
Rpcb3
V3n
IL2 Rdcr1
Phase2 Rs Cs Rs Rs
V2p
L2
Rdcr2 IL2
Rpcb2
Vo
V2n
ISEN1
IL1
ISEN1
V1p Phase1 Rs Cs Rs Rs
L1
Rdcr1 IL1
Rpcb1
V1n
FIGURE 13. CURRENT BALANCING CIRCUIT
The ISL62883C monitors individual phase average current by monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 13 shows the current balancing circuit recommended for ISL62883C. Each phase node voltage is averaged by a low-pass filter consisting of Rs and Cs, and presented to the corresponding ISEN pin. Rs should be routed to inductor phase-node pad in order to eliminate the effect of phase node parasitic PCB DCR. Equations 5 thru 7 give the ISEN pin voltages:
V ISEN1 = ( R dcr1 + R pcb1 ) x I L1 V ISEN2 = ( R dcr2 + R pcb2 ) x I L2 V ISEN3 = ( R dcr3 + R pcb3 ) x I L3 (EQ. 5) (EQ. 6) (EQ. 7)
FIGURE 14. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
Sometimes, it is difficult to implement symmetrical layout. For the circuit shown in Figure 13, asymmetric layout causes different Rpcb1, Rpcb2 and Rpcb3 thus current imbalance. Figure 14 shows a differential-sensing current balancing circuit recommended for ISL62883C. The current sensing traces should be routed to the inductor pads so they only pick up the inductor DCR voltage. Each ISEN pin sees the average voltage of three sources: its own phase inductor phase-node pad, and the other two phases inductor output side pads. Equations 8 thru 10 give the ISEN pin voltages:
V ISEN1 = V 1p + V 2n + V 3n V ISEN2 = V 1n + V 2p + V 3n V ISEN3 = V 1n + V 2n + V 3p (EQ. 8) (EQ. 9) (EQ. 10)
where Rdcr1, Rdcr2 and Rdcr3 are inductor DCR; Rpcb1, Rpcb2 and Rpcb3 are parasitic PCB DCR between the inductor output side pad and the output voltage rail; and IL1, IL2 and IL3 are inductor average currents. The ISL62883C will adjust the phase pulse-width relative to the other phases to make VISEN1 = VISEN2 = VISEN3, thus to achieve IL1 = IL2 = IL3, when there are Rdcr1 = Rdcr2 = Rdcr3 and Rpcb1 = Rpcb2 = Rpcb3. Using same components for L1, L2 and L3 will provide a good match of Rdcr1, Rdcr2 and Rdcr3. Board layout will determine Rpcb1, Rpcb2 and Rpcb3. It is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that Rpcb1 = Rpcb2 = Rpcb3.
The ISL62883C will make VISEN1 = VISEN2 = VISEN3 as shown in Equations 11 and 12:
V 1p + V 2n + V 3n = V 1n + V 2p + V 3n V 1n + V 2p + V 3n = V 1n + V 2n + V 3p (EQ. 11) (EQ. 12)
Rewriting Equation 11 gives Equation 13:
V 1p - V 1n = V 2p - V 2n (EQ. 13)
and rewriting Equation 12 gives Equation 14:
V 2p - V 2n = V 3p - V 3n (EQ. 14)
Combining Equations 13 and 14 gives:
V 1p - V 1n = V 2p - V 2n = V 3p - V 3n (EQ. 15)
Therefore:
R dcr1 x I L1 = R dcr2 x I L2 = R dcr3 x I L3 (EQ. 16)
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Current balancing (IL1 = IL2 = IL3) will be achieved when there is Rdcr1 = Rdcr2 = Rdcr3. Rpcb1, Rpcb2 and Rpcb3 will not have any effect. Since the slave ripple capacitor voltages mimic the inductor currents, R3TM modulator can naturally achieve excellent current balancing during steady state and dynamic operations. Figure 15 shows current balancing performance of the ISL62883C evaluation board with load transient of 12A/51A at different rep rates. The inductor currents follow the load current dynamic change with the output capacitors supplying the difference. The inductor currents can track the load current well at low rep rate, but cannot keep up when the rep rate gets into the hundred-kHz range, where it's out of the control loop bandwidth. The controller achieves excellent current balancing in all cases installed.
REP RATE = 10kHz
REP RATE = 25kHz
CCM Switcing Frequency
The Rfset resistor between the COMP and the VW pins sets the sets the VW windows size, therefore sets the switching frequency. When the ISL62883C is in continuous conduction mode (CCM), the switching frequency is not absolutely constant due to the nature of the R3TM modulator. As explained in the Multiphase R3TM Modulator section, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. On the other hand, the switching frequency is relatively constant at steady state. Variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. The variation is usually less than 15% and doesn't have any significant effect on output voltage ripple magnitude. Equation 17 gives an estimate of the frequency-setting resistor Rfset value. 8k Rfset gives approximately 300kHz switching frequency. Lower resistance gives higher switching frequency.
R fset ( k ) = ( Period ( s ) - 0.29 ) x 2.65 (EQ. 17)
REP RATE = 50kHz
REP RATE = 100kHz
REP RATE = 200kHz
FIGURE 15. ISL62883 EVALUATION BOARD CURRENT BALANCING DURING DYNAMIC OPERATION. CH1: IL1, CH2: ILOAD, CH3: IL2, CH4: IL3
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Modes of Operation
TABLE 2. ISL62883C CONFIGURATIONS OVERSHOOT REDUCTION RBIAS ISEN2 CLK_EN# (k) CONFIG. FUNCTION External pull-up Tied to GND or floating External pull-up Tied to GND or floating Tied to x 5V 147 47 147 47 147 47 147 47 147 47 3-phase CPU VR 3-phase GPU VR 2-phase CPU VR 2-phase GPU VR 1-phase CPU 1-phase GPU Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled See Table 4
Table 2 shows the ISL62883C configurations, programmed by the PWM3 pin, the ISEN2 pin, the CLK_EN# pin status and the RBIAS value. When the ISL62883C is in 3- or 2-phase configuration, external pull-up on the CLK_EN# pin puts the ISL62883C in CPU VR configuration; Tying the CLK_EN# pin to GND or leaving it floating puts the ISL62883C in GPU VR configuration. In 3- or 2-phase configuration, RBIAS = 147k disables the overshoot reduction function and RBIAS = 47k enables it. If the PWM3 pin and the ISEN2 pin are both tied to 5V, the ISL62883C is in 1-phase configuration. The CLK_EN# pin status has no effect. RBIAS = 147k puts the ISL62883C in CPU VR configuration and RBIAS = 47k puts the ISL62883C in GPU configuration. In 1-phase configuration, the enabling and disabling of the overshoot reduction function are programmed by the resistance from COMP to GND, as Table 4 shows. Table 3 shows the ISL62883C operational modes, programmed by the logic status of the PSI# and the DPRSLPVR pins.
PWM3
To To External Power Stage Driver
Tied to 5V
TABLE 3. ISL62883C MODES OF OPERATION CONFIG. 3-phase CPU Config. OPERATIONAL PSI# DPRSLPVR MODE 0 1 0 1 3-phase GPU Config. 0 1 0 1 2-phase CPU Config. 0 1 0 1 2-phase GPU Config. 0 1 0 1 1-phase CPU Config. 1-phase GPU Config. x x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 2-phase CCM 3-phase CCM 1-phase DE 1-phase DE 2-phase CCM 3-phase CCM 1-phase DE 1-phase DE 1-phase CCM 2-phase CCM 1-phase DE 1-phase DE 1-phase CCM 2-phase CCM 1-phase DE 1-phase DE 1-phase CCM 1-phase DE 1-phase CCM 1-phase DE 10mV/s 5mV/s 10mV/s 5mV/s 10mV/s SLEW RATE 5mV/s
In 3-phase configuration, the ISL62883C enters 2-phase CCM for (PSI# = 0 and DPRSLPVR = 0). It drops phase 3 and operates phases 1 and 2 180 out-of-phase. It also reduces the overcurrent and the way-overcurrent protection levels to 2/3 of the initial values. The ISL62883C enters 1-phase DE mode for DPRSLPVR = 1 by dropping phase 2 and reduces the overcurrent and the way-overcurrent protection levels to 1/3 of the initial values. In 2-phase configuration, the ISL62883C enters 1-phase CCM for (PSI# = 0 and DPRSLPVR = 0). It drops phase 2 and reduces the overcurrent and the way-overcurrent protection levels to 1/2 of the initial values. The ISL62883C enters 1-phase DE mode for DPRSLPVR = 1 by dropping phase 2 and reduces the overcurrent and the way-overcurrent protection levels to 1/3 of the initial values. In 1-phase configuration, the ISL62883C does not change the operational mode when the PSI# signal changes status. It enters 1-phase DE mode when DLPRSLPVR = 1.
Dynamic Operation
When the ISL62883C is configured for CPU VR application, it responds to VID changes by slewing to the new voltage at 5mV/s slew rate. As the output approaches the VID command voltage, the dv/dt moderates to prevent overshoot. Geyserville-III transitions commands one LSB VID step (12.5mV) every 2.5s, controlling the effective dv/dt at 5mv/s. The ISL62883C is capable of 5mV/s slew rate. When the ISL62883C is configured for GPU VR application, it responds to VID changes by slewing to the new voltage at a slew rate set by the logic status on the DPRSLPVR pin. The slew rate is 5mV/s when DPRSLPVR=0 and is doubled when DPRSLPVR = 1.
The ISL62883C can be configured for 3, 2 or 1-phase operation. For 2-phase configuration, tie the PWM3 pin to 5V. In this configuration, phases 1 and 2 are active. For 1-phase configuration, tie the ISEN2 pin to 5V. In this configuration, only phase-1 is active.
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When the ISL62883C is in DE mode, it will actively drive the output voltage up when the VID changes to a higher value. The DE mode operation will resume after reaching the new voltage level. If the load is light enough to warrant DCM, it will enter DCM after the inductor current has crossed zero for four consecutive cycles. The ISL62883C will remain in DE mode when the VID changes to a lower value. The output voltage will decay to the new value and the load will determine the slew rate. Overvoltage protection is blanked during VID down transition in DE mode until the output voltage is within 60mV of the VID value. During load insertion response, the Fast Clock function increases the PWM pulse response speed. The ISL62883C monitors the VSEN pin voltage and compares it to 100ns-filtered version. When the unfiltered version is 20mV below the filtered version, the controller knows there is a fast voltage dip due to load insertion, hence issues an additional master clock signal to deliver a PWM pulse immediately. The R3TM modulator intrinsically has voltage feed-forward. The output voltage is insensitive to a fast slew rate input voltage change. The default OCP threshold is the value when Rcomp is not populated. It is recommended to scale the droop current Idroop such that the default OCP threshold gives approximately the desired OCP level, then use Rcomp to fine tune the OCP level if necessary. For overcurrent conditions above 2.5x the OCP level, the PWM outputs will immediately shut off and PGOOD will go low to maximize protection. This protection is also referred to as way-overcurrent protection or fast-overcurrent protection, for short-circuit protections. The ISL62883C monitors the ISEN pin voltages to determine current-balance protection. If the ISEN pin voltage difference is greater than 9mV for 1ms, the controller will declare a fault and latch off. The ISL62883C will declare undervoltage (UV) fault and latch off if the output voltage is less than the VID set value by 300mV or more for 1ms. It'll turn off the PWM outputs and de-assert PGOOD. The ISL62883C has two levels of overvoltage protections. The first level of overvoltage protection is referred to as PGOOD overvoltage protection. If the output voltage exceeds the VID set value by +200mV for 1ms, the ISL62883C will declare a fault and de-assert PGOOD. The ISL62883C takes the same actions for all of the above fault protections: de-assertion of PGOOD and turn-off of the high-side and low-side power MOSFETs. Any residual inductor current will decay through the MOSFET body diodes. These fault conditions can be reset by bringing VR_ON low or by bringing VDD below the POR threshold. When VR_ON and VDD return to their high operating levels, a soft-start will occur. The second level of overvoltage protection is different. If the output voltage exceeds 1.55V, the ISL62883C will immediately declare an OV fault, de-assert PGOOD, and turn on the low-side power MOSFETs. The low-side power MOSFETs remain on until the output voltage is pulled down below 0.85V when all power MOSFETs are turned off. If the output voltage rises above 1.55V again, the protection process is repeated. This behavior provides the maximum amount of protection against shorted high-side power MOSFETs while preventing output ringing below ground. Resetting VR_ON cannot clear the 1.55V OVP. Only resetting VDD will clear it. The 1.55V OVP is active all the time when the controller is enabled, even if one of the other faults have been declared. This ensures that the processor is protected against high-side power MOSFET leakage while the MOSFETs are commanded off. The ISL62883C has a thermal throttling feature. If the voltage on the NTC pin goes below the 1.18V OT threshold, the VR_TT# pin is pulled low indicating the need for thermal throttling to the system. No other action is taken within the ISL62883C in response to NTC pin voltage. Table 5 summarizes the fault protections.
Protections
The ISL62883C provides overcurrent, current-balance, undervoltage, overvoltage, and over-temperature protections. The ISL62883C determines overcurrent protection (OCP) by comparing the average value of the droop current Idroop with an internal current source threshold. It declares OCP when Idroop is above the threshold for 120s. A resistor Rcomp from the COMP pin to GND programs the OCP current source threshold, as well as the overshoot reduction function in 1-phase configuration, as Table 4 shows. It is recommended to use the nominal Rcomp value. The ISL62883C detects the Rcomp value at the beginning of start-up, and sets the internal OCP threshold accordingly. It remembers the Rcomp value until the VR_ON signal drops below the POR threshold.
TABLE 4. ISL62883C Rcomp PROGRAMMABILITY Rcomp MIN NOM MAX (k) (k) (k) none none 320 210 155 104 78 62 45 400 235 165 120 85 66 50 480 260 175 136 92 70 55 3-PHASE 2-PHASE CONFIG. CONFIG. 1-PHASECONFIG. OVERSHOOT REDUCTION FUNCTION 60 68 62 54 60 68 62 54 Enabled Disabled
OCP THRESHOLD (A) 60 68 62 54 56 58 64 66 40 45.3 41.3 36 37.33 38.7 42.7 44
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ISL62883C
TABLE 5. FAULT PROTECTION SUMMARY FAULT DURATION BEFORE PROTECTION PROTECTION ACTION 120s <2s 1ms
FAULT TYPE Overcurrent Way-Overcurrent (2.5xOC) Overvoltage +200mV Undervoltage 300mV Phase Current Unbalance Overvoltage 1.55V
FAULT RESET
the compensator. The compensator gain will increase with the removal of C3.2. By properly sizing C3.1 and C3.2, the compensator cab be optimal for both 2-phase mode and 1-phase mode. When the FB2 switch is off, C3.2 is disconnected from the FB pin. However, the controller still actively drives the FB2 pin voltage to follow the FB pin voltage such that C3.2 voltage always follows C3.1 voltage. When the controller turns on the FB2 switch, C3.2 will be reconnected to the compensator smoothly. The FB2 function ensures excellent transient response in both 2-phase mode and 1-phase mode. If one decides not to use the FB2 function, simply populate C3.1 only.
PWM tri-state, VR_ON toggle or PGOOD VDD latched low toggle
Immediately Low-side VDD MOSFET on toggle until Vcore <0.85V, then PWM tri-state, PGOOD latched low. 1ms N/A
Adaptive Body Diode Conduction Time Reduction
In DCM, the controller turns off the low-side MOSFET when the inductor current approaches zero. During ontime of the low-side MOSFET, phase voltage is negative and the amount is the MOSFET rDS(ON) voltage drop, which is proportional to the inductor current. A phase comparator inside the controller monitors the phase voltage during on-time of the low-side MOSFET and compares it with a threshold to determine the zero-crossing point of the inductor current. If the inductor current has not reached zero when the low-side MOSFET turns off, it'll flow through the low-side MOSFET body diode, causing the phase node to have a larger voltage drop until it decays to zero. If the inductor current has crossed zero and reversed the direction when the low-side MOSFET turns off, it'll flow through the highside MOSFET body diode, causing the phase node to have a spike until it decays to zero. The controller continues monitoring the phase voltage after turning off the low-side MOSFET and adjusts the phase comparator threshold voltage accordingly in iterative steps such that the low-side MOSFET body diode conducts for approximately 40ns to minimize the body diode-related loss.
Over-Temperature
Current Monitor
The ISL62883C provides the current monitor function. The IMON pin outputs a high-speed analog current source that is 3 times of the droop current flowing out of the FB pin. Thus Equation 18:
I IMON = 3 x I droop (EQ. 18)
As Figures 1 and 2 show, a resistor Rimon is connected to the IMON pin to convert the IMON pin current to voltage. A capacitor can be paralleled with Rimon to filter the voltage information. The IMVP-6.5TM specification requires that the IMON voltage information be referenced to VSSSENSE. The IMON pin voltage range is 0V to 1.1V. A clamp circuit prevents the IMON pin voltage from going above 1.1V.
FB2 Function
The FB2 function is only available when the ISL62883C is in 2-phase configuration.
CONTROLLER IN 2-PHASE MODE C2 R3 R1 FB VREF E/A C1 R2 C3.1 FB2 C3.2 CONTROLLER IN 1-PHASE MODE C2 R3 R1 FB VREF E/A COMP C1 R2 C3.1 FB2 C3.2
Overshoot Reduction Function
The ISL62883C has an optional overshoot reduction function. Tables 2 and 4 show how to enable and disable it. When a load release occurs, the energy stored in the inductors will dump to the output capacitor, causing output voltage overshoot. The inductor current freewheels through the low-side MOSFET during this period of time. The overshoot reduction function turns off the low-side MOSFET during the output voltage overshoot, forcing the inductor current to freewheel through the low-side MOSFET body diode. Since the body diode voltage drop is much higher than MOSFET rDS(ON) voltage drop, more energy is dissipated on the low-side MOSFET therefore the output voltage overshoot is lower. If the overshoot reduction function is enabled, the ISL62883C monitors the COMP pin voltage to determine the output voltage overshoot condition. The COMP voltage will fall and hit the clamp voltage when the
FN7557.1 March 18, 2010
VSEN
VSEN COMP
FIGURE 16. FB2 FUNCTION
Figure 16 shows the FB2 function. A switch (called FB2 switch) turns on to short the FB and the FB2 pins when the controller is in 2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving as part of the compensator. When the controller enters 1-phase mode, the FB2 switch turns off, removing C3.2 and leaving only C3.1 in 22
ISL62883C
output voltage overshoots. The ISL62883C will turn off LGATE1 and LGATE2 when COMP is being clamped. All the low-side MOSFETs in the power stage will be turned off. When the output voltage has reached its peak and starts to come down, the COMP voltage starts to rise and is no longer clamped. The ISL62883C will resume normal PWM operation. When PSI# is low, indicating a low power state of the CPU, the controller will disable the overshoot reduction function as large magnitude transient event is not expected and overshoot is not a concern. While the overshoot reduction function reduces the output voltage overshoot, energy is dissipated on the low-side MOSFET, causing additional power loss. The more frequent transient event, the more power loss dissipated on the low-side MOSFET. The MOSFET may face severe thermal stress when transient events happen at a high repetitive rate. User discretion is advised when this function is enabled. Figure 17 shows shows the inductor DCR currentsensing network for a 3-phase solution. An inductor current flows through the DCR and creates a voltage drop. Each inductor has two resistors in Rsum and Ro connected to the pads to accurately sense the inductor current by sensing the DCR voltage drop. The Rsum and Ro resistors are connected in a summing network as shown, and feed the total current information to the NTC network (consisting of Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative temperature coefficient (NTC) thermistor, used to temperature-compensate the inductor DCR change. The inductor output side pads are electrically shorted in the schematic, but have some parasitic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. It is recommended to use 1W~10W Ro to create quality signals. Since Ro value is much smaller than the rest of the current sensing circuit, the following analysis will ignore it for simplicity. The summed inductor current information is presented to the capacitor Cn. Equations 19 thru 23 describe the frequency-domain relationship between inductor total current Io(s) and Cn voltage VCn(s):
R ntcnet DCR V Cn ( s ) = ------------------------------------------ x ------------- x I o ( s ) x A cs ( s ) N R sum R ntcnet + ------------- N ( R ntcs + R ntc ) x R p R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p s 1 + -----L A cs ( s ) = ---------------------s 1 + ----------- sns DCR L = ------------L
ISUM+
Key Component Selection
RBIAS The ISL62883C uses a resistor (1% or better tolerance is recommended) from the RBIAS pin to GND to establish highly accurate reference current sources inside the IC. Refer to Table 2 to select the resistance according to desired configuration. Do not connect any other components to this pin. Do not connect any capacitor to the RBIAS pin as it will create instability.
Care should be taken in layout that the resistor is placed very close to the RBIAS pin and that a good quality signal ground is connected to the opposite side of the RBIAS resistor.
(EQ. 19)
(EQ. 20)
(EQ. 21)
Inductor DCR Current-Sensing Network
Phase1 Phase2 Phase3 Rsum Rsum Rsum
(EQ. 22)
L
L
L
Rntcs Rp Cn Vcn
1 sns = -------------------------------------------------------R sum R ntcnet x -------------N ------------------------------------------ x C n R sum R ntcnet + -------------N
(EQ. 23)
DCR
DCR
DCR
Rntc Ro Ro Ro Ri ISUM-
where N is the number of phases. Transfer function Acs(s) always has unity gain at DC. The inductor DCR value increases as the winding temperature increases, giving higher reading of the inductor DC current. The NTC Rntc values decreases as its temperature decreases. Proper selections of Rsum, Rntcs, Rp and Rntc parameters ensure that VCn represent the inductor total DC current over the temperature range of interest.
Io
FIGURE 17. DCR CURRENT-SENSING NETWORK
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ISL62883C
There are many sets of parameters that can properly temperature-compensate the DCR change. Since the NTC network and the Rsum resistors form a voltage divider, Vcn is always a fraction of the inductor DCR voltage. It is recommended to have a higher ratio of Vcn to the inductor DCR voltage, so the droop circuit has higher signal level to work with. A typical set of parameters that provide good temperature compensation are: Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k and Rntc = 10k (ERT-J1VR103J). The NTC network parameters may need to be fine tuned on actual boards. One can apply full load DC current and record the output voltage reading immediately; then record the output voltage reading again when the board has reached the thermal steady state. A good NTC network can limit the output voltage drift to within 2mV. It is recommended to follow the Intersil evaluation board layout and current-sensing network parameters to minimize engineering time. VCn(s) also needs to represent real-time Io(s) for the controller to achieve good transient response. Transfer function Acs(s) has a pole wsns and a zero wL. One needs to match wL and wsns so Acs(s) is unity gain at all frequencies. By forcing wL equal to wsns and solving for the solution, Equation 24 gives Cn value.
L C n = -------------------------------------------------------------R sum R ntcnet x -------------N ------------------------------------------ x DCR R sum R ntcnet + -------------N (EQ. 24)
io
Vo
FIGURE 18. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
io
V o
FIGURE 19. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
io
V o
For example, given N = 3, Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k, DCR = 0.88m and L = 0.36H, Equation 24 gives Cn = 0.406F. Assuming the compensator design is correct, Figure 18 shows the expected load transient response waveforms if Cn is correctly selected. When the load current Icore has a square change, the output voltage Vcore also has a square response. If Cn value is too large or too small, VCn(s) will not accurately represent real-time Io(s) and will worsen the transient response. Figure 19 shows the load transient response when Cn is too small. Vcore will sag excessively upon load insertion and may create a system failure. Figure 20 shows the transient response when Cn is too large. Vcore is sluggish in drooping to its final value. There will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the CPU reliability.
FIGURE 20. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
io
iL
Vo RING BACK
FIGURE 21. OUTPUT VOLTAGE RING BACK PROBLEM
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FN7557.1 March 18, 2010
ISL62883C
ISUM+
Rntcs Rp Rntc
Cn.1 Cn.2 Vcn Rn OPTIONAL Ri ISUM-
transient response waveforms on an actual board. The recommended range for Cip is 100pF~2000pF. However, it should be noted that the Rip -Cip branch may distort the idroop waveform. Instead of being triangular as the real inductor current, idroop may have sharp spikes, which may adversely affect idroop average value detection and therefore may affect OCP accuracy. User discretion is advised.
Resistor Current-Sensing Network
Phase1 Phase2 Phase3
Rip
Cip
L
L
L
OPTIONAL
DCR
DCR
DCR Rsum Rsum Rsum ISUM+
FIGURE 22. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Figure 21 shows the output voltage ring back problem during load transient response. The load current io has a fast step change, but the inductor current iL cannot accurately follow. Instead, iL responds in first order system fashion due to the nature of current loop. The ESR and ESL effect of the output capacitors makes the output voltage Vo dip quickly upon load current change. However, the controller regulates Vo according to the droop current idroop, which is a real-time representation of iL; therefore it pulls Vo back to the level dictated by iL, causing the ring back problem. This phenomenon is not observed when the output capacitor have very low ESR and ESL, such as all ceramic capacitors. Figure 22 shows two optional circuits for reduction of the ring back. Cn is the capacitor used to match the inductor time constant. It usually takes the parallel of two (or more) capacitors to get the desired value. Figure 22 shows that two capacitors Cn.1 and Cn.2 are in parallel. Resistor Rn is an optional component to reduce the Vo ring back. At steady state, Cn.1 + Cn.2 provides the desired Cn capacitance. At the beginning of io change, the effective capacitance is less because Rn increases the impedance of the Cn.1 branch. As Figure 19 explains, Vo tends to dip when Cn is too small, and this effect will reduce the Vo ring back. This effect is more pronounced when Cn.1 is much larger than Cn.2. It is also more pronounced when Rn is bigger. However, the presence of Rn increases the ripple of the Vn signal if Cn.2 is too small. It is recommended to keep Cn.2 greater than 2200pF. Rn value usually is a few ohms. Cn.1, Cn.2 and Rn values should be determined through tuning the load transient response waveforms on an actual board. Rip and Cip form an R-C branch in parallel with Ri, providing a lower impedance path than Ri at the beginning of io change. Rip and Cip do not have any effect at steady state. Through proper selection of Rip and Cip values, idroop can resemble io rather than iL, and Vo will not ring back. The recommended value for Rip is 100. Cip should be determined through tuning the load 25
Rsen
Rsen
Rsen Ro Ro Ro
Vcn
Cn Ri
ISUM-
Io
FIGURE 23. RESISTOR CURRENT-SENSING NETWORK
Figure 23 shows the resistor current-sensing network for a 2-phase solution. Each inductor has a series current-sensing resistor Rsen. Rsum and Ro are connected to the Rsen pads to accurately capture the inductor current information. The Rsum and Ro resistors are connected to capacitor Cn. Rsum and Cn form a a filter for noise attenuation. Equations 25 thru 27 give VCn(s) expression
R sen V Cn ( s ) = ------------- x I o ( s ) x A Rsen ( s ) N 1 A Rsen ( s ) = ---------------------s 1 + ----------- sns 1 Rsen = ---------------------------R sum -------------- x C n N (EQ. 25) (EQ. 26)
(EQ. 27)
Transfer function ARsen(s) always has unity gain at DC. Current-sensing resistor Rsen value will not have significant variation over-temperature, so there is no need for the NTC network. The recommended values are Rsum = 1k and Cn = 5600pF.
Overcurrent Protection
Refer to Equation 1 on page 17 and Figures 17, 21 and 23; resistor Ri sets the droop current Idroop. Table 4 on page 21 shows the internal OCP threshold. It is recommended to design Idroop without using the Rcomp resistor.
FN7557.1 March 18, 2010
ISL62883C
For example, the OCP threshold is 60A for 3-phase solution. We will design Idroop to be 40.9A at full load, so the OCP trip level is 1.5x of the full load current. For inductor DCR sensing, Equation 28 gives the DC relationship of Vcn(s) and Io(s).
R ntcnet DCR V Cn = ------------------------------------------ x ------------- x I o R sum N R ntcnet + ------------- N (EQ. 28)
flexibility. Table 4 shows the detail. It is recommended to scale Idroop such that the default OCP threshold gives approximately the desired OCP level, then use Rcomp to fine tune the OCP level if necessary.
Load Line Slope
Refer to Figure 12. For inductor DCR sensing, substitution of Equation 29 into Equation 2 gives the load line slope expression:
2R droop R ntcnet V droop DCR LL = ------------------ = ---------------------- x ------------------------------------------ x ------------Io Ri R sum N R ntcnet + -------------N (EQ. 36)
Substitution of Equation 28 into Equation 1 gives Equation 29:
R ntcnet 2DCR I droop = ---- x ------------------------------------------ x ------------- x I o R sum Ri N R ntcnet + -------------N (EQ. 29)
For resistor sensing, substitution of Equation 33 into Equation 2 gives the load line slope expression:
2R sen x R droop V droop LL = ------------------ = -----------------------------------------N x Ri Io (EQ. 37)
Therefore:
2R ntcnet x DCR x I o R i = --------------------------------------------------------------------------------R sum N x R ntcnet + -------------- x I droop N (EQ. 30)
Substitution of Equation 30 and rewriting Equation 36, or substitution of Equation 34 and rewriting Equation 37 give the same result in Equation 38:
Io R droop = ---------------- x LL I droop (EQ. 38)
Substitution of Equation 20 and application of the OCP condition in Equation 30 gives Equation 31:
( R ntcs + R ntc ) x R p 2 x ---------------------------------------------------- x DCR x I omax R ntcs + R ntc + R p R i = ---------------------------------------------------------------------------------------------------------------------------( R ntcs + R ntc ) x R p R sum N x ---------------------------------------------------- + -------------- x I droopmax N R ntcs + R ntc + R p
(EQ. 31)
One can use the full load condition to calculate Rdroop. For example, given Iomax = 51A, Idroopmax = 40.9A and LL = 1.9m, Equation 38 gives Rdroop = 2.37k. It is recommended to start with the Rdroop value calculated by Equation 38, and fine tune it on the actual board to get accurate load line slope. One should record the output voltage readings at no load and at full load for load line slope calculation. Reading the output voltage at lighter load instead of full load will increase the measurement error.
where Iomax is the full load current, Idroopmax is the corresponding droop current. For example, given N = 3, Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k, DCR = 0.88m, Iomax = 51A and Idroopmax = 40.9A, Equation 31 gives Ri = 606. For resistor sensing, Equation 32 gives the DC relationship of Vcn(s) and Io(s).
R sen V Cn = ------------- x I o N (EQ. 32)
Current Monitor
Refer to Equation 18 for the IMON pin current expression. Refer to Figures 1 and 2, the IMON pin current flows through Rimon. The voltage across Rimon is expressed in Equation 39:
V Rimon = 3 x I droop x R imon (EQ. 39)
Substitution of Equation 32 into Equation 1 gives Equation 33:
2 R sen I droop = ---- x ------------- x I o N Ri (EQ. 33)
Rewriting Equation 38 gives Equation 40:
Io I droop = ------------------ x LL R droop (EQ. 40)
Therefore
2R sen x I o R i = --------------------------N x I droop (EQ. 34)
Substitution of Equation 34 and application of the OCP condition in Equation 30 gives Equation 35:
2R sen x I omax R i = --------------------------------------N x I droopmax (EQ. 35)
Substitution of Equation 40 into Equation 39 gives Equation 41:
3I o x LL V Rimon = --------------------- x R imon R droop (EQ. 41)
where Iomax is the full load current, Idroopmax is the corresponding droop current. For example, given N = 3, Rsen = 1m, Iomax = 51A and Idroopmax = 40.9A, Equation 35 gives Ri = 831. A resistor from COMP to GND can adjust the internal OCP threshold, providing another dimension of fine-tune 26
Rewriting Equation 41 and application of full load condition gives Equation 42:
V Rimon x R droop R imon = ---------------------------------------------3I o x LL (EQ. 42)
For example, given LL = 1.9m, Rdroop = 2.37k, VRimon = 999mV at Iomax = 51A, Equation 42 gives Rimon = 8.14k.
FN7557.1 March 18, 2010
ISL62883C
A capacitor Cimon can be paralleled with Rimon to filter the IMON pin voltage. The RimonCimon time constant is the user's choice. It is recommended to have a time constant long enough such that switching frequency ripples are removed. T1(s) is the total loop gain of the voltage loop and the droop loop. It always has a higher crossover frequency than T2(s) and has more meaning of system stability. T2(s) is the voltage loop gain with closed droop loop. It has more meaning of output voltage response. Design the compensator to get stable T1(s) and T2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope.
L Q1 Vin GATE Q2 DRIVER C out io V o
Compensator
Figure 18 shows the desired load transient response waveforms. Figure 24 shows the equivalent circuit of a voltage regulator (VR) with the droop function. A VR is equivalent to a voltage source (= VID) and output impedance Zout(s). If Zout(s) is equal to the load line slope LL, i.e. constant output impedance, in the entire frequency range, Vo will have square response when Io has a square change.
Zout(s) = LL i o
LOAD LINE SLOPE
VID VR LOAD V o
20 MOD. COMP CHANNEL B LOOP GAIN = CHANNEL A EA VID ISOLATION TRANSFORMER
FIGURE 24. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
Intersil provides a Microsoft Excel-based spreadsheet to help design the compensator and the current sensing network, so the VR achieves constant output impedance as a stable system. Figure 27 shows a screenshot of the spreadsheet. A VR with active droop function is a dual-loop system consisting of a voltage loop and a droop loop which is a current loop. However, neither loop alone is sufficient to describe the entire system. The spreadsheet shows two loop gain transfer functions, T1(s) and T2(s), that describe the entire system. Figure 25 conceptually shows T1(s) measurement set-up and Figure 26 conceptually shows T2(s) measurement set-up. The VR senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. T(1) is measured after the summing node, and T2(s) is measured in the voltage loop before the summing node. The spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s) can be actually measured on an ISL62883C regulator.
CHANNEL A CHANNEL B NETWORK ANALYZER EXCITATION OUTPUT
FIGURE 25. LOOP GAIN T1(s) MEASUREMENT SET-UP
V O
L Q1 VIN GATE Q2 DRIVER COUT
I O
LOAD LINE SLOPE 20 MOD. EA COMP VID ISOLATION TRANSFORMER
CHANNEL B LOOP GAIN= CHANNEL A
CHANNEL A CHANNEL B NETWORK ANALYZER EXCITATION OUTPUT
FIGURE 26. LOOP GAIN T2(s) MEASUREMENT SET-UP
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FN7557.1 March 18, 2010
Compensation & Current Sensing Network Design for Intersil Multiphase R^3 Regulators for IMVP-6.5
Jia Wei, jwei@intersil.com, 919-405-3605 Attention: 1. "Analysis ToolPak" Add-in is required. To turn on, go to Tools--Add-Ins, and check "Analysis ToolPak". 2. Green cells require user input Compensator Parameters Operation Parameters Controller Part Number: ISL6288x s * s* 1 KZi Zi 1 Phase Number: 2 2Sf z1 2Sf z 2 (c) (c) AV ( s ) Vin: 12 volts s * s* 1 Vo: 1.15 volts s 1 2Sf p1 2Sf p 2 (c) (c) Full Load Current: 50 Amps Estimated Full-Load Efficiency: 87 % Number of Output Bulk Capacitors: 3 Recommended Value User-Selected Value Capacitance of Each Output Bulk Capacitor: 470 uF R1 2.870 k : R1 2.87 k : ESR of Each Output Bulk Capacitor: 4.5 m : ESL of Each Output Bulk Capacitor: 0.6 nH R2 387.248 k : R2 412 k : Number of Output Ceramic Capacitors: 30 R3 0.560 k : R3 0.562 k : Capacitance of Each Output Ceramic Capacitor: 10 uF C1 188.980 pF C1 150 pF C2 498.514 pF C2 390 pF ESR of Each Output Ceramic Capacitor: 3 m: ESL of Each Output Ceramic Capacitor: 3 nH C3 32.245 pF C3 32 pF Switching Frequency: 300 kHz Use User-Selected Value (Y/N)? N Inductance Per Phase: 0.36 uH CPU Socket Resistance: 0.9 m : Performance and Stability Desired Load-Line Slope: 1.9 m : Desired ISUM- Pin Current at Full Load: 33.1 uA T1 Bandwidth: 190kHz T2 Bandwidth: 52kHz (This sets the over-current protection level) T1 Phase Margin: 63.4 T2 Phase Margin: 94.7
Changing the settings in red requires deep understanding of control loop design Place the 2nd compensator pole fp2 at: 1.9 xfs (Switching Frequency) Tune K i to get the desired loop gain bandwidth
Current Sensing Network Parameters
0DJQLWXGH PRKP
*DLQ G%
3KDVH GHJUHH
3KDVH GHJUHH
28
FN7557.1 March 18, 2010
Tune the compensator gain factor K i: (Recommended K i range is 0.8~2) ( ( ( ( )UHTXHQF\ +]
1.15
Output Impedance, Gain Curve
Operation Parameters Inductor DCR 0.88 m : Rsum 3.65 k : Rntc 10 k : Rntcs 2.61 k : Rp 11 k : Recommended Value Cn 0.294 uF Ri 1014.245 : User Selected Value Cn 0.294 uF Ri 1000 :
ISL62883C
Loop Gain, Gain Curve 7V 7V
(
(
(
(
(
(
(
(
)UHTXHQF\ +] Output Impedance, Phase Curve
(
Loop Gain, Phase Curve 7V 7V
(
(
( ( )UHTXHQF\ +]
(
(
(
( ( )UHTXHQF\ +]
(
(
FIGURE 27. SCREENSHOT OF THE COMPENSATOR DESIGN SPREADSHEET
ISL62883C
Optional Slew Rate Compensation Circuit For 1-Tick VID Transition
Rdroop Rvid Cvid OPTIONAL FB Ivid Idroop_vid COMP E/A
To control Vcore slew rate during 1-tick VID transition, one can add the Rvid-Cvid branch, whose current Ivid cancels Idroop_vid. When Vcore increases, the time domain expression of the induced Idroop change is
-------------------------- C out x LL dV core C x LL I droop ( t ) = ------------------------- x ------------------ x 1 - e out dt R droop -t
Vcore
(EQ. 43)
where Cout is the total output capacitance.
VIDs RTN VID<0:6> VSSSENSE
VDACDAC
X1
In the mean time, the Rvid-Cvid branch current Ivid time domain expression is:
------------------------------- dV fb R xC vid I vid ( t ) = C vid x ------------ x 1 - e vid dt -t
INTERNAL TO IC
VID<0:6>
VSS
(EQ. 44)
It is desired to let Ivid(t) cancel Idroop_vid(t). So there are:
dV fb C out x LL dV core C vid x ------------ = ------------------------- x -----------------R droop dt dt (EQ. 45)
Vfb
and:
Ivid
R vid x C vid = C out x LL
(EQ. 46)
The result is expressed in Equation 47:
R vid = R droop
Vcore
(EQ. 47)
and:
dV core C out x LL -----------------dt C vid = ------------------------- x -----------------R droop dV fb -----------dt (EQ. 48)
Idroop_vid
FIGURE 28. OPTIONAL SLEW RATE COMPENSATION CIRCUIT FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the VIDs at a controlled slew rate. For example, the DAC may change a tick (12.5mV) per 2.5s per, controlling output voltage Vcore slew rate at 5mV/s. Figure 28 shows the waveforms of 1-tick VID transition. During 1-tick VID transition, the DAC output changes at approximately 15mV/s slew rate, but the DAC cannot step through multiple VIDs to control the slew rate. Instead, the control loop response speed determines Vcore slew rate. Ideally, Vcore will follow the FB pin voltage slew rate. However, the controller senses the inductor current increase during the up transition, as the Idroop_vid waveform shows, and will droop the output voltage Vcore accordingly, making Vcore slew rate slow. Similar behavior occurs during the down transition.
For example: given LL = 1.9m, Rdroop = 2.37k, Cout = 1320F, dVcore/dt = 5mV/s and dVfb/dt = 15mV/s, Equation 47 gives Rvid = 2.37k and Equation 48 gives Cvid = 350pF. It's recommended to select the calculated Rvid value and start with the calculated Cvid value and tweak it on the actual board to get the best performance. During normal transient response, the FB pin voltage is held constant, therefore is virtual ground in small signal sense. The Rvid - Cvid network is between the virtual ground and the real ground, and hence has no effect on transient response.
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ISL62883C
Voltage Regulator Thermal Throttling
54A 64A
Therefore, a larger value thermistor such as 470k NTC should be used. At +105C, 470k NTC resistance becomes (0.03322 x 470k) = 15.6k. With 60A on the NTC pin, the voltage is only (15.6k x 60A) = 0.937V. This value is much lower than the threshold voltage of 1.20V. Therefore, a regular resistor needs to be in series with the NTC. The required resistance can be calculated by Equation 51:
1.20V --------------- - 15.6k = 4.4k 60A (EQ. 51)
SW1 NTC VNTC + RNTC Rs 1.24V SW2 1.20V INTERNAL TO ISL62883C +
VR_TT#
FIGURE 29. CIRCUITRY ASSOCIATED WITH THE THERMAL THROTTLING FEATURE
4.42k is a standard resistor value. Therefore, the NTC branch should have a 470k NTC and 4.42k resistor in series. The part number for the NTC thermistor is ERTJ0EV474J. It is a 0402 package. NTC thermistor will be placed in the hot spot of the board.
Current Balancing
Refer to Figures 1 and 2. The ISL62883C achieves current balancing through matching the ISEN pin voltages. Rs and Cs form filters to remove the switching ripple of the phase node voltages. It is recommended to use rather long RsCs time constant such that the ISEN voltages have minimal ripple and represent the DC current flowing through the inductors. Recommended values are Rs = 10k and Cs = 0.22F.
Figure 29 shows the thermal throttling feature with hysteresis. An NTC network is connected between the NTC pin and GND. At low temperature, SW1 is on and SW2 connects to the 1.20V side. The total current flowing out of the NTC pin is 60A. The voltage on NTC pin is higher than threshold voltage of 1.20V and the comparator output is low. VR_TT# is pulled up by the external resistor. When temperature increases, the NTC thermistor resistance decreases so the NTC pin voltage drops. When the NTC pin voltage drops below 1.20V, the comparator changes polarity and turns SW1 off and throws SW2 to 1.24V. This pulls VR_TT# low and sends the signal to start thermal throttle. There is a 6A current reduction on NTC pin and 40mV voltage increase on threshold voltage of the comparator in this state. The VR_TT# signal will be used to change the CPU operation and decrease the power consumption. When the temperature drops down, the NTC thermistor voltage will go up. If NTC voltage increases to above 1.24V, the comparator will flip back. The external resistance difference in these two conditions is shown in Equation 49:
1.24V 1.20V --------------- - --------------- = 2.96k 54A 60A (EQ. 49)
Layout Guidelines
Table 6 shows the layout considerations. The designators refer to the reference design shown in Figure 31.
TABLE 6. LAYOUT CONSIDERATION PIN EP NAME GND LAYOUT CONSIDERATION Create analog ground plane underneath the controller and the analog signal processing components. Don't let the power ground plane overlap with the analog ground plane. Avoid noisy planes/traces (e.g.: phase node) from crossing over/overlapping with the analog plane. No special consideration No special consideration Place the RBIAS resistor (R16) in general proximity of the controller. Low impedance connection to the analog ground plane. No special consideration The NTC thermistor (R9) needs to be placed close to the thermal source that is monitor to determine thermal throttling. Usually it's placed close to phase-1 high-side MOSFET. Place the capacitor (C4) across VW and COMP in close proximity of the controller Place the compensator components (C3, C5, C6 R7, R11, R10 and C11) in general proximity of the controller.
1 2 3
PGOOD PSI# RBIAS
One needs to properly select the NTC thermistor value such that the required temperature hysteresis correlates to 2.96k resistance change. A regular resistor may need to be in series with the NTC thermistor to meet the threshold voltage values. For example, given Panasonic NTC thermistor with B = 4700, the resistance will drop to 0.03322 of its nominal at +105C, and drop to 0.03956 of its nominal at +100C. If the required temperature hysteresis is +105C to +100C, the required resistance of NTC will be as shown in Equation 50:
2.96k ----------------------------------------------------- = 467k ( 0.03956 - 0.03322 ) (EQ. 50)
4 5
VR_TT# NTC
6 7 8
VW COMP FB
30
FN7557.1 March 18, 2010
ISL62883C
TABLE 6. LAYOUT CONSIDERATION (Continued) PIN 9 NAME LAYOUT CONSIDERATION ISEN3/FB2 For ISEN3 function, capacitor C7 decouples it to VSUM-, then through capacitor C20 to GND. Keep the decoupling path short and minimize the loop impedance. For FB2 function, a capacitor connects this pin to the COMP pin. Put the capacitor in general proximity of the controller. ISEN2 Capacitor C9 decouples it to VSUM-, then through capacitor C20 to GND. Keep the decoupling path short and minimize the loop impedance. Capacitor C10 decouples it to VSUM-, then through capacitor C20 to GND. Keep the decoupling path short and minimize the loop impedance. Place the VSEN/RTN filter (C12, C13) in close proximity of the controller for good decoupling. Place the current sensing circuit in general proximity of the controller. Place C82 very close to the controller. Place NTC thermistors R42 next to phase-1 inductor (L1) so it senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signals traces in parallel fashion with decent width (>20mil). IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71 to the phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and R72 to the phase-2 side pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces. 24 25 26 27 PWM3 VCCP LGATE2 VSSP2 22 23 VSSP1 LGATE1 TABLE 6. LAYOUT CONSIDERATION (Continued) PIN 18 19 NAME IMON BOOT1 LAYOUT CONSIDERATION Place the filter capacitor (C21) close to the CPU. Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing PHASE1 trace to the phase-1 high-side MOSFET (Q2 and Q8) source pins instead of general phase-1 node copper. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing VSSP1 to the phase-1 low-side MOSFET (Q3 and Q9) source pins instead of general power ground plane for better performance. No special consideration. A capacitor (C22) decouples it to GND. Place it in close proximity of the controller. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing VSSP2 to the phase-2 low-side MOSFET (Q5 and Q1) source pins instead of general power ground plane for better performance. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing PHASE2 trace to the phase-2 high-side MOSFET (Q4 and Q10) source pins instead of general phase-2 node copper. Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. No special consideration. No special consideration.
20 21
UGATE1 PHASE1
10
11
ISEN1
12 13 14 15
VSEN RTN ISUMISUM+
28 29
PHASE2 UGATE2
30
BOOT2
31~3 7 38 39 40 Other
VID0~6 VR_ON
Inductor
Inductor
DPRSLPVR No special consideration. CLK_EN# No special consideration. Phase Node Minimize phase node copper area. Don't let the phase node copper overlap with/getting close to other sensitive traces. Cut the power ground plane to avoid overlapping with phase node copper. Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C27, C33, Q2, Q8, Q3 and Q9).
Vias Current-Sensing Traces
16 17 VDD VIN
Current-Sensing Traces
Other
A capacitor (C16) decouples it to GND. Place it in close proximity of the controller. A capacitor (C17) decouples it to GND. Place it in close proximity of the controller.
31
FN7557.1 March 18, 2010
VIN VID0 IN VID1 IN VID2 IN VID3 IN VID4 IN VID5 IN VID6 IN VR_ON IN DPRSLPVR IN CLK_EN# OUT +3.3V
IN
IN
10UF C34
10UF
56UF C25
56UF
C28
C24
IRF7821
DNP
Q4
Q10 L2
270UF
270UF
270UF
C39
C52
C57
3.65K
R65
R72
R23 1.91K
10K R90
0
0.22UF
Q5
Q11
40 39 38 37 36 35 34 33 32 31
1
10UF
10UF
10UF
C44
R57
C31
IRF7832
IRF7832
10UF
270UF
0.36UH
OUT
VCORE
10UF 10UF
CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0
1.91K
R19
VSUM+
10UF C33
10UF
C27
PSI# +1.1V
IN IN
VSUM-
ISEN2
C41
PGOOD OUT
10UF
10UF
10UF
R12
499
C49
C50
C54
C55
C56
------R4
DNP ------R6
---- OPTIONAL
VR_TT# OUT
R16 R8 147K R9
2 3 4 5 6 7 8 9 10
PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2 EP U6 ISL62883C
BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1
IRF7821
DNP
29 28 27 26 25 24 23 22 21
IN
Q2
Q8 L1
8.66K
10UF
10UF
10UF
10UF 10UF
C59 C66 C74
1
30
10UF
1000PF
10UF
TBD
3.65K
------------C83 R110
560PF 2.37K -------------
------- OPTIONAL
C6 C3
NTC TBD
C4
+5V
R56 0
C30 0.22UF
IRF7832
IRF7832
0.36UH 10K R88 R71
Q3
Q9
R63
1
10UF
10UF
10UF
10UF
R10 R7
C11
VSUM+
0.22UF
0.22UF
0.22UF
150PF 324K ---ISEN3 IN ISEN2 IN ISEN1 IN C7
10UF C35
10UF
C29
2.37K
41
ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1
IRF7821
DNP
Q6
Q12 L3
IRF7832 IRF7832
11 12 13 14 15 16 17 18 19 20
ISEN1
C22
1UF
R11
VSUM-
39PF
536
390PF
10UF
C67
C68
C72
C73
C71
10UF
C63
C64
C60
C65
C61
10UF
10UF
C40
C42
C43
C47
C48
OUT
OUT
OUT
C10
C9
R50
0.22UF
R67
R73
C16
1UF C17
10K R92
1
0
3.65K
C21
0
IN
7.87K
1
0.047UF
----C12
VSUM+
VSUM-
ISEN3
10
IN IN
10K 2.61K NTC
VCORE
1000PF 330PF -----
0.039UF
0.47UF
R41
11K
C82
C18
R38
-----> R42
C13
0.1UF
----
----
C20
C26
820PF 100 ------------OPTIONAL
FIGURE 30. 3-PHASE CPU APPLICATION REFERENCE DESIGN
1UF
32
FN7557.1 March 18, 2010
OUT
OUT
OUT
ISL62883C
R20
R37 R40
OUT IN
IMON
R58 0
C32 0.22UF Q7 Q13
LAYOUT NOTE: ROUTE UGATE1 TRACE IN PARALLEL WITH THE PHASE1 TRACE GOING TO THE SOURCE OF Q2 AND Q8 ROUTE LGATE1 TRACE IN PARALLEL WITH THE VSSP1 TRACE GOING TO THE SOURCE OF Q3 AND Q9 SAME RULE APPLIES TO OTHER PHASES
+5V VIN
0.36UH
IN
R17
OPTIONAL -------
IN IN
VSSSENSE VSUM+
U3 UGATE BOOT PHASE FCCM VCC LGATE
OUT
OUT
OUT
VCCSENSE VSSSENSE
R18 10
R30
604 ------------C81 R109
IN
VSUM-
PWM GND
IN
+5V
PLACE NEAR L1
ISL6208
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VR_ON DPRSLPVR +3.3V
IN IN IN IN IN IN IN IN IN IN
1.91K
R19
CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0
VIN
IN
10UF C33
PGOOD +1.1V
OUT IN
10UF
IRF7821
------------
499 -------
R12
OPTIONAL -----
56UF
C27
C24
PGOOD R16 PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2 EP R20 U6 ISL62883C
BOOT2 UGATE2 PHASE2
Q2 L1
------R4
DNP ------R6
C22
1UF
220UF 7MOHM
8.66K
1000PF
----
22UF
22UF
10UF
C40
C54
C55
C56
C59
DNP
DNP
C60
DNP
----
DNP DNP ------------
C4
VCCP PWM3 LGATE1 VSSP1 PHASE1
IN
+5V
Q3
Q9
--------
DNP DNP --------
C83 R110
OPTIONAL ---C3
C6
R10 R7 R11
C11
47PF
2.37K 390PF 3.48K
----
390PF
261K
ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1
DNP
C41
C61
C39
C52
LGATE2
10UF
IRF7832
IRF7832
220UF 7MOHM
----C12
1000PF 330PF -----
R50
0.22UF
C13
C16
VSSSENSE
IN
R18 10
1UF C17
0
C21
IN
7.15K
----
1
R40
IN
0.047UF
10K 2.61K NTC
0.033UF
0.27UF
R41
R30
0.1UF
----
----
C20
1.07K -----------C81 R109
DNP DNP -----------OPTIONAL
PLACE NEAR L1
FIGURE 31. 1-PHASE GPU APPLICATION REFERENCE DESIGN
-----> R42
11K
C82
C18
R38
33
FN7557.1 March 18, 2010
OPTIONAL ---- VR_TT#
IN
47.5K ------R8 R9
VSSP2
0.56UH 1.3MOHM
OUT
VCORE
ISL62883C
VCORE
IN
R17 10
IN
OPTIONAL ----
0
R56 0 R37
C30 0.22UF
OUT
VCCSENSE
IMON
+5V VIN
LAYOUT NOTE:
IN
R63
VSSSENSE
1.82K
ROUTE UGATE TRACE IN PARALLEL WITH THE PHASE TRACE GOING TO THE SOURCE OF Q2 ROUTE LGATE TRACE IN PARALLEL WITH THE VSSP TRACE GOING TO THE SOURCE OF Q3
ISL62883C
1-PHASE GPU Application Reference Design Bill of Materials
QTY 1 1 1 0 2 2 1 1 1 1 2 1 2 1 2 REFERENCE C11 C12 C13 C15 C16, C22 C17, C30 C18 C20 C21 C24 C27,C33 C3 C39, C52 C4 C40, C41 VALUE DESCRIPTION MANUFACTURER GENERIC GENERIC GENERIC PART NUMBER H1045-00391-16V10 H1045-00331-16V10 H1045-00102-16V10 PACKAGE SM0603 SM0603 SM0603 390pF Multilayer Cap, 16V, 10% 330pF Multilayer Cap, 16V, 10% 1000pF Multilayer Cap, 16V, 10% DNP 1F Multilayer Cap, 16V, 20% GENERIC GENERIC GENERIC GENERIC GENERIC SANYO GENERIC GENERIC PANASONIC GENERIC TAIYO MURATA Kyocera TDK TAIYO MURATA Kyocera TDK GENERIC GENERIC H1045-00105-16V20 H1045-00224-25V10 H1045-00274-16V10 H1045-00104-16V10 H1045-00473-16V10 25SP56M H1065-00106-25V20 H1045-00391-16V10 EEXSX0D221E7 H1045-00102-16V10 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 CASE-CC SM1206 SM0603
0.22F Multilayer Cap, 25V, 10% 0.27F Multilayer Cap, 16V, 10% 0.1F Multilayer Cap, 16V, 10%
0.047F Multilayer Cap, 16V, 10% 56F 10F Radial SP Series Cap, 25V, 20% Multilayer Cap, 25V, 20%
390pF Multilayer Cap, 16V, 10% 220F SPCAP, 2V, 7M 1000pF Multilayer Cap, 16V, 10% 22F Multilayer Cap, 6.3V, 20%
SM0805 JMK212BJ226MG-T GRM21BC80J226M CM21X5R226M04AT C2012X5R0J226MT009N SM0805 JMK212BJ106MG-T GRM21BR60J106ME19 CM21X5R106M06AT C2012X5R0J106MT009N H1045-00470-16V10 H1045-00333-16V10 SM0603 SM0603
2
C54, C55
10F
Multilayer Cap, 6.3V, 20%
1 1 0 1 1 2 1 1 1 2 1 0 3 1 1 1 1 1 1
C6 C82 C56, C59-C61, C81, C83 L1 Q2 Q3, Q9 R10 R11 R16 R17, R18 R19 R26 R20, R40, R56 R30 R37 R38 R41 R42 R50
47pF
Multilayer Cap, 16V, 10%
0.033F Multilayer Cap, 16V, 10% DNP
0.56H Inductor, Inductance 20%, DCR 7% PANASONIC N-Channel Power MOSFET N-Channel Power MOSFET 2.37k 3.48k 47.5k 10 1.91k DNP 0 1.07k 1 11k 2.61k Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% GENERIC GENERIC GENERIC GENERIC GENERIC PANASONIC GENERIC Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% IR IR GENERIC GENERIC GENERIC GENERIC GENERIC
ETQP4LR56AFC IRF7821 IRF7832 H2511-02371-1/16W1 H2511-03481-1/16W1 H2511-04752-1/16W1 H2511-00100-1/16W1 H2511-01911-1/16W1
10mmx10mm PWRPAKSO8 PWRPAKSO8 SM0603 SM0603 SM0603 SM0603 SM0603
H2511-00R00-1/16W1 H2511-01071-1/16W1 H2511-01R00-1/16W1 H2511-01102-1/16W1 H2511-02611-1/16W1 ERT-J1VR103J H2511-07151-1/16W1
SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603
10k NTC Thermistor, 10k NTC 7.15k Thick Film Chip Resistor, 1%
34
FN7557.1 March 18, 2010
ISL62883C
1-PHASE GPU Application Reference Design Bill of Materials (Continued)
QTY 1 1 1 0 1 REFERENCE R6 R63 R7 R109, R110, R4, R8, R9 U6 VALUE 8.66k 1.82k 261k DNP IMVP-6.5 PWM Controller INTERSIL ISL62883CHRTZ QFN-40 DESCRIPTION Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% MANUFACTURER GENERIC GENERIC GENERIC PART NUMBER H2511-08661-1/16W1 H2511-01821-1/16W1 H2511-02613-1/16W1 PACKAGE SM0603 SM0805 SM0603
2-PHASE CPU Application Reference Design Bill of Materials
QTY 1 1 1 1 3 1 1 8 2 6 1 4 REFERENCE C11 C12 C13 C15 C16, C22, C26 C18 C20 C21, C7, C9, C10, C17, C30, C31, C32 C24, C25 C27, C28, C29, C33, C34, C35 C3 C39, C44, C52, C57 VALUE 390pF 330pF DESCRIPTION Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC PART NUMBER H1045-00391-16V10 H1045-00331-16V10 H1045-00102-16V10 H1045-00103-16V10 H1045-00105-16V20 H1045-00474-16V10 H1045-00104-16V10 H1045-00224-16V10 25SP56M H1065-00106-25V20 H1045-00151-16V10 EEXSX0D471E4 T520V277M2R5A(1)E4R 5-6666 H1045-00102-16V10 SM0603 PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 CASE-CC SM1206 SM0603
1000pF Multilayer Cap, 16V, 10% 0.01F Multilayer Cap, 16V, 10% 1F Multilayer Cap, 16V, 20%
0.47F Multilayer Cap, 16V, 10% 0.1F Multilayer Cap, 16V, 10%
0.22F Multilayer Cap, 16V, 10% 56F 10F 150pF 270F
Radial SP Series Cap, 25V, 20% SANYO Multilayer Cap, 25V, 20% Multilayer Cap, 16V, 10% SPCAP, 2V, 4M POLYMER CAP, 2.5V, 4.5M GENERIC GENERIC PANASONIC KEMET GENERIC TAIYO MURATA Kyocera TDK GENERIC GENERIC GENERIC GENERIC NEC-TOKIN PANASONIC IR IR
1 24
C4 C40-C43, C47-C50, C53-C56, C59-C69, C78
1000pF Multilayer Cap, 16V, 10% 10F Multilayer Cap, 6.3V, 20%
SM0805 JMK212BJ106MG-T GRM21BR60J106ME19 CM21X5R106M06AT C2012X5R0J106MT009N H1045-00390-16V10 H1045-00821-16V10 H1045-00393-16V10 H1045-00561-16V10 MPCH1040LR36 ETQP4LR36AFC IRF7821 IRF7832 SM0603 SM0603 SM0603 SM0603 10mmx10mm PWRPAKSO8 PWRPAKSO8
1 1 1 1 3 3 6 3 1 1 1 1
C6 C81 C82 C83 L1, L2, L3 Q2, Q4, Q6 Q3, Q5, Q7, Q9, Q11, Q13 Q8, Q10, Q12 R10 R109 R11 R110
39pF 820pF
Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10%
0.039F Multilayer Cap, 16V, 10% 560pF Multilayer Cap, 16V, 10%
0.36H Inductor, Inductance 20%, DCR 5% N-Channel Power MOSFET N-Channel Power MOSFET DNP 536 100 2.37k 2.37k Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1%
GENERIC GENERIC GENERIC GENERIC
H2511-05360-1/16W1 H2511-01000-1/16W1 H2511-02371-1/16W1 H2511-02371-1/16W1
SM0603 SM0603 SM0603 SM0603
35
FN7557.1 March 18, 2010
ISL62883C
2-PHASE CPU Application Reference Design Bill of Materials (Continued)
QTY 1 1 2 4 1 1 5 1 4 1 1 1 1 1 1 3 2 1 1 1 REFERENCE R12 R16 R17, R18 R19, R71, R72, R73 R23 R26 R20, R40, R56, R57, R58 R30 R37, R88, R90, R92 R38 R4 R41 R42 R50 R6 R63, R65, R67 R8, R9 R7 U3 U6 VALUE 499 147k 10 10k 1.91k 82.5 0 604 1 11k DNP 2.61k Thick Film Chip Resistor, 1% GENERIC PANASONIC GENERIC GENERIC GENERIC H2511-02611-1/16W1 ERT-J1VR103J H2511-07871-1/16W1 H2511-08662-1/16W1 H2511-03651-1/16W1 SM0603 SM0603 SM0603 SM0603 SM0805 DESCRIPTION Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC PART NUMBER H2511-04990-1/16W1 H2511-01473-1/16W1 H2511-00100-1/16W1 H2511-01002-1/16W1 H2511-01911-1/16W1 H2511-082R5-1/16W1 H2511-00R00-1/16W1 H2511-06040-1/16W1 H2511-01R00-1/16W1 H2511-01102-1/16W1 PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603
10k NTC Thermistor, 10k NTC 7.87k 8.66k 3.65k DNP 324k Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1%
GENERIC
H2511-03243-1/16W1 ISL6208CBZ ISL62883CHRTZ
SM0603 SOIC8_150_50 QFN-40
Synchronous Rectified MOSFET INTERSIL Driver IMVP-6.5 PWM Controller INTERSIL
36
FN7557.1 March 18, 2010
ISL62883C
Typical Performance
92 90 88 EFFICIENCY(%) 86 84 82 80 78 76 74 72 70 0 5 10 15 20 25 30 35 40 45 50 55 60 65 VIN = 8V VOUT (V) VIN = 12.6V VIN = 19V 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0 5 10 15 20 25 30 35 40 IOUT (A) 45 50 55 60 65
IOUT (A)
FIGURE 32. 3-PHASE CCM EFFICIENCY, VID = 1.075V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 33. 3-PHASE CCM LOAD LINE, VID = 1.075V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
95 90 EFFICIENCY (%) 85 80 75 70 65 60 0 1 2 3 4 5 6 89 IOUT(A) 7 10 11 12 13 14 15 VIN = 12.6V VIN = 19V VOUT (V) VIN = 8V 0.885 0.875 0.865 0.855 0.845 0.835 0.825 0 1 2 3 4 5 6 789 IOUT (A) 10 11 12 13 14 15
FIGURE 34. 2-PHASE CCM EFFICIENCY, VID = 0.875V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 35. 2-PHASE CCM LOAD LINE, VID = 0.875V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
95 0.885 90
EFFICIENCY (%)
85 80 75 70 65 60 0.1
VIN = 8V VOUT (V) VIN = 12.6V VIN = 19V 1 IOUT (A) 10 100
0.875 0.865 0.855 0.845 0.835 0.825 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IOUT (A)
FIGURE 36. 1-PHASE DEM EFFICIENCY, VID = 0.875V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 37. 1-PHASE DEM LOAD LINE, VID = 0.875V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
37
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ISL62883C
Typical Performance (Continued)
FIGURE 38. SOFT-START, VIN = 19V, IO = 0A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
FIGURE 39. SHUT DOWN, VIN = 19V, IO = 1A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
FIGURE 40. CLK_EN# DELAY, VIN = 19V, IO = 2A, VID = 1.5V, Ch1: PHASE1, Ch2: VO, Ch3: IMON, Ch4: CLK_EN#
FIGURE 41. PRE-CHARGED START UP, VIN = 19V, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3: IMON, Ch4: VR_ON
1000 900 IMON-VSSSENSE (mV) 800 700 600 500 400 300 200 100 0 0 5 10 15 TARGET VIN = 12V VIN = 8V 20 25 30 IOUT (A) 35 40 45 50 VIN = 19V
FIGURE 42. STEADY STATE, VIN = 19V, IO = 51A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
FIGURE 43. IMON, VID = 1.075V
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ISL62883C
Typical Performance (Continued)
FIGURE 44. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 12V, SV CLARKSFIELD CPU TEST CONDITION: VID = 0.95V, IO = 12A/51A, di/dt = "FASTEST", LL = 1.9mW
FIGURE 45. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 12V, SV CLARKSFIELD CPU TEST CONDITION: VID = 0.95V, IO = 12A/51A, di/dt = "FASTEST", LL = 1.9mW
FIGURE 46. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 12V, SV CLARKSFIELD CPU TEST CONDITION: VID = 0.95V, IO = 12A/51A, di/dt = "FASTEST", LL = 1.9mW
FIGURE 47. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 12V, SV CLARKSFIELD CPU TEST CONDITION: VID = 0.95V, IO = 12A/51A, di/dt = "FASTEST", LL = 1.9mW
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Typical Performance (Continued)
FIGURE 48. 2-PHASE MODE LOAD INSERTION RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, 3-PHASE CONFIGURATION, PSI# = 0, DPRSLPVR = 0, VIN = 12V, VID = 0.875V, IO = 4A/17A, di/d = "FASTEST
FIGURE 49. 2-PHASE MODE LOAD INSERTION RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, 3-PHASE CONFIGURATION, PSI# = 0, DPRSLPVR=0, VIN = 12V, VID = 0.875V, IO = 4A/17A, di/dt = "FASTEST"
FIGURE 50. PHASE ADDING/DROPPING (PSI# TOGGLE), IO = 15A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
FIGURE 51. DEEPER SLEEP MODE ENTRY/EXIT, IO = 1.5A, HFM VID = 1.075V, LFM VID = 0.875V, DEEPER SLEEP VID = 0.875V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
FIGURE 52. VID ON THE FLY, 1.075V/0.875V, 3-PHASE CONFIGURATION, PSI# = 1, DPRSLPVR=0, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
FIGURE 53. VID ON THE FLY, 1.075V/0.875V, 3-PHASE CONFIGURATION, PSI# = 0, DPRSLPVR=0, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
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Typical Performance (Continued)
FIGURE 54. VID ON THE FLY, 1.075V/0.875V, 3-PHASE CONFIGURATION, PSI# = 0, DPRSLPVR = 1, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
FIGURE 55. VID ON THE FLY, 1.075V/0.875V, 3-PHASE CONFIGURATION, PSI# = 1, DPRSLPVR = 1, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: PHASE3
Phase Margin
Gain
FIGURE 56. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION ENABLED, VIN = 12V, SV CLARKSFIELD CPU TEST CONDITION: VID = 0.95V, IO = 12A/51A, di/dt = "FASTEST", LL = 1.9mW, Ch1: LGATE1, Ch2: VO, Ch3: LGATE2, Ch4: ISL6208 LGATE
FIGURE 57. REFERENCE DESIGN LOOP GAIN T2(s) MEASUREMENT RESULT
5.0 4.5 4.0 3.5 Z(f) (m) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1k 100k 10k FREQUENCY (Hz) 1M PSI# = 1, DPRSLPVR = 0, 3-PHASE CCM PSI# = 0, DPRSLPVR = 0, 2-PHASE CCM
FIGURE 58. 1.55V OVP, Ch1: PHASE1, Ch2: VO, Ch3: LGATE1
FIGURE 59. REFERENCE DESIGN FDIM RESULT
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Typical Performance (Continued)
FIGURE 60. 1-PHASE GPU MODE SOFT-START, DPRSLPVR=0, VIN = 8V, IO = 0A, VID = 1.2375V, Ch1: PHASE1, Ch2: VO
FIGURE 61. 1-PHASE GPU MODE SHUT DOWN, VIN = 8V, IO = 1A, VID = 1.2375V, Ch1: PHASE1, Ch2: VO
FIGURE 62. 1-PHASE GPU MODE VID TRANSITION, DPRSLPVR=0, IO = 2A, VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
FIGURE 63. 1-PHASE GPU MODE VID TRANSITION, DPRSLPVR=1, IO = 2A, VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL62883C To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 42
FN7557.1 March 18, 2010
ISL62883C
Package Outline Drawing
L40.5x5
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/07
4X 3.60 5.00
A
B
36X 0.40
6 PIN 1 INDEX AREA
PIN #1 INDEX AREA
6
5.00
(4X)
0.15
TOP VIEW
40X 0.4 0 .1
BOTTOM VIEW
b
0.20
0.10 M
3.50
C
AB
PACKAGE OUTLINE
0.40
0.750
SEE DETAIL "X" // 0.10 C C BASE PLANE SEATING PLANE 0.08 C
SIDE VIEW
0.050
5.00
3.50
(36X 0 ..40) 0.2 REF
C
5
(40X 0.20)
0.00 MIN 0.05 MAX
(40X 0.60)
DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.27mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
43
FN7557.1 March 18, 2010

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