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8Mbit 1.8V SPI Serial Flash
SST25WF080
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
FEATURES:
* Single Voltage Read and Write Operations - 1.65-1.95V * Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 * High Speed Clock Frequency - 75 MHz * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Ultra-Low Power Consumption: - Active Read Current: 2 mA (typical @ 33 MHz) - Standby Current: 5 A (typical) * Flexible Erase Capability - Uniform 4 KByte sectors - Uniform 32 KByte overlay blocks - Uniform 64 KByte overlay blocks * Fast Erase and Byte-Program: - Chip-Erase Time: 35 ms (typical) - Sector-/Block-Erase Time: 18 ms (typical) - Byte-Program Time: 14 S (typical) * Auto Address Increment (AAI) Programming - Decrease total chip programming time over Byte-Program operations * End-of-Write Detection - Software polling the BUSY bit in Status Register - Busy Status readout on SO pin * Reset Pin (RST#) or Programmable Hold Pin (HOLD#) option - Hardware Reset pin as default - Hold pin option to suspend a serial sequence without deselecting the device * Write Protection (WP#) - Enables/Disables the Lock-Down function of the status register * Software Write Protection - Write protection through Block-Protection bits in status register * Temperature Range - Industrial: -40C to +85C * Packages Available - 8-lead SOIC (150 mils) - 8-bump XFBGA * All devices are RoHS compliant
PRODUCT DESCRIPTION
The SST25WF080 is a member of the Serial Flash 25 Series family and features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. SST25WF080 SPI serial flash memory is manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST25WF080 significantly improves performance and reliability, while lowering power consumption. The device writes (Program or Erase) with a single power supply of 1.65-1.95V for SST25WF080. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25WF080 is offered in both an 8-lead, 150 mils SOIC package and an 8-bump XFBGA package. See Figures 2 and 3 for the pin assignments.
(c)2010 Silicon Storage Technology, Inc. S71203-03-000 04/10 1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
Address Buffers and Latches
X - Decoder
SuperFlash Memory
Y - Decoder
Control Logic
I/O Buffers and Data Latches
Serial Interface
CE#
SCK
SI
SO
WP#
RST#/HOLD#
1203 F01.0
Note: In AAI mode, the SO pin functions as an RY/BY# pin when configured as a ready/busy status pin. See "End-of-Write Detection" on page 12 for more information.
FIGURE 1: Functional Block Diagram
(c)2010 Silicon Storage Technology, Inc.
S71203-03-000
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
PIN DESCRIPTION
Top View CE# SO WP# VSS 1 2 3 4 8 7 6 5 VDD RST#/HOLD# SCK SI
1203.25WF 08-soic-P0.0
FIGURE 2: Pin Assignment for 8-Lead SOIC
Top View (Balls Facing Down)
2
SI SCK
RST#/ HOLD#
VDD CE#
1
VSS WP# SO
A
B
C
D
1328.25WF 8-xfbga P1.0
FIGURE 3: Pin Assignment for 8-bump XFBGA TABLE 1: Pin Description
Symbol SCK Pin Name Serial Clock Functions To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See "End-of-Write Detection" on page 12 for more information. The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. To reset the operation of the device and the internal logic. The device powers on with RST# pin functionality as default. To temporarily stop serial communication with SPI Flash memory while device is selected. This is selected by an instruction sequence; see "Reset/Hold Mode" on page 5. To provide power supply voltage: 1.65-1.95V for SST25WF080
T1.0 1203
SI SO
Serial Data Input Serial Data Output
CE# WP# RST#/HOLD#
Chip Enable Write Protect Reset Hold
VDD VSS
Power Supply Ground
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
MEMORY ORGANIZATION
The SST25WF080 SuperFlash memory arrays are organized in uniform 4 KByte sectors with 16 KByte, 32 KByte, and 64 KByte overlay erasable blocks. The SST25WF080 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 4, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25WF080 are accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
CE#
MODE 3 MODE 3 MODE 0
SCK SI SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1203 F03.0
HIGH IMPEDANCE
FIGURE 4: SPI Protocol
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected option where an Enable-Hold instruction enables the Hold mode. Once selected as a hold pin (HOLD#), the RST#/HOLD# pin will be configured as a HOLD# pin, and goes back to RST# pin only after a poweroff and power-on sequence. Reset If the RST#/HOLD# pin is used as a reset pin, RST# pin provides a hardware method for resetting the device. Driving the RST# pin high puts the device in normal operating mode. The RST# pin must be driven low for a minimum of TRST time to reset the device. The SO pin is in high impedance state while the device is in reset. A successful reset will reset the status register to its power-up state. See Table 4 for default power-up modes. A device reset during an active Program or Erase operation aborts the operation and data of the targeted address range may be corrupted or lost due to the aborted erase or program operation. The device exits AAI Programming Mode in progress and places the SO pin in high impedance state.
CE# TRECR TRECP TRECE SCK TRST RST# TRHZ SO
SI
1203 F04.0
FIGURE 5: Reset Timing Diagram TABLE 2: Reset Timing Parameters
Symbol TRST1 TRHZ TRECR TRECP TRECE Parameter Reset Pulse Width Reset to High-Z Output Reset Recovery from Read Reset Recovery from Program Reset Recovery from Erase Min 100 107 100 10 1 Max Units ns ns ns s ms
T2.1203
1. For reset while in a Programming or Erase mode, the reset pulse must be >5s
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information Hold The Hold operation enables the hold pin functionality of the RST#/HOLD# pin. Once set to hold pin mode, the RST#/ HOLD# pin continues functioning as a hold pin until the device is powered off and then powered on. After a poweroff and power-on, the pin functionality returns to a reset pin (RST#) mode. See "Enable-Hold (EHLD)" on page 18 for detailed timing of the Hold instruction. In the hold mode, serial sequences underway with the SPI Flash memory are paused without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The Hold mode ends when the rising edge of the HOLD# signal coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits Hold mode when the SCK next reaches the active low state. See Figure 6 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, the device returns to standby mode. The device can then be re-initiated with the command sequences listed in Table 6. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 6 for Hold timing.
SCK
HOLD# Active Hold Active Hold Active
1203 F05.0
FIGURE 6: Hold Condition Waveform
Write Protection
SST25WF080 provide software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for the Block-Protection description. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled.
TABLE 3: Conditions to execute Write-Status-Register (WRSR) Instruction
WP# L L H BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed
T3.0 1203
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
Status Register
The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or TABLE 4: Software Status Register
Bit 0 1 2 3 4 5 6 Name BUSY WEL BP0 BP1 BP2 BP3 AAI Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP3, BP2, BP1 and BP0 are read-only bits 0 = BP3, BP2, BP1 and BP0 are read/writable Default at Power-up 0 0 1 1 1 0 0 Read/Write R R R/W R/W R/W R/W R
Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register.
7
BPL
0
R/W
T4.1 1203
Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A `1' for the Busy bit indicates the device is busy with an operation in progress. A `0' indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal Write-Enable-Latch memory. If the WEL bit is set to `1', it indicates the device is Write enabled. If the bit is set to `0' (reset), it indicates the device is not Write enabled and does not accept any Write (Program/Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: * * * * * Device Reset Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Write-Status-Register instructions
Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
* * * *
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information Block-Protection (BP3, BP2, BP1, BP0) The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area to be software protected against any memory Write (Program or Erase) operation, see Table 5. The Write-Status-Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is `0'. Chip-Erase can only be executed if Block-Protection bits are all `0'. After power-up, BP3, BP2, BP1 and BP0 are set to defaults. See Table 4 for defaults at power-up. Block Protection Lock-Down (BPL) When the WP# pin is driven low (VIL), it enables the BlockProtection-Lock-Down (BPL) bit. When BPL is set to `1', it prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is `Don't Care'. After power-up, the BPL bit is reset to `0'.
TABLE 5: Software Status Register Block Protection for SST25WF080
Status Register Bit Protection Level None 1 (Upper 16th Memory, Blocks 30 and 31) 2 (Upper 8th Memory, Blocks 28 to 31) 3 (Upper Quarter Memory, Blocks 24 to 31) 4 (Upper Half Memory, Blocks 16 to 31) 5 (Full Memory, Blocks 0 to 31) BP31 X X X X X X X X
1. X = Don't Care (Reserved), default is `0'. 2. Default at power-up for BP2, BP1 and BP0 is `11'.
Protected Memory Address BP02 0 1 0 1 0 1 0 1
T5.1 1203
BP22 0 0 0 0 1 1 1 1
BP12 0 0 1 1 0 0 1 1
8 Mbit None F0000H-FFFFFH E0000H-FFFFFH C0000H-FFFFFH 80000H-FFFFFH 00000H-FFFFFH
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
INSTRUCTIONS
Instructions are used to read, write (Erase and Program), and configure the SST25WF080. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The complete instructions are provided in Table 6. All instructions are synchronized off a high-to-low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first.
TABLE 6: Device Operation Instructions for SST25WF080
Instruction Read High-Speed Read Description Read Memory Read Memory at Higher Speed Op Code Cycle1 0000 0011b (03H) 0000 1011b (0BH) 0010 0000b (20H) 0101 0010b (52H) 1101 1000b (D8H) 0110 0000b (60H) or 1100 0111b (C7H) 0000 0010b (02H) 1010 1101b (ADH) 0000 0101b (05H) 0110 0000b (50H) 0000 0001b (01H) 0000 0110b (06H) 0000 0100b (04H) 1001 0000b (90H) or 1010 1011b (ABH) Address Cycle(s)2 3 3 3 3 3 0 3 3 0 0 0 0 0 3 0 0 0 0 Dummy Data Maximum Cycle(s) Cycle(s) Frequency 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 to 1 to 0 0 0 0 1 2 to 1 to 0 1 0 0 1 to 0 0 3 to 0
T6.0 1203
33 MHz
4 KByte Sector-Erase3 Erase 4 KByte of memory array 32 KByte Block-Erase4 Erase 32 KByte block of memory array 64 KByte Block-Erase5 Erase 64 KByte block of memory array Chip-Erase Byte-Program AAI-Word-Program6 RDSR7 EWSR8 WRSR WREN8 WRDI RDID9 EBSY DBSY JEDEC-ID EHLD
1. 2. 3. 4. 5. 6.
Erase Full Memory Array To Program One Data Byte Auto Address Increment Programming Read-Status-Register Enable-Write-Status-Register Write-Status-Register Write-Enable Write-Disable Read-ID
75 MHz
Enable SO to output RY/BY# sta- 0111 0000b (70H) tus during AAI programming Disable SO to output RY/BY# sta- 1000 0000b (80H) tus during AAI programming JEDEC ID read 1001 1111b (9FH) Enable HOLD# pin functionality of 1010 1010b (AAH) the RST#/HOLD# pin
One bus cycle is eight clock periods. Address bits above the most significant bit of each density can be VIL or VIH. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don't care but must be set either at VIL or VIH. 32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don't care but must be set either at VIL or VIH. 64 KByte Block-Erase addresses: use AMS-A16, remaining addresses are don't care but must be set either at VIL or VIH. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0 = 1. 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides backward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs. 9. Manufacturer's ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer's ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
Read (33 MHz)
The Read instruction, 03H, supports up to 33 MHz Read. The device outputs a data stream starting from the specified address location. The data stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer automatically increments until the highest memory address is reached. Once the highest memory address is reached, the address pointer automatically increments to the beginning (wraparound) of the address space. For example, for 8 Mbit density, once the data from the address location FFFFFH is read, the next output is from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits A23-A0. CE# must remain active low for the duration of the Read cycle. See Figure 7 for the Read sequence.
CE#
MODE 3
012345678
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI MSB SO
03
ADD. MSB HIGH IMPEDANCE
ADD.
ADD. N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT
1203 F06.0
FIGURE 7: Read Sequence
High-Speed-Read (75 MHz)
The High-Speed-Read instruction supporting up to 75 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-SpeedRead cycle. See Figure 8 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wraparound) of the address space. For example, for 2 Mbit density, once the data from address location 7FFFFH is read, the next output will be from address location 000000H.
CE# MODE 3 SCK MODE 0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SI MSB SO
0B
ADD.
ADD.
ADD.
X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT
1203 F07.0
HIGH IMPEDANCE
FIGURE 8: High-Speed-Read Sequence
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction. The ByteProgram instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 9 for the Byte-Program sequence.
CE#
MODE 3
012345
678
15 16
23 24
31 32
39
SCK
MODE 0
SI MSB SO
02
ADD.
ADD.
ADD.
DIN MSB LSB
HIGH IMPEDANCE
1203 F08.0
FIGURE 9: Byte-Program Sequence
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
Auto Address Increment (AAI) Word-Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when multiple bytes or the entire memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI Word Program operation. While within AAI Word Programming sequence, the only valid instructions are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users have three options to determine the completion of each AAI Word program cycle: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the software status register or wait TBP. Refer to End-Of-Write Detection section for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI Word Program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data are input sequentially, each one from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0) will be programmed into the initial address [A23-A1] with A0 = 0, the second byte of Data (D1) will be programmed into the initial address [A23-A1] with A0 = 1. CE# must be driven high before the AAI Word Program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. Check the busy status after WRDI to determine if the device is ready for any command. See Figures 12 and 13 for AAI Word programming sequence. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-EnableLatch bit (WEL = 0) and the AAI bit (AAI = 0). End-of-Write Detection There are three methods to determine completion of a program cycle during AAI Word programming: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the Software Status Register or wait TBP .
Hardware End-of-Write Detection The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the Serial Output (SO) pin to indicate Flash Busy status during AAI Word programming, as shown in Figure 10. The 8-bit command, 70H, must be executed prior to executing an AAI Word-Program instruction. Once an internal programming operation begins, asserting CE# will immediately drive the status of the internal flash status on the SO pin. A `0' indicates the device is busy and a `1' indicates the device is ready for the next instruction. De-asserting CE# will return the SO pin to tristate. The 8-bit command, 80H, disables the Serial Output (SO) pin to output busy status during AAI-Word-program operation, and re-configures SO as an output pin. In this state, the SO pin will function as a normal Serial Output pin. At this time, the RDSR command can poll the status of the Software Status Register. This is shown in Figure 11.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
70 HIGH IMPEDANCE
1203 F09.0
SO
FIGURE 10: Enable SO as Hardware RY/BY# during AAI Programming
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
80 HIGH IMPEDANCE
1203 F10.0
SO
FIGURE 11: Disable SO as Hardware RY/BY# during AAI Programming
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
CE#
0 78 15 16 23 24 31 32 39 40 47 0 78 15 16 23 0 78 15 16 23 0 7 0 78 15
MODE 3
SCK SI
MODE 0
AD
A
A
A
D0
D1
AD
D2
D3
AD
Dn-1 Last 2 Data Bytes
Dn
WRDI WDRI to exit AAI Mode
RDSR
Load AAI command, Address, 2 bytes data
SO
Check for Flash Busy Status to load next valid1 command
DOUT Wait TBP or poll Software Status register to load any command
Note:
1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming
1203 F11.0
FIGURE 12: Auto Address Increment (AAI) Word Program Sequence with Hardware End-of-Write Detection
Wait TBP or poll Software Status register to load next valid1 command
CE#
MODE 3
0
78
15 16 23 24
31 32 39 40 47
0
78
15 16 23
0
78
15 16 23
0
7
0
78
15
SCK SI
MODE 0
AD
A
A
A
D0
D1
AD
D2
D3
AD
Dn-1 Last 2 Data Bytes
Dn
WRDI WDRI to exit AAI Mode
RDSR
Load AAI command, Address, 2 bytes data SO Note: 1. Valid commands during AAI programming: AAI command or WRDI command
DOUT Wait TBP or poll Software Status register to load any command
1203 F12.0
FIGURE 13: Auto Address Increment (AAI) Word Program Sequence with Software End-of-Write Detection
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 14 for the Sector-Erase sequence.
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
20
ADD.
MSB
ADD.
ADD.
SO
HIGH IMPEDANCE
1203 F13.0
FIGURE 14: Sector-Erase Sequence
32-KByte Block-Erase
The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Significant Address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase. See Figure 15 for the Block-Erase sequences.
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
52
ADDR
MSB
ADDR
ADDR
SO
HIGH IMPEDANCE
1203 F14.0
FIGURE 15: 32-KByte Block-Erase Sequence
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8Mbit 1.8V SPI Serial Flash SST25WF080
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64-KByte Block-Erase
The Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23-A0]. Address bits [AMS-A16] (AMS = Most Significant Address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase. See Figure 16 for the Block-Erase sequences.
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
D8
ADDR
MSB
ADDR
ADDR
SO
HIGH IMPEDANCE
1203 F15.0
FIGURE 16: 64-KByte Block-Erase Sequence
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction is ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 17 for the Chip-Erase sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
60 or C7 HIGH IMPEDANCE
1203 F16.0
SO
FIGURE 17: Chip-Erase Sequence
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8Mbit 1.8V SPI Serial Flash SST25WF080
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Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction, 05H, allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 18 for the RDSR instruction sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK SI
MODE 0
05
MSB
SO
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out
1203 F17.0
FIGURE 18: Read-Status-Register (RDSR) Sequence
Write-Enable (WREN)
The Write-Enable (WREN) instruction, 06H, sets the WriteEnable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed. See Figure 19 for the WREN instruction sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
06 HIGH IMPEDANCE
1203 F18.0
SO
FIGURE 19: Write Enable (WREN) Sequence
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8Mbit 1.8V SPI Serial Flash SST25WF080
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Write-Disable (WRDI)
The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit and AAI to 0 disabling any new Write operations from occurring. The WRDI instruction will not terminate any programming operation in progress. Any program operation in progress may continue up to TBP after executing the WRDI instruction. CE# must be driven high before the WRDI instruction is executed. See Figure 20 for the WRDI instruction sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
04 HIGH IMPEDANCE
1203 F19.0
SO
FIGURE 20: Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Write-StatusRegister instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. See Figure 21 for EWSR instruction followed by WRSR instruction.
sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 21 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to `1'. When the WP# is low, the BPL bit can only be set from `0' to `1' to lock-down the status register, but cannot be reset from `1' to `0'. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1, BP2, and BP3 bits in the status register can all be changed. As long as BPL bit is set to `0' or WP# pin is driven high (VIH) prior to the lowto-high transition of the CE# pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to `1' to lock down the status register as well as altering the BP0, BP1, BP2, and BP3 bits at the same time. See Table 3 for a summary description of WP# and BPL functions.
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of the status register. CE# must be driven low before the command
CE#
MODE 3
01234567
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
MODE 0
SI MSB SO
50 or 06 MSB
01 HIGH IMPEDANCE
STATUS REGISTER IN 76543210 MSB
1203 F20.0
FIGURE 21: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence
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8Mbit 1.8V SPI Serial Flash SST25WF080
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Enable-Hold (EHLD)
The 8-bit command, AAH, Enable-Hold instruction enables the HOLD functionality of the RST#/HOLD# pin. CE# must remain active low for the duration of the Enable-Hold instruction sequence. CE# must be driven high before the instruction is executed. See Figure 22 for the Enable-Hold instruction sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
AA HIGH IMPEDANCE
1203 F21.0
SO
FIGURE 22: Enable-Hold Sequence
Read-ID
The Read-ID instruction identifies the manufacturer as SST and the device as SST25WF080. Use the Read-ID instruction to identify SST device when using multiple manufacturers in the same socket. See Table 7. The device information is read by executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the Read-ID instruction, the manufacturer's ID is located in address 000000H and the device ID is located in address 000001H. Once the device is in Read-ID mode, the manufacturer's and device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition on CE#. TABLE 7: Product Identification
Address Manufacturer's ID Device ID SST25WF080 000000H 000001H Data BFH 05H
T7.1203
CE#
MODE 3
012345678
15 16
23 24
31 32
39 40
47 48
55 56
63
SCK
MODE 0
SI
MSB
90 or AB
00
00
ADD
MSB
SO
HIGH IMPEDANCE
MSB
BF
Device ID
BF
Device ID
HIGH IMPEDANCE
Note: 1. The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. 2. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
1203 F22.0
FIGURE 23: Read-ID Sequence
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8Mbit 1.8V SPI Serial Flash SST25WF080
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JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as SST25WF080 and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer's ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. The Device ID is assigned by the manufacturer and contains the type of memory in the first byte and the memory capacity of the device in the second byte. See Figure 24 for the instruction sequence. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK
MODE 0
SI HIGH IMPEDANCE
9F
SO
BF
MSB MSB
25
05H
1203 F23.0
FIGURE 24: JEDEC Read-ID Sequence TABLE 8: JEDEC Read-ID Data-Out
Device ID Manufacturer's ID (Byte 1) BFH Memory Type (Byte 2) 25H Memory Capacity (Byte 3) 05H
T8.0 1203
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8Mbit 1.8V SPI Serial Flash SST25WF080
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ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range Industrial Ambient Temp -40C to +85C VDD 1.65-1.95V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
Power-Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 1.8V in less than 180 ms). If the VDD ramp rate is slower than 1V/100 ms, a hardware reset is required. The recommended VDD power-up to RESET# high time should be greater than 100 s to ensure a proper reset. See Table 9 and Figures 25 and 26 for more information. TABLE 9: Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE1 Parameter VDD Min to Read Operation VDD Min to Write Operation Minimum 100 100 Units s s
T9.0 1203
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TPU-READ VDD 0V RESET# VIH VDD min
TRECR CE#
1203 F37.0
Note: See Table 2 on page 5 for TRECR parameter.
FIGURE 25: Power-Up Reset Diagram
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8Mbit 1.8V SPI Serial Flash SST25WF080
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VDD
VDD Max Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device.
VDD Min TPU-READ TPU-WRITE
Device fully accessible
Time
1203 F27.0
FIGURE 26: Power-up Timing Diagram
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8Mbit 1.8V SPI Serial Flash SST25WF080
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DC Characteristics
TABLE 10: DC Operating Characteristics
Limits Symbol IDDR IDDR2 IDDW ISB ILI ILO VIL VIH VOL VOH Parameter Read Current Read Current Program and Erase Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VDD-0.2 0.7 VDD 0.2 Min Typ1 2 4 6 5 Max 5 9 10 20 1 1 0.3 Units mA mA mA A A A V V V V Test Conditions CE#=0.1 VDD/0.9 VDD@33 MHz, SO=open CE#=0.1 VDD/0.9VDD@75 MHz, SO=open CE#=VDD CE#=VDD, VIN=VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T10.0 1203
1. Value characterized, not fully tested in production.
TABLE 11: Capacitance (TA = 25C, f=1 Mhz, other pins open)
Parameter COUT CIN1
1
Description Output Pin Capacitance Input Capacitance
Test Condition VOUT = 0V VIN = 0V
Maximum 12 pF 6 pF
T11.0 1203
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: Reliability Characteristics
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T12.0 1203
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
AC Characteristics
TABLE 13: AC Operating Characteristics
Limits - 33 MHz Symbol FCLK
1
Limits - 75 MHz Min 6 6 Max 75 Units MHz ns ns 0.1 0.1 5 5 5 5 25 v/ns v/ns ns ns ns ns ns 7 0 2 4 6 6 6 6 ns ns ns ns ns ns ns ns 7 7 0 6 30 30 60 25 ns ns ns ns ms ms ms s
T13.2 1203
Parameter Serial Clock Frequency Serial Clock High Time Serial Clock Low Time Serial Clock Rise Time Serial Clock Fall Time CE# Active Setup Time CE# Active Hold Time CE# Not Active Setup Time CE# Not Active Hold Time CE# High Time CE# High to High-Z Output SCK Low to Low-Z Output Data In Setup Time Data In Hold Time HOLD# Low Setup Time HOLD# High Setup Time HOLD# Low Hold Time HOLD# High Hold Time HOLD# Low to High-Z Output HOLD# High to Low-Z Output Output Hold from SCK Change Output Valid from SCK Sector-Erase Block-Erase Chip-Erase Byte-Program
Min 13 13
Max 33
TSCKH TSCKL TSCKR TSCKF TCES2 TCEH2 TCHS2 TCHH TCPH TCHZ TCLZ TDS TDH THLS THHS THLH THHH THZ TLZ TOH TV TSE TBE TSCE TBP
3 2
0.1 0.1 12 12 10 10 50 20 0 5 5 10 10 15 10 20 20 0 12 30 30 60 25
1. Maximum clock frequency for Read instruction, 03H, is 33 MHz 2. Relative to SCK 3. AAI-Word Program TBP maximum specification is also at 25 s maximum time
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8Mbit 1.8V SPI Serial Flash SST25WF080
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TCPH CE# TCHH SCK TDS SI TDH TSCKR TSCKF TCES TCEH TCHS
MSB HIGH-Z
LSB HIGH-Z
1203 F24.0
SO
FIGURE 27: Serial Input Timing Diagram
CE# TSCKH SCK TCLZ SO TV SI
1203 F25.0
TSCKL
TOH MSB LSB
TCHZ
FIGURE 28: Serial Output Timing Diagram
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
CE# THHH SCK THLH THZ SO TLZ THLS THHS
SI
HOLD#
1203 F26.0
FIGURE 29: Hold Timing Diagram
VIHT VHT
INPUT REFERENCE POINTS
VHT
OUTPUT
VLT VILT
VLT
1203 F28.0
AC test inputs are driven at VIHT (0.9VDD) for a logic `1' and VILT (0.1VDD) for a logic `0'. Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 30: AC Input/Output Reference Waveforms
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
PRODUCT ORDERING INFORMATION
SST 25 WF XX XX XXX XXX - 75 - XX - 4I - SA - XX - XX F X Environmental Attribute E1 = non-Pb F2 = non-Pb / non-Sn contact (lead) finish: Nickel plating with Gold top (outer) layer Package Modifier A = 8 leads Package Type Z = XFBGA S = SOIC 150 mil body width Temperature Range I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Operating Frequency 75 = 75 MHz Device Density 080 = 8 Mbit Voltage W= 1.65-1.95V Product Series 25 = Serial Peripheral Interface flash memory
1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". 2. Environmental suffix "F" denotes non-Pb/non-SN solder. SST non-Pb/non-Sn solder devices are "RoHS Compliant".
Valid combinations for SST25WF080 SST25WF080-75-4I-SAF SST25WF080-75-4I-ZAE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information
PACKAGING DIAGRAMS
Pin #1 Identifier
TOP VIEW
SIDE VIEW
7 4 places
5.0 4.8 1.27 BSC
0.51 0.33
END VIEW
0.25 0.10 1.75 1.35 0.25 0.19 1.27 0.40 45 7 4 places
4.00 3.80 6.20 5.80
0 8
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
08-soic-5x6-SA-8
1mm
FIGURE 31: 8-lead Small Outline Integrated Circuit (SOIC) 200 mil body width (5mm x 8mm) SST Package Code: SA Note: For more information about the ZA package, including a copy of the package diagram, please contact your SST representative.
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8Mbit 1.8V SPI Serial Flash SST25WF080
Advance Information TABLE 14: Revision History
Number 00 01 Description Date Sep 2007 Apr 2009
* * * * * * * * *
Initial release of data sheet Revised Active Read Current, Standby Current, Chip-Erase Time, and Sector-/ Block-Erase Time in Features on page 1 Added a footnote to Table 2 Reset Timing Parameters Revised Table 6 on page 9 Revised Table 10 on page 23 Revised Table 13 on page 24 Revised Figure 12 and Figure 13 Revised Product Ordering Information and Valid Combinations Revised THLS, THHS, THLH, and THHH in Table 13 on page 24 from 5 ns to 6ns. Changed Standby Current: from 5 mA to 5 A in Features on page 1 Added the Z1A package Removed Z1AE package information Added ZAE package information Updated SST address information on page 29
02 03
* * * * *
May 2009 Apr 2010
Silicon Storage Technology, Inc. www.SuperFlash.com or www.sst.com
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