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| IPDH6N03LA G IPSH6N03LA G IPFH6N03LA G IPUH6N03LA G OptiMOS(R)2 Power-Transistor Features * Ideal for high-frequency dc/dc converters * Qualified according to JEDEC1) for target application * N-channel, logic level * Excellent gate charge x R DS(on) product (FOM) * Superior thermal resistance * 175 C operating temperature * Pb-free lead plating; RoHS compliant Product Summary V DS R DS(on),max (SMD version) ID 25 6 50 V m A Type IPDH6N03LA G IPFH6N03LA G IPSH6N03LA G IPUH6N03LA G Package Marking PG-TO252-3-11 H6N03LA PG-TO252-3-23 H6N03LA PG-TO251-3-11 H6N03LA PG-TO251-3-1 H6N03LA Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 C2) T C=100 C Pulsed drain current Avalanche energy, single pulse Reverse diode dv /dt Gate source voltage4) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 C T C=25 C3) I D=50 A, R GS=25 I D=50 A, V DS=20 V, di /dt =200 A/s, T j,max=175 C Value 50 50 350 150 6 20 71 -55 ... 175 55/175/56 mJ kV/s V W C Unit A Rev. 1.5 page 1 2008-04-14 IPDH6N03LA G IPSH6N03LA G Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area5) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=30 A V DS=25 V, V GS=0 V, T j=25 C V DS=25 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=30 A V GS=4.5 V, I D=30 A, IPD version V GS=10 V, I D=50 A V GS=10 V, I D=50 A, IPD version Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=50 A 25 1.2 1.6 0.1 Values typ. IPFH6N03LA G IPUH6N03LA G Unit max. 2.1 75 50 K/W 2 1 V A 35 10 10 8.2 8 5.2 5 1.3 69 100 100 10.2 10 6.2 6 S nA m 1) J-STD20 and JESD22 Current is limited by bondwire; with an R thJC=2.1 K/W the chip is able to carry 80 A. See figure 3 T j,max=150 C and duty cycle D <0.25 for V GS<-5 V 2) 3) 4) 5) 2 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.5 page 2 2008-04-14 IPDH6N03LA G IPSH6N03LA G Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics 6) Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total Gate plateau voltage Gate charge total, sync. FET Output charge Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 C V GS=0 V, I F=50 A, T j=25 C V R=15 V, I F=I S, di F/dt =400 A/s 0.93 Q gs Q g(th) Q gd Q sw Qg V plateau Q g(sync) Q oss V DS=0.1 V, V GS=0 to 5 V V DD=15 V, V GS=0 V V DD=15 V, I D=25 A, V GS=0 to 5 V 5.9 2.9 4.1 7.1 14 3.3 13 15 C iss C oss Crss t d(on) tr t d(off) tf V DD=15 V, V GS=10 V, I D=25 A, R G=2.7 V GS=0 V, V DS=15 V, f =1 MHz 1800 690 85 6 5.4 23 4.2 Values typ. IPFH6N03LA G IPUH6N03LA G Unit max. 2390 920 130 9 8 34 6.3 pF ns 7.8 3.8 6.1 10 19 17 20 nC V nC 50 350 1.2 A V Reverse recovery charge Q rr - - 10 nC 6) See figure 16 for gate charge parameter definition Rev. 1.5 page 3 2008-04-14 IPDH6N03LA G IPSH6N03LA G 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V IPFH6N03LA G IPUH6N03LA G 80 60 70 50 60 40 50 P tot [W] 40 I D [A] 0 50 100 150 200 30 30 20 20 10 10 0 0 0 50 100 150 200 T C [C] T C [C] 3 Safe operating area I D=f(V DS); T C=25 C; D =0 parameter: t p 1000 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 10 limited by on-state resistance 1 s 10 s 100 1 0.5 Z thJC [K/W] 100 s 0.2 I D [A] DC 1 ms 0.1 0.05 10 10 ms 0.1 0.02 0.01 single pulse 1 0.1 1 10 100 0.01 0 0 0 0 0 0 1 10-6 10-5 10-4 10-3 10-2 10-1 100 V DS [V] t p [s] Rev. 1.5 page 4 2008-04-14 IPDH6N03LA G IPSH6N03LA G 5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS 100 90 80 70 10 V 4.5 V IPFH6N03LA G IPUH6N03LA G 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS 20 18 4.1 V 3.2 V 3.5 V 3.8 V 4.1 V 16 14 I D [A] 3.8 V 50 40 3.5 V R DS(on) [m] 60 12 10 8 6 10 V 4.5 V 30 20 10 0 0 1 2 3 3.2 V 3V 2.8 V 4 2 0 0 20 40 60 80 100 V DS [V] I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 100 8 Typ. forward transconductance g fs=f(I D); T j=25 C 80 70 80 60 60 50 g fs [S] 40 20 175 C 25 C I D [A] 40 30 20 10 0 0 1 2 3 4 5 0 0 10 20 30 40 50 60 V GS [V] I D [A] Rev. 1.5 page 5 2008-04-14 IPDH6N03LA G IPSH6N03LA G 9 Drain-source on-state resistance R DS(on)=f(T j); I D=50 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS parameter: I D 12 2.5 IPFH6N03LA G IPUH6N03LA G 10 2 8 300 A 98 % R DS(on) [m] V GS(th) [V] 1.5 30 A 6 typ 1 4 2 0.5 0 -60 -20 20 60 100 140 180 0 -60 -20 20 60 100 140 180 T j [C] T j [C] 11 Typ. capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 104 1000 25 C Ciss 103 Coss 100 175 C 175 C, 98% C [pF] I F [A] 102 Crss 10 25 C, 98% 101 0 10 20 30 1 0.0 0.5 1.0 1.5 2.0 V DS [V] V SD [V] Rev. 1.5 page 6 2008-04-14 IPDH6N03LA G IPSH6N03LA G 13 Avalanche characteristics I AS=f(t AV); R GS=25 parameter: Tj(start) 100 IPFH6N03LA G IPUH6N03LA G 14 Typ. gate charge V GS=f(Q gate); I D=25 A pulsed parameter: V DD 12 15 V 10 100 C 150 C 25 C 5V 20 V 8 10 V GS [V] 1 10 100 1000 I AV [A] 6 4 2 1 0 0 5 10 15 20 25 30 t AV [s] Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA 16 Gate charge waveforms 30 V GS 28 Qg 27 V BR(DSS) [V] 26 24 V g s(th) 23 21 Q g(th) Q gs -60 -20 20 60 100 140 180 Q sw Q gd Q g ate 20 T j [C] Rev. 1.5 page 7 2008-04-14 IPDH6N03LA G IPSH6N03LA G Package Outline PG-TO252-3-11 IPFH6N03LA G IPUH6N03LA G Rev. 1.5 page 8 2008-04-14 IPDH6N03LA G IPSH6N03LA G Package Outline PG-TO252-3-23: Outline PG-TO252-3-23 IPFH6N03LA G IPUH6N03LA G Footprint: Rev. 1.5 page 9 2008-04-14 IPDH6N03LA G IPSH6N03LA G Package Outline PG-TO251-3-11 IPFH6N03LA G IPUH6N03LA G Rev. 1.5 page 10 2008-04-14 IPDH6N03LA G IPSH6N03LA G Package Outline PG-TO251-3-21 IPFH6N03LA G IPUH6N03LA G Rev. 1.5 page 11 2008-04-14 IPDH6N03LA G IPSH6N03LA G IPFH6N03LA G IPUH6N03LA G Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.5 page 12 2008-04-14 |
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