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ISL22424
Dual Digitally Controlled Potentiometer (XDCPTM)
Data Sheet May 31, 2007 FN6425.0
Low Noise, Low Power, SPI(R) Bus, 256 Taps
The ISL22424 integrates two digitally controlled potentiometers (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WRi) and a non-volatile Initial Value Register (IVRi) that can be directly written to and read by the user. The contents of the WRi control the position of the wiper. At power-up the device recalls the contents of the DCP's IVRi to the corresponding WRi. The ISL22424 also has 13 General Purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22424 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. Each DCP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* Two potentiometers in one package * 256 resistor taps * SPI serial interface with write/read capability * Daisy Chain Configuration * Shutdown mode * Non-volatile EEPROM storage of wiper position * 13 General Purpose non-volatile registers * High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T +55C * Wiper resistance: 70 typical @ 1mA * Standby current <4A max * Shutdown current <4A max * Dual power supply - VCC = 2.25V to 5.5V - V- = -2.25V to -5.5V * 10k, 50k or 100k total resistance * Extended industrial temperature range: -40C to +125C * 14 Ld TSSOP or 16 Ld QFN * Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER (NOTES 1, 2) ISL22424TFV14Z ISL22424TFR16Z ISL22424UFV14Z ISL22424UFR16Z ISL22424WFV14Z ISL22424WFR16Z NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-TK" suffix for 1,000 Tape and Reel option PART MARKING 22424TFVZ 22424TFRZ 22424UFVZ 22424UFRZ 22424WFVZ 22424WFRZ RESISTANCE OPTION (k) 100 100 50 50 10 10 TEMPERATURE RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 14 Ld TSSOP 16 Ld QFN 14 Ld TSSOP 16 Ld QFN 14 Ld TSSOP 16 Ld QFN PKG. DWG. # M14.173 L16.4x4A M14.173 L16.4x4A M14.173 L16.4x4A
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22424 Block Diagram
VCC VRH0 RH1
SCK SDI SDO CS SPI INTERFACE POWER UP, CONTROL AND STATUS LOGIC
WR0 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY
WR0 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY
NON-VOLATILE REGISTERS
GND
RW0
RL0
RW1
RL1
Pinouts
ISL22424 (14 LD TSSOP) TOP VIEW
RW1 RH0 RL0 RW0 RH1 RL1 RW1 NC 1 2 3 4 5 6 7 14 VCC 13 CS 12 SDI 11 GND 10 SCK 9 8 SDO VNC NC NC V1 2 3 4 5 SDO 6 SCK 7 GND 8 SDI
ISL22424 (16 LD QFN) TOP VIEW
RW0 13 12 RL0 11 RH0 10 VCC 9 CS RH1 14 RL1 15
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ISL22424 Pin Descriptions
TSSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 QFN PIN 11 12 13 14 15 16 1, 2, 3 4 5 6 7 8 9 10 EPAD* SYMBOL RH0 RL0 RW0 RH1 RL1 RW1 NC VSDO SCK GND SDI CS VCC "High" terminal of DCP0 "Low" terminal of DCP0 "Wiper" terminal of DCP0 "High" terminal of DCP1 "Low" terminal of DCP1 "Wiper" terminal of DCP1 No connection Negative power supply pin Data Output of the SPI serial interface SPI interface clock input Device ground pin Data Input of the SPI serial interface Chip Select active low input Positive power supply pin Exposed Die Pad internally connected to VDESCRIPTION
* Note: PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf
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Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V Voltage at any DCP pin with Respect to GND . . . . . . . . . . V- to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 16 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Full Industrial) . . . . . . . . . . . .-40C to +125C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25V to -5.5V Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option T option MIN TYP (NOTE 4) 10 50 100 -20 W option U, T option 85 45 V70 10/10/25 0.1 1 VCC 250 +20 MAX UNIT k k k % ppm/C ppm/C V pF A
PARAMETER RHi to RLi resistance
RHi to RLi resistance tolerance End-to-End Temperature Coefficient
VRH, VRL RW CH/CL/CW (Note 20) ILkgDCP INL (Note 9)
DCP terminal voltage Wiper resistance Potentiometer capacitance Leakage on DCP pins
VRHi and VRLi to GND RH - floating, VRL = V-, force Iw current to the wiper, IW = (VCC - VRL)/RTOTAL See Macro Model below. Voltage at pin from V- to VCC W option U, T option
VOLTAGE DIVIDER MODE (V- @ RLi; VCC @ RHi; measured at RWi, unloaded) Integral non-linearity -1.5 -1.0 -1.0 -0.5 0 0 -5 -2 -2 0.5 0.2 0.4 0.15 1 0.5 -1 -1 1.5 1.0 1.0 0.5 5 2 0 0 2 LSB (Note 5) LSB (Note 5) LSB (Note 5) LSB (Note 5) LSB (Note 5) LSB (Note 5) LSB (Note 5) ppm/C
DNL (Note 8)
Differential non-linearity Monotonic over all tap positions
W option U, T option
ZSerror (Note 6) FSerror (Note 7) VMATCH (Note 10)
Zero-scale error
W option U, T option
Full-scale error
W option U, T option
DCP to DCP matching
Wipers at the same tap position, the same voltage at all RH terminals and the same voltage at all RL terminals DCP register set to 80 hex
TCV Ratiometric temperature coefficient (Note 11, 20)
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Analog Specifications
SYMBOL fcutoff (Note 20) Over recommended operating conditions unless otherwise stated. (Continued) TEST CONDITIONS Wiper at midpoint (80hex) W option (10k) Wiper at midpoint (80hex) U option (50k) Wiper at midpoint (80hex) T option (100k) MIN TYP (NOTE 4) 1000 250 120 MAX UNIT kHz kHz kHz
PARAMETER -3dB cut off frequency
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 15) Integral non-linearity W option U, T option RDNL (Note 14) Differential non-linearity W option U, T option Roffset (Note 13) Offset W option U, T option RMATCH (Note 16) DCP to DCP matching Wipers at the same tap position with the same terminal voltages DCP register set between 32hex and FF hex -3 -1 -1.5 -0.5 0 0 -2 40 1.5 0.4 0.5 0.15 1 0.5 3 1 1.5 0.5 5 2 2 MI (Note 12) MI (Note 12) MI (Note 12) MI (Note 12) MI (Note 12) MI (Note 12) MI (Note 12) ppm/C
TCR Resistance temperature coefficient (Note 17, 20)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 PARAMETER VCC Supply Current (volatile write/read) TEST CONDITIONS VCC = 5.5V, V- = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) VCC = 2.25V, V- = -2.25V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) IV-1 V- Supply Current (volatile write/read) V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) ICC2 VCC Supply Current (non-volatile write/read) VCC = 5.5V, V- = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) VCC = 2.25V, V- = -2.25V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) IV-2 V- Supply Current (non-volatile write/read) V- Supply Current (non-volatile write/read) ISB VCC Current (standby) V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) VCC = +5.5V, V- = -5.5V @ +85C, SPI interface in standby state VCC = +5.5V, V- = -5.5V @ +125C, SPI interface in standby state VCC = +2.25V, V- = -2.25V @ +85C, SPI interface in standby state VCC = +2.25V, V- = -2.25V @ +125C, SPI interface in standby state -2.0 -1.0 -1.0 -0.5 MIN TYP (NOTE 4) 0.6 0.25 -0.3 -0.1 1.0 0.3 -1.2 -0.4 0.5 1.0 0.2 0.5 2.0 4.0 1.0 2.0 2.0 1.0 MAX 1.0 0.5 UNIT mA mA mA mA mA mA mA mA A A A A
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL IV-SB PARAMETER V- Current (standby) TEST CONDITIONS V- = -5.5V, VCC = +5.5V @ +85C, SPI interface in standby state V- = -5.5V, VCC = +5.5V @ +125C, SPI interface in standby state V- = -2.25V, VCC = +2.25V @ +85C, SPI interface in standby state V- = -2.25V, VCC = +2.25V @ +125C, SPI interface in standby state ISD VCC Current (shutdown) VCC = +5.5V, V- = -5.5V @ +85C, SPI interface in standby state VCC = +5.5V, V- = -5.5V @ +125C, SPI interface in standby state VCC = +2.25V, V- = -2.25V @ +85C, SPI interface in standby state VCC = +2.25V, V- = -2.25V @ +125C, SPI interface in standby state IV-SD V- Current (shutdown) V- = -5.5V, VCC = +5.5V @ +85C, SPI interface in standby state V- = -5.5V, VCC = +5.5V @ +125C, SPI interface in standby state V- = -2.25V, VCC = +2.25V @ +85C, SPI interface in standby state V- = -2.25V, VCC = +2.25V @ +125C, SPI interface in standby state ILkgDig tWRT (Note 20) tShdnRec (Note 20) Vpor VccRamp tD Leakage current, at pins SCK, SDI, SDO and CS DCP wiper response time DCP recall time from shutdown mode Power-on recall voltage VCC ramp rate Power-up delay VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state Voltage at pin from GND to VCC CS rising edge to wiper new position CS rising edge to wiper stored position and RH connection Minimum Vcc at which memory recall occurs 1.9 0.2 5 -3.0 -5.0 -2.0 -3.0 -1 1.5 1.5 2.1 MIN -3.0 -5.0 -2.0 -3.0 TYP (NOTE 4) -0.7 -1.5 -0.3 -0.4 0.5 1.0 0.2 0.5 -0.7 -1.5 -0.3 -0.4 1 2.0 4.0 1.0 2.0 MAX UNIT A A A A A A A A A A A A A s s V V/ms ms
EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 18) Non-volatile Write Cycle time Temperature T +55C 1,000,000 50 12 20 Cycles Years ms
SERIAL INTERFACE SPECIFICATIONS VIL VIH Hysteresis VOL Rpu (Note 19) SCK, SDI, and CS input buffer LOW voltage SCK, SDI, and CS input buffer HIGH voltage SCK, SDI, and CS input buffer hysteresis SDO output buffer LOW voltage SDO pull-up resistor off-chip IOL = 4mA for Open Drain output, pull-up voltage Vpu = Vcc Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz 0.7 * VCC 0.05 * VCC 0 0.4 2 0.3 * VCC V V V V k
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL Cpin (Note 20) fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tSO tV tHO tRO tFO tCS NOTES: 4. Typical values are for TA = +25C and 3.3V supply voltage. 5. LSB: [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)255 - VCC]/LSB. 8. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 9. INL = [V(RW)i - i * LSB - V(RW)]/LSB for i = 1 to 255. 10. VMATCH= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 1, y = 0 to 1. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 11. TC = --------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 240 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 +165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 12. MI = |RW255 - RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 13. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 14. RDNL = (RWi - RWi-1)/MI -1, for i = 1 to 255. 15. RINL = [RWi - (MI * i) - RW0]/MI, for i = 1 to 255. 16. RMATCH= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 1, y = 0 to 1. 17. [ Max ( Ri ) - Min ( Ri ) ] 10 - for i = 16 to 240, T = -40C to +125C. Max( ) is the maximum value of the resistance and Min ( ) is TC R = --------------------------------------------------------------- x ---------------[ Max ( Ri ) + Min ( Ri ) ] 2 +165C the minimum value of the resistance over the temperature range.
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PARAMETER SCK, SDI, SDO and CS pin capacitance SPI frequency SPI clock cycle time SPI clock high time SPI clock low time Lead time Lag time SDI, SCK and CS input setup time SDI, SCK and CS input hold time SDI, SCK and CS input rise time SDI, SCK and CS input fall time SDO output Disable time SDO output setup time SDO output valid time SDO output hold time SDO output rise time SDO output fall time CS deselect time
TEST CONDITIONS
MIN
TYP (NOTE 4) 10
MAX
UNIT pF
5 200 100 100 250 250 50 50 10 10 0 50 150 0 Rpu = 2k, Cbus = 30pF Rpu = 2k, Cbus = 30pF 2 60 60 20 100
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
18. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 19. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates. 20. This parameter is not 100% tested.
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DCP Macro Model
RTOTAL RH CH CL CW 10pF RL
10pF RW
25pF
Timing Diagrams
Input Timing
tCS CS tLEAD SCK tSU SDI MSB tH tWL tCYC ... tWH ... tLAG
tFI LSB
tRI
SDO
HIGH IMPEDANCE
Output Timing
CS
SCK tSO SDO MSB tV SDI ADDR tHO
... tDIS ... LSB
XDCP Timing (for All Load Instructions)
CS tWRT SCK ...
SDI
MSB
...
LSB
VW
SDO
HIGH IMPEDANCE
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ISL22424 Typical Performance Curves
80 T = +125C 70 WIPER RESISTANCE () STANDBY CURRENT (A) 60 T = +25C 50 40 30 20 10 0 0 50 100 150 200 250 TAP POSITION (DECIMAL) T = -40C 1.5 1.0 0.5 0 -0.5 IV-1.0 -1.5 -2.0 -40 ICC 2.0
0
40 TEMPERATURE (C)
80
120
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W)
FIGURE 2. STANDBY ICC and IV- vs TEMPERATURE
0.50 T = +25C VCC = 2.25V 0.25 DNL (LSB)
0.50 VCC = 5.5V 0.25 T = +25C
INL (LSB) VCC = 5.5V
0
0
-0.25
-0.25
VCC = 2.25V -0.50 200 250 0 50 100 150 200 250
-0.50 0 50 100 150 TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
2.0 10k 1.6
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
0
-1 FS ERROR (LSB)
VCC = 2.25V 50k VCC = 5.5V
ZS ERROR (LSB)
1.2
-2
0.8 VCC = 2.25V 0.4
50k VCC = 5.5V
-3
10k
-4
0 -40
0
40 TEMPERATURE (C)
80
120
-5
-40
0
40 TEMPERATURE (C)
80
120
FIGURE 5. ZS ERROR vs TEMPERATURE
FIGURE 6. FS ERROR vs TEMPERATURE
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ISL22424 Typical Performance Curves
0.5 T = +25C 0.25 RDNL (MI) VCC = 5.5V 1.5 VCC = 2.25V
(Continued)
2.0 T = +25C
1.0 0 RINL (MI) VCC = 2.25V -0.50 0 50 100 150 200 250 TAP POSITION (DECIMAL) -0.5 0
0.5
-0.25 0 VCC = 5.5V 50 100 150 200 250
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
1.60 10k 1.20 RTOTAL CHANGE (%)
200
160 10k TCv (ppm/C)
0.80
120
5.5V
0.40
80
0.00 2.25V -0.40 -40 0 40 TEMPERATURE (C) 80 50k
40
50k
0 120
16
66
116
166
216
266
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
500
INPUT
10k
OUTPUT
400
TCr (ppm/C)
300
200 50k 100 WIPER AT MID POINT (POSITION 80h) RTOTAL = 10k 16 66 116 166 216 TAP POSITION (DECIMAL)
0
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (1MHz)
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ISL22424 Typical Performance Curves
(Continued)
CS SCL
WIPER UNLOADED, WIPER MOVEMENT FROM 0h to FFh
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
Pin Description
Potentiometer Pins
RHI AND RLI The high (RHi) and low (RLi) terminals of the ISL22424 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 255 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWI RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register.
shifted in at the rising edge of the serial clock SCK, while the CS input is low. CHIP SELECT (CS) CS LOW enables the ISL22424, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22424 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state.
Principles of Operation
The ISL22424 is an integrated circuit incorporating two DCPs with their associated registers, non-volatile memory and the SPI serial interface providing direct communication between host, potentiometers and memory. The resistor arrays are comprised of individual resistors connected in a series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the content of the IVRi is recalled and loaded into the corresponding WRi to set the wiper to the initial position.
Bus Interface Pins
SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. SERIAL DATA OUTPUT (SDO) The SDO is a serial data output pin. During a read cycle, the data bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the following rising edge of SCK. The output type is configured through ACR[1] bit for Push Pull or Open Drain operation. Default setting for this pin is Push - Pull. An external pull up resistor is required for Open Drain output operation. Note: the external pull up voltage not allowed beyond VCC. SERIAL DATA INPUT (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI remote host device. The data bits are
DCP Description
Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP
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ISL22424
contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is closest to its "Low" terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0]= FFh), its wiper terminal (RWi) is closest to its "High" terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RLi to the closest to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL22424 is being powered up, the WRi is reset to 80h (128 decimal), which locates RWi roughly at the center between RLi and RHi. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WRi will be reloaded with the value stored in a corresponding non-volatile Initial Value Register (IVRi). The WRi and IVRi can be read or written to directly using the SPI serial interface as described in the following sections. The register at address 0Fh is a read-only reserved register. Information read from this register should be ignored. The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit (ACR[7]) determines whether the access to wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # BIT NAME 7 6 5 4 0 3 0 2 0 1 SDO 0 0
VOL SHDN WIP
Memory Description
The ISL22424 contains two non-volatile 8-bit Initial Value Registers (IVRi), thirteen non-volatile 8-bit General Purpose (GP) registers, two volatile 8-bit Wiper Registers (WRi), and volatile 8-bit Access Control Register (ACR). The memory map of ISL22424 is in Table 1.
TABLE 1. MEMORY MAP
If VOL bit is 0, the non-volatile IVRi and General Purpose registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note: value that is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. When this bit is 0, DCP is in Shutdown mode, i.e. each DCP is forced to end-to-end open circuit and RWi is shorted to RLi as shown on Figure 15. Default value of SHDN bit is 1.
RHi
ADDRESS (hex) 10 F E D C B A 9 8 7 6 5 4 3 2 1 0
NON-VOLATILE N/A Reserved General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose IVR1 IVR0
VOLATILE ACR
RWi
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A WR1 WR0
RLi
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
Setting SHDN bit to 1 is returned wipers to prior to Shutdown Mode position. The WIP bit (ACR[5]) is a read-only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write or read to the WRi or ACR while WIP bit is 1. The SDO bit (ACR[1]) configures type of SDO output pin. The default value of SDO bit is 0 for Push - Pull output. SDO pin can be configured as Open Drain output for some application. In this case, an external pull up resistor is required. See "Applications Information" on page 14.
SPI Serial Interface
The ISL22424 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22424. SCK and CS lines are
The non-volatile registers (IVRi) at address 0 and 1, contain initial wiper position and volatile registers (WRi) contain current wiper position.
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ISL22424
controlled by the host or master. The ISL22424 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first.
Write Operation
A Write operation to the ISL22424 is a two or more bytes operation. First, It requires, the CS transition from HIGH to LOW. Then host must send a valid Instruction Byte followed by one or more Data Bytes to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. Instruction is executed on rising edge of CS. For a write-to address 0 or 1, the MSB of the byte at address 10h (ACR[7]) determines if the Data Byte is to be written to volatile or both volatile and non-volatile registers. Refer to "Memory Description" and Figure 16. Note: the internal non-volatile write cycle starts with the rising edge of CS and requires up to 20ms. During non-volatile write cycle the read operation to ACR register is allowed to check WIP bit.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one or more Data Bytes. A valid Instruction Byte contains instruction as the three MSBs, with the following five register address bits (see Table 3). The next byte sent to the ISL22424 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT BIT # 7 I2 6 I1 5 I0 4 R4 3 R3 2 R2 1 R1 0 R0
Read Operation
A Read operation to the ISL22424 is a four byte operation. It requires first, the CS transition from HIGH to LOW. Then the host must send a valid Instruction Byte followed by "dummy" Data Byte, a NOP Instruction Byte and another "dummy" Data Byte to SDI pin. The SPI host receives the Instruction Byte (instruction code + register address) and requested Data Byte from SDO pin on rising edge of SCK during third and fourth bytes respectively. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 17). Reading from the IVRi will not change the WRi, if its contents are different.
Table 4 contains a valid instruction set for ISL22424. There are only sixteen register addresses possible for this DCP. If the [R4:R0] bits are 00000 or 00001, then the read or write is to either the IVRi or the WRi registers (depends of VOL bit at ACR). If the [R4:R0] are 10000, then the operation is on the ACR.
TABLE 4. INSTRUCTION SET
INSTRUCTION SET I2
0 0 0 1 1
I1
0 0 1 0 1
I0
0 1 1 0 0
R4
X X X R4 R4
R3
X X X R3 R3
R2
X X X R2 R2
R1
X X X R1 R1
R0
X X X R0 R0 NOP ACR READ ACR WRITE
OPERATION
WR, IVR, GP or ACR READ WR, IVR, GP or ACR WRITE
where X means "do not care".
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
WR INSTRUCTION
ADDR
DATA BYTE
SDO
FIGURE 16. TWO BYTE WRITE SEQUENCE
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ISL22424
CS 1 8 16 24 32
SCK
SDI
RD
ADDR
NOP
SDO
RD
ADDR
READ DATA
FIGURE 17. FOUR BYTE READ SEQUENCE
Applications Information
Communicating with ISL22424
Communication with ISL22424 proceeds using SPI interface through the ACR (address 10000b), IVRi (address 00000b, 00001b), WRi (addresses 00000b, 00001b) and General Purpose registers (addresses from 00010b to 01110b). The wiper position of each potentiometer is controlled by the corresponding WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address 10000b to 1 (ACR[7] = 1). The non-volatile IVRi stores the power up position of the wiper. IVRi is accessible when MSB bit at address 10000b is set to 0 (ACR[7] = 0). Writing a new value to the IVRi register will set a new power up position for the wiper. Also, writing to this registers will load the same value into the corresponding WRi as the IVRi. Reading from the IVRi will not change the WRi, if its contents are different.
to DCP(N-1) as follow: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously.
Daisy Chain Read Operation
The read operation consists of two parts: first, send read instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two bytes operation) as shown on Figure 20 and Figure 21. The first part starts by HIGH to LOW transition on CS line, followed by N two bytes read instruction on SDI line with reversed chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by LOW to HIGH transition on CS line. The read instructions are executed during second part of read sequence. It also starts by HIGH to LOW transition on CS line, followed by N two bytes NOP instructions on SDI line and LOW to HIGH transition of CS. The data is read on every even byte during second part of read sequence while every odd byte contains instruction code + address from which the data is being read.
Daisy Chain Configuration
When application needs more then one ISL22424, it can communicate with all of them without additional CS lines by daisy chaining the DCPs as shown on Figure 18. In Daisy Chain configuration the SDO pin of previous chip is connected to SDI pin of the following chip, and each CS and SCK pins are connected to the corresponding microcontroller pins in parallel, like regular SPI interface implementation. The Daisy Chain configuration can also be used for simultaneous setting of multiple DCPs. Note, the number of daisy chained DCPs is limited only by the driving capabilities of SCK and CS pins of microcontroller; for larger number of SPI devices buffering of SCK and CS lines is required.
Wiper Transition
When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance "make" to a much higher impedance "break within an extremely short period of time (<50ns). Two such code transitions are EFh to F0h, and 0Fh to 10h. Note, that all switching transients will settle well within the settling time as stated on the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery.
Daisy Chain Write Operation
The write operation starts by HIGH to LOW transition on CS line, followed by N two bytes write instructions on SDI line with reversed chain access sequence: the instruction byte + data byte for the last DCP in chain is going first, as shown on Figure 19. The serial data is going through DCPs from DCP0 14
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ISL22424
Application Example
Figure 22 shows an example of using ISL22424 for gain setting and offset correction in high side current measurement application. DCP0 applies a programmable offset voltage of 25mV to the FB+ pin of the Instrumentation Amplifier EL8173 to adjust output offset to zero voltages. DCP1 programs the gain of the EL8173 from 90 to 110 with 5V output for 10A current through current sense resistor. More application examples can be found at http://www.intersil.com/data/an/AN1145.pdf
N DCP IN A CHAIN CS SCK MOSI MISO C CS SCK SDI SDO DCP0 CS SCK SDI SDO DCP1 CS SCK SDI SDO DCP2 DCP(N-1) CS SCK SDI SDO
FIGURE 18. DAISY CHAIN CONFIGURATION
CS
SCK 16 CLKLS SDI SDO 0 WR D C P2 16 CLKS WR WR D C P1 D C P2 WR WR 16 CLKS D C P0 D C P1
SDO 1
WR
D C P2
SDO 2
FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
INSTRUCTION
ADDR
DATA IN
SDO
DATA OUT
FIGURE 20. TWO BYTE OPERATION
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ISL22424
CS
SCK 16 CLKS SDI RD DCP2 16 CLKS RD DCP1 16 CLKS RD DCP0 16 CLKS NOP 16 CLKS NOP 16 CLKS NOP
SDO
DCP2 OUT
DCP1 OUT
DCP0 OUT
FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP
1.2V DC/DC CONVERTER OUTPUT
0.005
PROCESSOR LOAD 10A, MAX
10k
0.1F
10k
+5V 8 VS+ 3 IN+ EN EL8173IS
1
2 INVOUT 7 FB+ +5V R1 50k, 1% RH0 RW0 50k RL0 DCP0 (1/2 ISL22424U) PROGRAMMABLE OFFSET 25mV R3 50k, 1% -5V +5V 14 10 9 12 13 7 11 -5V 8 R2 1k, 1% RW1 50k RL1 5 FB- V S 4 RH1 R5 309, 1% R4 150k, 1% 6 VOUT = 0V to + 5V to ADC
DCP1 (1/2 ISL22424U) PROGRAMMABLE GAIN 90 TO 110 R6 1.37k, 1%
ISL22424UFV14Z Vcc SCL SDO SDI CS NC GND VRH0 RL0 RW0 RH1 RL1 RW1 1 2 3 4 5 6
DCP0
SPI bus
DCP1
FIGURE 22. CURRENT SENSING WITH GAIN AND OFFSET CONTROL
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ISL22424 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGD-10) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 2.30 2.30 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.25 4.00 BSC 3.75 BSC 2.40 4.00 BSC 3.75 BSC 2.40 0.50 BSC 0.40 16 4 4 0.60 12 0.50 0.15 2.55 2.55 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 2 3/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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ISL22424 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN6425.0 May 31, 2007

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