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TDA8263HN
Fully integrated satellite tuner
Rev. 01 -- 14 December 2004 Product data sheet
1. General description
The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV broadcasting, satisfying both DVB-S and DBS TV standards. The wide range oscillator (from 950 MHz to 2175 MHz) covers the American, European and Asian satellite bands, as well as the SMA-TV US standard. The Zero-IF (ZIF) concept discards traditional IF filtering and intermediate conversion techniques. Gain-controlled amplifiers in the RF guarantee optimum signal level. The variable gain is controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and applied to pin AGC. The integrated LNA allows the IC to be directly connected to the LNB output. The LNA can be by-passed by an I2C-bus selectable attenuation, providing a 20 dB extra attenuation in order to handle higher input signal levels of up to 0 dBm per channel. Connected at the RF input, an RMS level detector provides through I2C-bus read mode the full band input signal level. The LO quadrature outputs are derived from a high performance integrated LC oscillator. f LO f XTAL Its frequency is: -------- = -------------- . Thanks to the low phase noise performance of the N R integrated LC oscillator which controls the LO frequency, the synthesizer offers a good performance for phase noise in the satellite band. The step size of the LO output frequency is equal to the comparison frequency. Control data is entered via the I2C-bus. The bus can be either 5.0 V or 3.3 V, allowing compatibility with most of existing microcontrollers. An 8-byte frame is required to address the device and to program the main divider ratio, the reference divider ratio, the charge-pump current and the operating mode. A flag is set when the loop is in-lock, readable during read operations, as well as the Power-on reset flag and RF input level. The device has four selectable I2C-bus addresses. Applying a specific voltage to pin AS selects an address. This feature gives the possibility to use up to four TDA8263HN ICs in the same system.
Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
2. Features
s s s s Direct conversion QPSK and 8PSK demodulation (ZIF) 3.3 V DC supply voltage (no 30 V required) 950 MHz to 2175 MHz frequency range High range input level; x -70 dBm to -15 dBm at 75 (normal mode) x Up to 0 dBm (20 dB attenuation configuration). Low noise RF input (integrated LNA) 0 dB to 55 dB continuous variable gain on RF input RF input level detector Switchable 0 dB to 9 dB additional gain on baseband output amplifier High AGC linearity (< 0.7 dB/step when used with an 8-bit DAC), AGC controlled voltage between 0.3 V and 3 V Programmable 5 MHz to 36 MHz 5th-order baseband filters for I and Q paths Fully integrated PLL frequency synthesizer Low phase noise fully integrated oscillator Operation from a 16 MHz crystal or external clock 5 frequency steps from 125 kHz to 2 MHz Crystal frequency output to drive the demodulator IC Compatible with 5 V and 3.3 V I2C-bus Fully compatible and easy to interface with the PS digital satellite demodulators family 32-pin low thermal resistance package.
s s s s s s s s s s s s s s
3. Applications
s s s s Direct Broadcasting Satellite (DBS) QPSK demodulation Digital Video Broadcasting (DVB) QPSK demodulation BS digital 8PSK demodulation DVB-S2 8PSK demodulation.
4. Quick reference data
Table 1: Symbol VCC ICC fosc Vo(I/Q)(rms) Quick reference data Parameter supply voltage supply current oscillator frequency absolute quadrature error recommended I and Q output voltage RMS value (QPSK signals) LPF cut-off frequency 5-bit controlled measured at 10 MHz
[1]
Conditions
Min 3.15 950 0 -
Typ 3.3 167 200
Max 3.45 2175 5 -
Unit V mA MHz degree mV
fLPF
-
5 to 36 -
MHz
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Product data sheet
Rev. 01 -- 14 December 2004
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
Quick reference data ...continued Parameter Conditions
[2]
Table 1: Symbol Nosc SNFSB AGC Tamb
[1] [2]
Min 55 -20
Typ -100 60 -
Max -94 -78 +85
Unit dBc/Hz dBc/Hz dB C
oscillator phase noise in 100 kHz offset; the satellite band fcomp = 1 MHz synthesizer noise floor in 1 kHz and10 kHz the satellite band offset; fcomp = 1 MHz amplifier gain control range ambient temperature
[2]
The product is qualified with an output voltage of 550 mV (p-p) differential, however larger values can be used at baseband outputs that might have impact on the product performance. Phase noise in optimal conditions, see related application note.
5. Typical performances
* Noise figure at maximum gain: 8 dB * High linearity:
- IIP2 = +2 dBm at -20 dBm input and 2.15 GHz - IIP3 = +6 dBm at -20 dBm input and 2.15 GHz.
* Low synthesizer noise floor: -78 dBc/Hz at 1 kHz and 10 kHz offset with
fcomp = 1 MHz
* * * *
AGC linearity: < 0.7 dB/step with a 8-bit DAC Maximum I/Q amplitude mismatch: 1 dB Maximum I/Q quadrature mismatch: 5 Symbol rates: from 1 MBd to 45 MBd.
6. Ordering information
Table 2: Ordering information Package Name TDA8263HN HVQFN32 Description plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm Version SOT617-1 Type number
9397 750 13193
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Product data sheet
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TDA8263HN
Fully integrated satellite tuner
7. Block diagram
AGC 9 4 2 LNA RFIN 3 11 AGC control
1 5 3
PORT0 8
PORT1 32
10 15
VCC(BB) GND(BB)
VCC(LNA) GND(LNA)
TDA8263HN
5 MHz to 36 MHz filter
0 dB to +9 dB variation gain 14 13 IP IN
ATT VCC(RF) GND(RF) 7 5
12
QP QN
3
LEVEL DETECTOR 0 90
GND(DIE)
1
LATCH AND CONTROL BIT
I 2 C-BUS INTERFACE
29 30 17
SDA SCL AS
15-BIT DIVIDER XTOUT
15 3
25
XTOUT
x I/Q outputs wide band integrated oscillator n.c. 6 19 VCC(VCO) GND(VCO) 21
N2 N1
LOW-NOISE INTEGRATED LC OSCILLATOR
26 REFERENCE DIVIDER CRYSTAL OSCILLATOR 27 16
XT XTN MS
3, 2
LOCK DETECTOR 23 VCC(PLL) GND(PLL) 24 18 CAPVCO 20 22
1
POWER-ON RESET 28 31
1
VT CP
VCC(DIG) GND(DIG)
001aaa974
Fig 1. Block diagram
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
8. Pinning information
8.1 Pinning
31 GND(DIG) 28 VCC(DIG)
GND(DIE) GND(LNA) RFIN VCC(LNA) GND(RF) n.c. VCC(RF) PORT0
1 2 3 4 5 6 7 8 VCC(BB) 10 QP 11 QN 12 IN 13 IP 14 GND(BB) 15 MS 16 9
26 XT
terminal 1 index area
25 XTOUT 24 GND(PLL) 23 VCC(PLL) 22 CP 21 GND(VCO) 20 VT 19 VCC(VCO) 18 CAPVCO 17 AS
32 PORT1
29 SDA
TDA8263HN
AGC
27 XTN
30 SCL
001aaa976
Transparent top view
Fig 2. Pin configuration
8.2 Pin description
Table 3: Symbol GND(DIE) GND(LNA) RFIN VCC(LNA) GND(RF) n.c. VCC(RF) PORT0 AGC VCC(BB) QP QN IN IP GND(BB) MS AS CAPVCO
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Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description isolation ground LNA ground RF input LNA supply voltage RF ground not connected RF supply voltage pull-down port 0 automatic gain control input baseband supply voltage Q positive output Q negative output I negative output I positive output baseband ground master/slave crystal oscillator mode input address select input internal LC VCO regulation capacitor
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Product data sheet
Rev. 01 -- 14 December 2004
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
Pin description ...continued Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description VCO supply voltage VCO tuning voltage input VCO ground charge pump output PLL supply voltage PLL ground 16 MHz frequency for external ICs output 16 MHz crystal oscillator input 16 MHz crystal oscillator input digital supply voltage I2C-bus data input/output I2C-bus clock input digital ground pull-down port 1
Table 3: Symbol VCC(VCO) VT GND(VCO) CP VCC(PLL) GND(PLL) XTOUT XT XTN VCC(DIG) SDA SCL GND(DIG) PORT1
9. Tuner configuration
16 MHz RF input I/Q base band AGC control 16 MHz I 2 C-bus
MPEG2 stream
TDA8263
TDA10086
I 2 C-bus
001aaa975
Fig 3. Tuner configuration
10. Functional description
The TDA8263HN contains the core of the RF analog part of a digital satellite receiver. The signal coming from the LNB is coupled to the RF inputs. The internal circuitry performs the Zero-IF quadrature frequency conversion and two in-phase (IP/IN) and two quadrature (QP/QN) output signals can directly be used to feed a Satellite Demodulator and Decoder circuit (SDD). Low-pass filter cut-off frequency can be adjusted from 5 MHz to 36 MHz in 32 steps. This allows a large flexibility in the SDD input. 10 gain values are present at output amplifier to compensate cut-off frequency adjustment and single output application. The IC gain controlled amplifier before the mixer is controlled by the SDD through pin AGC. An input level detector gives the wide band RF level. This information is available through I2C-bus in read mode.
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Product data sheet
Rev. 01 -- 14 December 2004
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
The internal loop controls a fully integrated VCO, to cover the range from 950 MHz to 2175 MHz. This VCO provides both in phase and quadrature signals to drive the two mixers. The output of the 15-bit programmable divider passes through the phase comparator where it is compared in both phase and frequency to the comparison frequency (fcomp). This fcomp is derived from the signal present at the XT/XTN pins (fXTAL), divided down in the reference divider. The buffered signal on pin XTOUT is able to drive the crystal frequency input of the SDD, which saves a crystal in the application. The output of the phase comparator drives the charge pump and loop amplifier section. Pin CP is the output of the charge pump, and pin VT drives the tuning voltage to the varicap diode of the voltage controlled oscillator. The loop filter has to be connected between pins CP and VT. For test and alignment purposes, it is possible to release the tuning voltage output and to apply an external voltage on the VT pin, as well as to select the charge pump sink, source or off.
10.1 Gain distribution
RFATT AGC BBGAIN [3:0]
LNA/ATT
AGC
12 dB -8 dB
24 dB -37 dB
10.2 dB
9 dB
10.2 dB
10.2 dB
001aaa977
Fig 4. Gain distribution; typical values
11. Programming
The programming of the TDA8263HN is done through the I2C-bus. The READ/WRITE selection is done through the R/W bit (address LSB). The TDA8263HN fulfils the fast mode I2C-bus specification, according to the Philips I2C-bus specification, see document 9398 393 40011.
11.1 I2C-bus inputs
The I2C-bus lines SCL and SDA can be connected to an I2C-bus system tied to either 3.3 V or 5.0 V, which allows direct connection to most of existing microcontrollers. Data transfer format should be MSB first, and 8-bit word + acknowledge bit.
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Product data sheet
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TDA8263HN
Fully integrated satellite tuner
Pins used for the I2C-bus:
* Pin SCL is the clock input * Pin SDA is the data input/output * Pin AS is for address selection. 11.2 Address selection
Table 4: Address selection (pin AS) Write address C0 C2 C4 C6 Read address C1 C3 C5 C7 Voltage on pin AS 0 V to 0.1 x VCC 0.2 x VCC to 0.3 x VCC or open pin 0.4 x VCC to 0.6 x VCC 0.9 x VCC to VCC
11.3 Master-slave selection
Table 5: Master-slave selection (pin MS) Crystal oscillator mode master slave Voltage on pin MS 0 V to 0.1 x VCC 0.9 x VCC to VCC
11.4 Data transfer in write mode
The data transfer in write mode use the following pattern:
Table 6: I2C-bus write mode data transfer pattern ack subaddress ack data 1 ack data 2 ack data n ack STOP
START address
Subaddress is automatically incremented starting from the initial value.
11.5 I2C-bus table in write mode
Table 7: I2C-bus write mode map LSB 6 R1 N13 N5 FC3 BBGAIN2 CPTST AMPVCO1 BBIAS2 5 R0 N12 N4 FC2 BBGAIN1 FUP AMPVCO0 BBIAS1 4 D4 N11 N3 FC1 BBGAIN0 FDN SELVTH1 BBIAS0 3 D3 N10 N2 FC0 CP2TST SELVTH0 2 D2 N9 N1 FPFD2 SELVTL1 1 D1 N8 N0 CPHIGH PORT1 0 TEST1 D0 N7 CALMANUAL RFATT PORT0 PDXTOUT PDRSSI Subaddress MSB (hex) 7 0X 1X 2X 3X 4X 5X 6X 7X 8X 9X R2 N14 N6 FC4 BBGAIN3 CPCURSEL AMPVCO2 CALTIME BBIAS3
SELVTL0 -
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Product data sheet
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TDA8263HN
Fully integrated satellite tuner
11.6 I2C-bus table in write mode (default at POR)
Table 8: I2C-bus write mode map (default at POR) [1] LSB 6 0 0 0 0 0 0 0 0 5 1 0 0 0 0 X 0 0 4 0 0 0 0 0 0 X 0 0 3 1 0 0 0 0 0 0 2 0 0 0 X 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 Subaddress MSB (hex) 7 0X 1X 2X 3X 4X 5X 6X 7X 8X 9X
[1]
0 0 0 0 0 0 1 0 0
X means don't care.
11.7 Bit description I2C-bus write mode
Table 9: Bit PDXTOUT PDRSSI TEST1 Power-down section; bits PDXTOUT, PDRSSI and TEST1 Description power-down of the XTOUT output power-down of the input level detector used for test purposes only State 0 = function on; 1 = function off 0 = function on; 1 = function off must be logic 1
Table 10: Reference divider range; bits R[2:0] These bits select the ratio between the comparison frequency and the crystal frequency. R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 Decimal 0 1 2 3 4 5 6 7 Comparison frequency 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 125 kHz 125 kHz 125 kHz
Table 11: VCO preprogramming range; bits D[4:0] These bits are also called Dword: It determines the ratio between LO frequency and VCO frequency. The bits are used for the calibration protocol of the internal VCO. D4 0 0 0 0
9397 750 13193
D3 0 0 0 0
D2 0 0 0 0
D1 0 0 1 1
D0 0 1 0 1
Decimal 0 1 2 3
Ratio fLO to fVCO 0.27 0.29 0.31 0.33
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Product data sheet
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
Table 11: VCO preprogramming range; bits D[4:0] ...continued These bits are also called Dword: It determines the ratio between LO frequency and VCO frequency. The bits are used for the calibration protocol of the internal VCO. D4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Decimal 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Ratio fLO to fVCO 0.36 0.36 0.38 0.40 0.42 0.43 0.44 0.45 0.46 0.47 0.50 0.54 0.55 0.56 0.58 0.60 0.63 0.64 0.67 0.70 0.75 0.78 0.88 0.88 0.88 0.88 0.88 0.88
Table 12: Main divider range; bits N[14:0] These bits control the ratio between the LO frequency and the comparison frequency. N[14:0] Binary value Ratio The ratio N is equal to N14 x 214 + N13 x 213 + ...N1 x 21 + N0
Table 13: Selects manual or automatic LC oscillator calibration; bit CALMANUAL This bit controls the LC VCO frequency programming mode. CALMANUAL 0 1 Action automatic process control; the LC VCO searches the better ratio of the Dword to have the optimum tuning frequency manual process control; the LC VCO is tuned by selecting the programmed Dword
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9397 750 13193
Product data sheet
Rev. 01 -- 14 December 2004
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
Table 14: RX baseband cut-off frequency control; bits FC[4:0] The register selects the cut-off frequency of the RX baseband filter. The cut-off frequency can be set from 5 MHz to 36 MHz in 32 steps of 1 MHz FC4 FC3 FC2 FC1 FC0 Decimal Baseband cut-off frequency (MHz) [1] 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[1]
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Typical values at nominal process and room temperature.
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TDA8263HN
Fully integrated satellite tuner
Table 15: RX baseband gain control; bits BBGAIN[3:0] These bits control the additional gain of the baseband between 0 dB and 9dB BBGAIN3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
[1]
BBGAIN2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
BBGAIN1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
BBGAIN0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Additional gain in dB [1] 0 0 0 0 0 1.6 3 4.6 6.3 7.3 8.2 8.5 8.8 8.8 9 9
Typical values at nominal process and room temperature.
Table 16: 20 dB RF attenuation control; bit RFATT This bit controls the RF attenuation inside the LNA amplifier. RFATT 0 1 Action normal gain of RF path 20 dB attenuation. When active, the LNA works in attenuation (-8 dB gain).
Table 17:
Select main loop charge-pump current; bit CPCURSEL Action low charge-pump current high charge-pump current 0 1
CPCURSEL
Table 18: Main loop charge pump test; bits CPTST, FUP and FDN These bits force the inputs of the main loop charge pump. Thus the current and leakage measurement could be done. This test could be used also to force the LC VCO at its maximum or minimum tuning voltage. CPTST 0 1 1 1 1 FUP X 0 0 1 1 FDN X 0 1 0 1 Actions test disable sink and source off; leakage measurement sink off and source on; source measurement sink on and source off; sink measurement sink on and source on
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TDA8263HN
Fully integrated satellite tuner
Table 19: Second loop charge pump test; bits CP2TST and FPFD2 These bits force the inputs of the second loop charge pump. This test could be used to force the LO VCO at its maximum or minimum tuning voltage. CP2TST 0 1 1 Table 20: FPFD2 X 0 1 Actions test disable sink on and source off; LO VCO maximum frequency measurement sink off and source on; LO VCO minimum frequency measurement
Select main loop charge-pump current; bit CPHIGH Action first charge pump active (low currents) second charge pump active (high currents) 0 1
CPHIGH
Table 21: Amplitude of the internal VCO; bits AMPVCO[2:0] These bits control the amplitude of the internal LC VCO. AMPVCO[2:0] Binary value Value The allowed value is AMPVCO[2:0] = 100 (decimal 4). The product is specified only with this value, other settings may lead to different performance.
Table 22: Control port output; bits PORT[1:0] Bit PORT1 controls the use of PORT1 and bit PORT0 controls the use of PORT0. Outputs PORTn are realized with open-drain NMOS transistors. PORTn 0 1 Action PORTn at high-impedance PORTn in sink mode; minimum 9 mA drive capability
Table 23: Calibration wait time control; bit CALTIME This bit controls the duration of the wait time of the calibration. This time is used to wait PLL locking after programming a Dword. The reference clock of the time is the comparison frequency of the PLL CALTIME 0 1 fc divider ratio 28673 32769 Wait time for fcomp = 1 MHz (ms) 28.673 32.769
Table 24: Maximum voltage tuning threshold for calibration control; bits SELVTH[1:0] These bits control the voltage threshold for the ACUP comparator. The ACUP and ACDN comparators sense the LC VCO tuning voltage at pin VT. SELVTH1 0 0 1 1
[1] [2]
SELVTH0 0 1 0 1
Decimal 0 1 2 3
Threshold VTH (V) [1] [2] 1.8 1.9 2.0 2.1
Typical values at nominal process and room temperature. The recommended value is SELVTH[1:0] = 11 (decimal 3).
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TDA8263HN
Fully integrated satellite tuner
Table 25: Minimum voltage tuning threshold for calibration control; bits SELVTL[1:0] These bits control the voltage threshold for the ACDN comparator. The ACUP and ACDN comparators sense the LC VCO tuning voltage at pin VT. SELVTL1 0 0 1 1
[1] [2]
SELVTL0 0 1 0 1
Decimal 0 1 2 3
Threshold VTL (V) [1] [2] 0.6 0.5 0.4 0.3
Typical values at nominal process and room temperature. The recommended value is SELVTL[1:0] = 01 (decimal 1).
Table 26: Baseband bias current control; bits BBIAS[3:0] This register modifies the baseband bias current through different parts: Output buffer or other amplifier. BBIAS[3:0] Binary value Value The allowed value is BBIAS[3:0] = 1101 (decimal 13). The product is specified only with this value, other settings may lead to different performance.
11.8 Data transfer in read mode
The data transfer in read mode use the following pattern.
Table 27: I2C-bus read mode data transfer pattern ack data 1 ack data 2 ack STOP
START address
11.9 I2C-bus table in read mode
Table 28: Byte 0 1
[1]
I2C-bus read mode map [1] MSB 7 POR 1 6 LOCK INLEVEL1 5 ACUP INLEVEL0 4 ACDN DW4 3 DW3 2 DW2 1 X DW1 ERRORCAL X LSB 0 X DW0
X can be 1 or 0 and needs to be masked in the microcontrollers' software; MSB is transmitted first.
11.10 Bit description I2C-bus read mode
Table 29: POR 0 1 Power-on reset; bit POR Action Normal operation This bit is set to logic 1 at the VCC(DIG) power supply ramp-up. It is reset to logic 0 after the first read of the IC. When VCC(DIG) falls below 2 V typical, this bit is set to logic 1. This is to prevent loss in internal I2C-bus registers programming.
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Fully integrated satellite tuner
Synthesizer lock indicator; bit LOCK Action synthesizer is not locked synthesizer is locked Auto calibration up threshold control; bit ACUP Action LC VCO tuning voltage is lower than VTH (see Table 24) LC VCO tuning voltage is higher than VTH (see Table 24) Auto calibration down threshold control; bit ACDN Action LC VCO tuning voltage is higher than VTL (see Table 25) LC VCO tuning voltage is lower than VTL (see Table 25) Calibration defect detection; bit ERRORCAL no defect detected calibration unit control tries to go lower than the minimum or higher than the maximum Dword ratio
Table 30: LOCK 0 1 Table 31: ACUP 0 1 Table 32: ACDN 0 1 Table 33: 0 1
ERRORCAL Action
Table 34: RF input level indicator; bits INLEVEL[1:0] This register gives the RF input level in dBm INLEVEL1 0 0 1 1
[1]
INLEVEL0 Decimal 0 1 0 1 0 1 2 3
RF power (dBm) [1] < -30 -30 to -20 -20 to -15 > -15
Typical values at nominal process and room temperature. Values are valid only when LNA path is selected (bit RFATT = 0).
Table 35: Internal Dword register; bits DW[4:0] This register gives the internal Dword value. This value could be the programmed D[4:0] value in manual mode or the calculated value after LC VCO calibration in automatic mode. DW[4:0] Binary value Description The fLO to fVCO ratio is the same as shown in Table 11
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Fully integrated satellite tuner
12. Internal circuitry
Table 36: Symbol RFIN Internal circuitry Pin 3 Equivalent circuit
RFIN
001aaa979
GND(RF)
PORT0
8
PORT0
test
GND(RF)
001aaa980
AGC
9
50 k 21 k
AGC
35 k
GND(BB)
001aaa981
QP
11
QP GND(BB)
001aaa982
QN
12
QN
GND(BB)
001aaa983
IN
13
IN
GND(BB)
001aaa984
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TDA8263HN
Fully integrated satellite tuner
Internal circuitry ...continued Pin 14 Equivalent circuit
Table 36: Symbol IP
IP
GND(BB)
001aaa985
MS
16
500
MS
GND(BB)
001aaa986
AS
17
500
AS
GND(PLL) test
001aaa987
CAPVCO
18
5 k
CAPVCO
GND(PLL)
001aaa988
VT
20
100
VT
GND(PLL)
001aaa989
CP
22
CP GND(PLL)
001aaa990
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Product data sheet
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
Internal circuitry ...continued Pin 25 Equivalent circuit
Table 36: Symbol XTOUT
XTOUT
GND(PLL)
001aaa991
XT
26
XT GND(PLL)
001aaa992
XTN
27
XTN GND(PLL)
001aaa993
SDA
29
500
SDA
GND(DIG)
001aaa994
SCL
30
500
SCL
GND(DIG)
001aaa995
PORT1
32
500
CMOS logic test
PORT1
GND(DIG) test
001aaa996
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Product data sheet
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TDA8263HN
Fully integrated satellite tuner
13. Limiting values
Table 37: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] Symbol VCC VI Parameter supply voltage input voltage pins SDA, SCL, PORT1 and PORT0 pin RFIN all other pins Tamb Tstg Tj tsc Vesd operating ambient temperature storage temperature junction temperature short circuit time electrostatic discharge voltage human body model pin PORT0 (pin 8) all other pins machine model
[1] [2] [3] [4]
[4] [3] [2]
Conditions
Min -0.5 -0.3 -0.3
Max +3.6 +5.5 VCC - 0.3 VCC + 0.3 +3.6 +85 +125 125 10 1000 2000 200
Unit V V V V V C C C s
VCC < 3.3 V VCC 3.3 V
-0.3 -0.3 -20 -40 -
V V V
Maximum ratings cannot be exceeded, not even momentarily without causing irreversible damages to the IC. Maximum ratings cannot be accumulated. Each pin to VCC or GND; except RFIN pin which should never exceed VCC - 0.3 V. Test in accordance with JEDEC specification EIA/JESD22-114B. Test in accordance with JEDEC specification EIA/JESD22-A115-A.
14. Thermal characteristics
Table 38: Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance junction to ambient Conditions JEDEC 4 layer test board with 9 thermal vias (exposed die pad soldered on board) Typ 43 Unit K/W
15. Characteristics
Table 39: Characteristics Tamb = 25 C; VCC = 3.3 V; output level on differential I/Q output is 550 mV (p-p); unless otherwise specified. Symbol Supply VCC ICC VPOR supply voltage supply current voltage limit when POR is active 3.15 1.5 3.3 167 3.45 2.5 V mA V Parameter Conditions Min Typ Max Unit
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Table 39: Characteristics ...continued Tamb = 25 C; VCC = 3.3 V; output level on differential I/Q output is 550 mV (p-p); unless otherwise specified. Symbol LOL(RFIN) Zi ZL(I/Q)(max) VO(I/Q) Parameter LO leakage through RF inputs input impedance maximum load on each IP, IN, QP and QN output DC voltage on I/Q output single mode Conditions between 950 MHz and 2175 MHz Min [1]
Typ -85 75 10 1 1.65 0 9 200 550
Max -
Unit dBm pF k V dB dB mV mV
RF and Baseband
Gv(BB)(min) minimum baseband additional gain BBGAIN[3:0] = 0h Gv(BB)(max) maximum baseband additional gain BBGAIN[3:0] = Fh Vo(I/Q)(rms) Vo(I/Q)(p-p) recommended I and Q output voltage RMS value (QPSK signals) differential voltage typical AC output voltage on differential I/Q output; peak-to-peak value second-order interception point at RF input third-order interception point at RF input fi = 2150 MHz; PRFIN = -20 dBm PRFIN = -20 dBm fi = 2150 MHz fi = 950 MHz F Gv(I-Q)(M) Gv(I/Q)(R) td(g)(I-Q) td(g)(I/Q)(R) 60(I/Q) fLPF(min) fLPF(max) Gv(LNA)(min) noise figure voltage gain mismatch between I and Q voltage gain ripple for I or Q absolute quadrature error group delay mismatch between I and Q group delay ripple for I or Q rejection at 60 MHz for I and Q minimum filter cut-off frequency maximum filter cut-off frequency minimum voltage gain LNA configuration maximum gain; VAGC = 3 V measured at 10 MHz; fLPF = 36 MHz fLPF = 36 MHz; 22.5 MHz band measured at 10 MHz; fLPF = 36 MHz fLPF = 36 MHz; 22.5 MHz band fLPF = 36 MHz; 22.5 MHz band fLPF = 36 MHz FC[4:0] = 00h FC[4:0] = 1Fh VAGC = 0.3 V VAGC = 3 V VAGC = 0.3 V VAGC = 3 V
[3] [2]
-
IIP2 IIP3
-
2
-
dBm dBm
0 55
6 0 7.7 0 5 30 5 36 6 67 -14 47 60
8.5 1 2 5 -
dBm dBm dB dB dB degree ns ns dB MHz MHz dB dB dB dB dB
Voltage gain from RF input to IP, IN, QP and QN outputs; differential output; fLPF = 36 MHz; BBGAIN[3:0] = 0h.
Gv(LNA)(max) maximum voltage gain LNA configuration Gv(a)(min) Gv(a)(max) AGC VCO fosc
9397 750 13193
minimum voltage gain attenuated configuration maximum voltage gain attenuated configuration amplifier gain control range
VCO and synthesizer oscillator frequency 950 2175 MHz
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Product data sheet
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Fully integrated satellite tuner
Table 39: Characteristics ...continued Tamb = 25 C; VCC = 3.3 V; output level on differential I/Q output is 550 mV (p-p); unless otherwise specified. Symbol Nosc SNFSB MDR Zosc fXTAL ZXTAL Vo(p-p) MS input Ih Il Il Il(min) Il(max) Ih(min) Ih(max) HIGH level input current LOW level input current charge pump leakage current charge pump low, minimum current CPHIGH = 0 and CPCURSEL = 0 charge pump low, maximum current charge pump high, minimum current charge pump high, maximum current CPHIGH = 0 and CPCURSEL = 1 CPHIGH = 1 and CPCURSEL = 0 CPHIGH = 1 and CPCURSEL = 1 VMS = VCC VMS = 0 V -50 -50 -10 0.67 0.97 1.27 1.87 0 0.9 1.3 1.7 2.5 +50 +50 +10 1.13 1.63 2.13 3.13 A A nA mA mA mA mA Parameter oscillator phase noise in the satellite band synthesizer noise floor in the satellite band main divider ratio crystal oscillator negative impedance crystal frequency recommended crystal series resistance output voltage (peak-to-peak value) crystal output absolute value Conditions 100 kHz offset, out of the PLL bandwidth 1 kHz and 10 kHz offset; fcomp = 1 MHz
[4]
Min 128 500 16 550
Typ -100 16 750
Max -94 -78 32767 16 150 -
Unit dBc/Hz dBc/Hz
[4]
Crystal oscillator and XTOUT MHz mV
Charge pump and tuning voltage
I2C-bus and PORTn SDA and SCL input VIL VIH IHI ILI fSCL SDA output VO AS input IASh IASl PORTn VO(max)
[1] [2]
LOW-level input voltage HIGH-level input voltage HIGH-level leakage current LOW-level leakage current input clock frequency
5 V and 3.3 V bus 5 V and 3.3 V bus VIH = 3.3 V; VCC = 0 V or 3.3 V VIL = 0 V; VCC = 3.3 V
2.3 -10 -100 -100 -
-
0.99 10 400 0.4 +100 +100 0.4
V V A A kHz V A A V
output voltage during acknowledge Isink = 3 mA high level input current low level input current PORTn maximum output voltage VAS = VCC VAS = 0 V Isink = 9 mA
The product is qualified with an output voltage of 550 mV (p-p) differential, however larger values can be used at baseband outputs that might have impact on the product performance. IIP2 = -20 + (P1 - P2) [dBm]. Wanted signal: RF1 is 2140 MHz, PRFIN = -20 dBm and the AGC adjusted to get 550 mV (p-p) on the differential output. The output level is P1.
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9397 750 13193
Product data sheet
Rev. 01 -- 14 December 2004
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
Unwanted signal: RF1 is 1040 MHz and PRFIN = -20 dBm and RF2 is 1100 MHz and PRFIN = -20 dBm. The output level of (RF1 + RF2) on the output pins is P2. [3] IIP3 = -23 + ---------- [dBm], see Figure 5 Wanted signal: RF1 is LO + 5 MHz, PRFIN = -20 dBm and the AGC adjusted to get 550 mV (p-p) on the differential output. Unwanted signal: RF1 is LO + 5 MHz and PRFIN = -23 dBm, RF2 is LO + 7 MHz and Pin = -23 dBm. [4] Phase noise in optimal conditions, see related application note.
IM3 2
3 MHz
5 MHz
7 MHz
9 MHz IM3
f1
f2
001aac085
IM3 is the difference between the wanted signal and the unwanted signal (2f1 - f2) and (2f2 - f1) on output pins.
Fig 5. Base band spectrum
16. Application information
SCL SDA 3.3 V
39 pF 39 pF 39 pF 100 nF
16 MHz
GND(DIG)
VCC(DIG)
SDA
SCL
XTN
3.3 V
39 pF
PORT1
XTOUT
XTOUT 3.3 V
39 pF
32
31
30
29
28
27
26
XT
GND(DIE) GND(LNA)
10 pF
25
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22
GND(PLL) VCC(PLL) CP GND(VCO) VT VCC(VCO) CAPVCO AS
100 nF 39 pF 4.7 k 100 pF 1 nF
1 k 68 nF
RFIN
RFIN VCC(LNA) GND(RF) n.c. VCC(RF)
TDA8263HN
21 20 19 18 17
39 pF
PORT0
AGC
VCC(BB)
GND(BB)
QP
QN
IN
IP
MS
3.3 V AGC
3.3 V
001aaa978
39 pF
3.3 V
IP IN QN QP
Fig 6. Typical application circuit
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Product data sheet
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TDA8263HN
Fully integrated satellite tuner
17. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm
SOT617-1
D
B
A
terminal 1 index area E
A A1 c
detail X
e1 e 9 L 8 17 e
1/2 e
C b 16 vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area
24 32 Dh 0 2.5 scale E (1) 5.1 4.9 Eh 3.25 2.95 e 0.5 e1 3.5 e2 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 25 X
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.25 2.95
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
Fig 7. Package outline SOT617-1 (HVQFN32)
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Product data sheet
Rev. 01 -- 14 December 2004
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TDA8263HN
Fully integrated satellite tuner
18. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits.
19. Soldering
19.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
19.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
19.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
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Product data sheet
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TDA8263HN
Fully integrated satellite tuner
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
19.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
19.5 Package related soldering information
Table 40: Package [1] BGA, LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8],
[1]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave Reflow [2] suitable suitable not suitable not suitable [4]
HTSSON..T [3],
suitable not WQCCN..L [8] recommended [5] [6] not recommended [7] not suitable
suitable suitable suitable not suitable
PMFP [9],
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office.
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Product data sheet
Rev. 01 -- 14 December 2004
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TDA8263HN
Fully integrated satellite tuner
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[3]
[4]
[5] [6] [7] [8]
[9]
20. Revision history
Table 41: Revision history Release date 20041214 Data sheet status Product data sheet Change notice Doc. number 9397 750 13193 Supersedes Document ID TDA8263HN_1
9397 750 13193
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Product data sheet
Rev. 01 -- 14 December 2004
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Philips Semiconductors
TDA8263HN
Fully integrated satellite tuner
21. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
22. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
24. Licenses
Purchase of Philips I2C-bus components Purchase of Philips I2C-bus components conveys a license under the Philips' I2C-bus patent to use the components in the I2C-bus system provided the system conforms to the I2C-bus specification defined by Koninklijke Philips Electronics N.V. This specification can be ordered using the code 9398 393 40011.
23. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
25. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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Product data sheet
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TDA8263HN
Fully integrated satellite tuner
26. Contents
1 2 3 4 5 6 7 8 8.1 8.2 9 10 10.1 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 21 22 23 24 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Typical performances . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Tuner configuration . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Gain distribution . . . . . . . . . . . . . . . . . . . . . . . . 7 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C-bus inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Address selection . . . . . . . . . . . . . . . . . . . . . . . 8 Master-slave selection . . . . . . . . . . . . . . . . . . . 8 Data transfer in write mode. . . . . . . . . . . . . . . . 8 I2C-bus table in write mode. . . . . . . . . . . . . . . . 8 I2C-bus table in write mode (default at POR) . . 9 Bit description I2C-bus write mode . . . . . . . . . . 9 Data transfer in read mode . . . . . . . . . . . . . . . 14 I2C-bus table in read mode . . . . . . . . . . . . . . . 14 Bit description I2C-bus read mode . . . . . . . . . 14 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 16 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal characteristics. . . . . . . . . . . . . . . . . . 19 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application information. . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Handling information. . . . . . . . . . . . . . . . . . . . 24 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25 Package related soldering information . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 27 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 25 Contact information . . . . . . . . . . . . . . . . . . . . 27
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 December 2004 Document number: 9397 750 13193
Published in The Netherlands

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