 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| High IP3, 10 MHz to 6 GHz, Active Mixer ADL5801 FEATURES Broadband upconverter/downconverter Power conversion gain of 1.8 dB Broadband RF, LO, and IF ports SSB noise figure (NF) of 9.75 dB Input IP3: 28.5 dBm Input P1dB: 13.3 dBm Typical LO drive: 0 dBm Single-supply operation: 5 V at 130 mA Adjustable bias for low power operation Exposed paddle, 4 mm x 4 mm, 24-lead LFCSP package FUNCTIONAL BLOCK DIAGRAM VPLO GND NC IFON IFOP GND 24 23 22 21 20 19 GND GND 1 2 ADL5801 18 VPRF 17 GND 16 LOIP 3 V2I LOIN 4 GND GND 5 6 RFIP 15 RFIN 14 13 GND VPDT APPLICATIONS Cellular base station receivers Radio link downconverters Broadband block conversion Instrumentation 7 8 9 10 11 DET 08079-001 12 VPLO GND ENBL VSET DETO GND Figure 1. GENERAL DESCRIPTION The ADL5801 uses a high linearity, doubly balanced, active mixer core with integrated LO buffer amplifier to provide high dynamic range frequency conversion from 10 MHz to 6 GHz. The mixer benefits from a proprietary linearization architecture that provides enhanced input IP3 performance when subject to high input levels. A bias adjust feature allows the input linearity, SSB noise figure, and dc current to be optimized using a single control pin. An optional input power detector is provided for adaptive bias control. The high input linearity allows the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in degradation in dynamic performance. The adaptive bias feature allows the part to provide high input IP3 performance when presented with large blocking signals. When blockers are removed, the ADL5801 can automatically bias down to provide low noise figure and low power consumption. The balanced active mixer arrangement provides superb LO-toRF and LO-to-IF leakage, typically better than -40 dBm. The IF outputs are designed to provide a typical voltage conversion gain of 7.8 dB when loaded into a 200 load. The broad frequency range of the open-collector IF outputs allows the ADL5801 to be applied as an upconverter for various transmit applications. The ADL5801 is fabricated using a SiGe high performance IC process. The device is available in a compact 4 mm x 4 mm, 24-lead LFCSP package and operates over a -40C to +85C temperature range. An evaluation board is also available. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved. ADL5801 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings ............................................................ 4 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 Typical Performance Characteristics ............................................. 6 Spur Performance ....................................................................... 10 Circuit Description ......................................................................... 11 LO Amplifier and Splitter .......................................................... 11 RF Voltage-to-Current (V-to-I) Converter ............................. 11 Mixer Core .................................................................................. 11 Mixer Output Load .................................................................... 11 RF Detector ................................................................................. 11 Bias Circuit .................................................................................. 12 Applications Information .............................................................. 13 Basic Connections ...................................................................... 13 RF and LO Ports ......................................................................... 13 IF Port .......................................................................................... 14 Evaluation Board ............................................................................ 15 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 REVISION HISTORY 2/10--Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADL5801 SPECIFICATIONS VS = 5 V, TA = 25C, fRF = 900 MHz, fLO = 747 MHz, LO power = 0 dBm, Z0 1 = 50 , VSET = 3.8 V, unless otherwise noted. Table 1. Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage2 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER INTERFACE Supply Voltage Quiescent Current Disable Current Enable Time Disable Time DYNAMIC PERFORMANCE at fRF = 900 MHz/1900 MHz Power Conversion Gain3 Voltage Conversion Gain4 SSB Noise Figure SSB Noise Figure Under Blocking5 Input Third-Order Intercept6 Input Second-Order Intercept7 Input 1 dB Compression Point LO-to-IF Output Leakage LO-to-RF Input Leakage RF-to-IF Output Isolation IF/2 Spurious8 Test Conditions Tunable to >20 dB over a limited bandwidth 10 Differential impedance, f = 200 MHz Can be matched externally to 3000 MHz Externally generated 230 LF 4.75 -10 VS 0 15 50 600 5.25 +10 Min Typ 12 50 6000 Max Unit dB MHz MHz V dBm dB MHz V mA mA ns ns dB dB dB dB dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm dBc dBc dBc dBc dBc 10 4.75 Resistor programmable ENBL pin high Time from ENBL pin low to enable Time from ENBL pin high to disable fRF = 900 MHz fRF = 1900 MHz fRF = 900 MHz fRF = 1900 MHz fCENT = 900 MHz, VSET = 2.0 V fCENT = 1900 MHz, VSET = 2.0 V fCENT = 900 MHz, VSET = 2.0 V fCENT = 1900 MHz, VSET = 2.0 V fCENT = 900 MHz fCENT = 1900 MHz fCENT = 900 MHz fCENT = 1900 MHz fRF = 900 MHz fRF = 1900 MHz Unfiltered IF output 5 130 50 182 28 1.8 1.8 7.8 7.8 9.75 11.5 19.5 20 28.5 26.4 63 49.7 13.3 12.7 -27 -30 -35 -67.5 -53 -65.5 -72.6 6000 5.25 200 0 dBm input power, fRF = 900 MHz 0 dBm input power, fRF = 1900 MHz 0 dBm input power, fRF = 900 MHz 0 dBm input power, fRF = 1900 MHz Z0 is the characteristic impedance assumed for all measurements and the PCB. Supply voltage must be applied from an external circuit through choke inductors. 3 Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss. 4 ZSOURCE = 50 , differential; ZLOAD = 200 differential; ZSOURCE is the impedance of the source instrument; ZLOAD is the load impedance at the output. 5 fRF = fCENT, fBLOCKER = (fCENT - 5) MHz, fLO = (fCENT - 153) MHz, blocker level = 0 dBm. 6 fRF1 = (fCENT - 1) MHz, fRF2 = (fCENT) MHz, fLO = (fCENT - 153) MHz, each RF tone at -10 dBm. 7 fRF1 = (fCENT ) MHz, fRF2 = (fCENT + 100) MHz, fLO = (fCENT - 153) MHz, each RF tone at -10 dBm. 8 For details, see the Spur Performance section. 1 2 Rev. 0 | Page 3 of 20 ADL5801 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS VSET, ENBL IFOP, IFON RFIN Power Internal Power Dissipation JA (Exposed Paddle Soldered Down)1 JC (at Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range 1 Rating 5.5 V 5.5 V 5.5 V 20 dBm 1.2 W 26.5C/W 8.7C/W 150C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION As measured on the evaluation board. For details, see the Evaluation Board section. Rev. 0 | Page 4 of 20 ADL5801 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 VPLO GND NC IFON IFOP GND PIN 1 INDICATOR GND GND LOIP LOIN GND GND 1 2 3 4 5 6 ADL5801 TOP VIEW (Not to Scale) 18 17 16 15 14 13 VPRF GND RFIP RFIN GND VPDT Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 2, 5, 6, 8, 12, 14, 17, 19, 23 3, 4 7, 24 9 10 11 13 15, 16 18 20, 21 22 Mnemonic GND LOIP, LOIN VPLO ENBL VSET DETO VPDT RFIN, RFIP VPRF IFOP, IFON NC EPAD Description Device Common (DC Ground). Differential LO Input Terminal. Internally matched to 50 . Must be ac-coupled. Positive Supply Voltage for LO System. Device Enable. Pull high to disable the device; pull low to enable. Input IP3 Bias Adjustment. The voltage presented to the VSET pin sets the internal bias of the mixer core and allows for adaptive control of the input IP3 and NF characteristics of the mixer core. Detector Output. The DETO pin should be loaded with a capacitor to ground. The developed voltage is proportional to the rms input level. When the DETO output voltage is connected to the VSET input pin, the part auto biases and increases input IP3 performance when presented with large signal input levels. Positive Supply Voltage for Detector. Differential RF Input Terminal. Internally matched to 50 differential input impedance. Must be ac-coupled. Positive Supply Voltage for RF Input System. Differential IF Output Terminal. Bias must be applied through pull-up choke inductors or the center tap of the IF transformer. Not Connected. The exposed paddle must be soldered to ground. Rev. 0 | Page 5 of 20 08079-002 NOTES 1. THERE IS AN EXPOSED PADDLE THAT MUST BE SOLDERED TO GROUND. 2. NC = NO CONNECT. VPLO GND ENBL VSET DETO GND 7 8 9 10 11 12 ADL5801 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25C, VSET = 3.8 V as measured using a typical circuit schematic, unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement. 6 5 4 3 6 35 5 TA = -40C 30 GAIN (dB) GAIN (dB) 2 1 0 -1 -2 -3 08079-003 3 TA = +85C GAIN = 900MHz GAIN = 1900MHz INPUT IP3 = 900MHz INPUT IP3 = 1900MHz 20 2 15 1 10 1000 1500 2000 2500 3000 -10 -5 0 LO LEVEL (dBm) 5 10 15 RF FREQUENCY (MHz) Figure 3. Power Conversion Gain vs. RF Frequency 4.0 3.5 3.0 Figure 6. Power Conversion Gain and Input IP3 vs. LO Power 100 90 80 70 MEAN = 1.87 SD = 0.03 2.5 FREQUENCY (%) GAIN (dB) 900MHz 2.0 1.5 60 50 40 30 20 1900MHz 1.0 0.5 0 0 50 100 150 200 250 IF FREQUENCY (MHz) 10 0 08079-004 1.940 1.980 2.020 2.060 1.700 1.740 1.780 1.820 1.860 1.900 2.100 POWER CONVERSION GAIN (dB) Figure 4. Power Conversion Gain vs. IF Frequency 3.0 2.5 2.0 1.5 GAIN = 900MHz GAIN = 1900MHz IPOS = 900MHz IPOS = 1900MHz 0.18 0.16 Figure 7. Power Conversion Gain Distribution 3.0 TA = -40C 2.5 0.14 SUPPLY CURRENT (A) TA = +25C 2.0 0.12 0.10 0.08 0.06 0.04 0.02 5.0 GAIN (dB) GAIN (dB) TA = +85C 1.5 1.0 0.5 0 -0.5 -1.0 2.0 1.0 0.5 08079-005 2.5 3.0 3.5 VSET (V) 4.0 4.5 4.7 4.8 4.9 5.0 SUPPLY (V) 5.1 5.2 5.3 Figure 5. Power Conversion Gain and Supply Current vs. VSET Figure 8. Power Conversion Gain vs. Supply Voltage Rev. 0 | Page 6 of 20 08079-008 0 08079-007 08079-006 -4 500 0 -15 5 INPUT IP3 (dBm) TA = +25C 4 25 ADL5801 35 30 25 TA = -40C TA = +25C 70 60 50 INPUT IP3 (dBm) 20 TA = +85C INPUT IP2 (dBm) TA = -40C TA = +25C TA = +85C 40 30 20 10 0 500 15 10 5 0 500 08079-009 1000 1500 2000 2500 3000 1000 1500 2000 2500 3000 RF FREQUENCY (MHz) RF FREQUENCY (MHz) Figure 9. Input IP3 vs. RF Frequency 40 80 70 Figure 12. Input IP2 vs. RF Frequency 35 60 900MHz INPUT IP3 (dBm) INPUT IP2 (dBm) 30 900MHz 50 1900MHz 40 30 20 25 1900MHz 20 15 10 0 08079-010 0 50 100 150 200 250 0 50 100 150 200 250 IF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 10. Input IP3 vs. IF Frequency 30 20 Figure 13. Input IP2 vs. IF Frequency 80 70 25 18 900MHz 60 INPUT IP3 (dBm) INPUT IP2 (dBm) 20 16 NOISE FIGURE (dB) 50 1900MHz 40 30 20 15 14 10 INPUT IP3 = 900MHz INPUT IP3 = 1900MHz NF = 900MHz NF = 1900MHz 2.0 2.5 3.0 3.5 VSET (V) 4.0 4.5 5.0 12 5 10 10 0 08079-011 2.0 2.5 3.0 3.5 VSET (V) 4.0 4.5 5.0 Figure 11. Input IP3 and Noise Figure vs. VSET Figure 14. Input IP2 vs. VSET Rev. 0 | Page 7 of 20 08079-014 0 8 08079-013 10 08079-012 ADL5801 20 18 16 TA = +85C TA = +25C 20 25 INPUT P1dB (dBm) 14 12 10 8 6 4 2 08079-015 SSB NOISE FIGURE (dB) 15 TA = -40C 1900MHz 10 900MHz 5 1000 1500 2000 2500 3000 0 100 200 300 400 500 600 700 RF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 15. Input P1dB vs. RF Frequency 20 18 Figure 18. SSB Noise Figure vs. IF Frequency (VSET = 2.0 V) 30 25 16 INPUT P1dB (dBm) 14 12 10 8 6 4 2 900MHz 1900MHz SSB NOISE FIGURE (dB) 20 RF = 1846MHz, IF = 153 MHz BLOCKER = 1841MHz 15 10 RF = 951MHz, IF = 153 MHz BLOCKER = 946MHz 5 0 50 100 150 200 250 08079-016 -25 -20 -15 -10 -5 0 5 IF FREQUENCY (MHz) BLOCKER LEVEL (dBm) Figure 16. Input P1dB vs. IF Frequency 18 16 14 TA = +25C TA = +85C Figure 19. SSB Noise Figure vs. Blocker Level (VSET = 2.0 V) 20 18 16 SSB NOISE FIGURE (dB) SSB NOISE FIGURE (dB) 14 12 10 900MHz 8 6 4 2 08079-020 12 10 TA = -40C 8 6 4 2 0 500 1900MHz 08079-017 1000 1500 2000 2500 3000 0 -15 -10 -5 RF FREQUENCY (MHz) 0 5 LO LEVEL (dBm) 10 15 Figure 17. SSB Noise Figure vs. RF Frequency (VSET = 2.0 V) Figure 20. SSB Noise Figure vs. LO Power (VSET = 2.0 V) Rev. 0 | Page 8 of 20 08079-019 0 0 -30 08079-018 0 500 0 ADL5801 0 5 -10 -15 -20 TA = -40C TA = +25C TA = +85C 10 15 20 25 30 LO-TO-IF LEAKAGE (dBm) 08079-021 RF RETURN LOSS (dB) -25 -30 -35 -40 -45 -50 -55 08079-024 08079-026 08079-025 35 0 500 1000 1500 2000 2500 3000 RF FREQUENCY (MHz) -60 500 1000 1500 2000 2500 3000 LO FREQUENCY (MHz) Figure 21. RF Return Loss vs. RF Frequency 0 Figure 24. LO-to-IF Leakage vs. LO Frequency -10 -15 TA = -40C TA = +25C TA = +85C 5 -20 10 LO-TO-RF LEAKAGE (dBm) 0 500 1000 1500 2000 2500 3000 08079-022 LO RETURN LOSS (dB) -25 -30 -35 -40 -45 -50 15 20 25 30 -55 -60 500 35 LO FREQUENCY (MHz) 1000 1500 2000 2500 3000 LO FREQUENCY (MHz) Figure 22. LO Return Loss vs. LO Frequency 500 4 Figure 25. LO-to-RF Leakage vs. LO Frequency 0 RF-TO-IF OUTPUT ISOLATION (dBc) 400 2 -10 CAPACITANCE (pF) RESISTANCE () -20 300 0 -30 TA = +85C 200 -2 -40 TA = -40C -50 TA = +25C 100 -4 10 100 IF FREQUENCY (MHz) 1000 3000 08079-023 0 -6 -60 500 1000 1500 2000 2500 3000 RF FREQUENCY (MHz) Figure 23. IF Differential Output Impedance (R Parallel C Equivalent) Figure 26. RF-to-IF Leakage vs. RF Frequency Rev. 0 | Page 9 of 20 ADL5801 SPUR PERFORMANCE All spur tables are (N x fRF) - (M x fLO) and were measured using the standard evaluation board (see the Evaluation Board section). Mixer spurious products are measured in decibels relative to the carrier (dBc) from the IF output power level. Data was measured for frequencies less than 6 GHz only. The typical noise floor of the measurement system is -100 dBm. 900 MHz Performance VS = 5 V, VSET = 3.8 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 900 MHz, fLO = 703 MHz, Z0 = 50 . 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -48.8 -35.9 -68.8 -47.5 -95.6 -85.7 1 -33.1 0.0 -74.9 -64.8 -80.7 -74.7 -96.4 -100 2 -23.3 -51.5 -67.5 -94.3 -78.0 -89.8 -83.1 -100 -100 3 -45.8 -19.0 -66.1 -65.9 -78.4 -70.7 -98.5 -95.9 -100 -100 4 -23.6 -65.1 -73.5 -86.3 -95.1 -84.8 -83.3 -100 -99.0 -100 5 -45.9 -29.6 -80.5 -70.2 -73.5 -90.7 -96.7 -97.2 -99.8 -100 -100 6 -30.7 -78.0 -65.0 -76.3 -89.4 -86.7 -100 -83.1 -86.0 -90.9 -100 -100 M 7 -55.4 -50.3 -89.8 -70.6 -87.3 -86.4 -89.4 -84.1 -100 -88.4 -100 -100 -100 8 -41.5 -74.4 -71.3 -74.5 -100 -83.1 -99.6 -100 -100 -83.5 -97.9 -92.6 -100 9 -57.7 -88.5 -81.4 -92.7 -73.7 -96.1 -100 -100 -87.6 -95.5 -87.4 -100 -100 10 11 12 13 14 N -86.8 -100 -99.5 -78.7 -96.1 -99.7 -100 -100 -99.0 -88.2 -100 -100 -100 -98.8 -99.6 -99.4 -80.7 -95.4 -87.9 -100 -100 -100 -92.3 -100 -95.1 -100 -100 -100 -100 -91.1 -95.5 -88.8 -100 -100 -100 -99.3 -100 -96.5 -100 -100 -100 -100 -100 -85.7 -100 -100 -100 -100 -100 -90.4 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 1900 MHz Performance VS = 5 V, VSET = 3.8 V, TA = 25C, RF power = 0 dBm, LO power = 0 dBm, fRF = 1900 MHz, fLO = 1703 MHz, Z0 = 50 . M 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -40.4 -38.4 -100 1 -31.4 0.0 -66.0 -66.2 -100 2 -17.1 -53.6 -52.9 -73.2 -89.4 3 -51.4 -38.5 -68.1 -72.6 -86.4 -83.7 4 -71.0 -64.2 -79.9 -94.6 -66.2 -100 5 6 7 8 9 10 11 12 13 14 N -86.8 -65.2 -87.4 -79.3 -86.4 -100 -92.8 -81.5 -89.0 -100 -92.4 -100 -100 -75.2 -99.0 -92.7 -100 -100 -100 -87.7 -100 -97.5 -100 -100 -100 -100 -98.4 -100 -100 -97.2 -100 -100 -100 -95.4 -100 -95.6 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 -100 Rev. 0 | Page 10 of 20 ADL5801 CIRCUIT DESCRIPTION The ADL5801 includes a double-balanced active mixer with a 50 input impedance and 250 output impedance. In addition, the ADL5801 integrates a local oscillator (LO) amplifier and an RF power detector that can be used to optimize the mixer dynamic range. The RF and LO are differential, providing maximum usable bandwidth at the input and output ports. The LO also operates with a 50 input impedance and can, optionally, be operated differentially or single ended. The input, output, and LO ports can be operated over an exceptionally wide frequency range. The ADL5801 can be configured as a downconvert mixer or as an upconvert mixer. The ADL5801 can be divided into the following sections: the LO amplifier and splitter, the RF voltage-to-current (V-to-I) converter, the mixer core, the output loads, the RF detector, and the bias circuit. A simplified block diagram of the device is shown in Figure 27. The LO block generates a pair of differential LO signals to drive two mixer cores. The RF input power is converted into RF currents by the V-to-I converter that then feed into the two-mixer core. The internal differential load of the mixer provides a wideband 250 output impedance from the mixer. Reference currents to each section are generated by the bias circuit, which can be enabled or disabled using the ENBL pin. A detailed description of each section of the ADL5801 follows. VPLO GND NC IFON IFOP GND 24 23 22 21 20 19 RF VOLTAGE-TO-CURRENT (V-TO-I) CONVERTER The differential RF input signal is applied to a V-to-I converter that converts the differential input voltage to output currents. The V-to-I converter provides a 50 input impedance The V-to. I section bias current can be adjusted up or down using the VSET pin. Adjusting the current up improves IP3 and P1dB input but degrades the SSB noise figure. Adjusting the current down improves the SSB noise figure but degrades IP3 and P1dB input. Conversion gain remains nearly constant over a wide range of VSET pin settings, allowing the part to be adjusted dynamically without affecting conversion gain. The current adjustment can be made by connecting a resistor from the VSET pin to the positive supply to increase the bias current or from the VSET pin to ground to decrease the bias current. Optionally, the VSET pin can be connected to the DETO pin to provide automatic setting of the mixer core current. MIXER CORE The ADL5801 has a double-balanced mixer that uses high performance SiGe NPN transistors. This mixer is based on the Gilbert cell design of four cross-connected transistors. MIXER OUTPUT LOAD The mixer load uses a pair of 125 resistors connected to the positive supply. This provides a 250 differential output resistance. The mixer output should be pulled to the positive supply externally using a pair of RF chokes or using an output transformer with the center tap connected to the positive supply. It is possible to exclude these components when the mixer core current is low, but both P1dB input and IP3 input are then reduced. The mixer load output can operate from direct current (dc) up to approximately 600 MHz into a 200 load. For upconversion applications, the mixer load can be matched using off-chip matching components. Transmit operation up to 2 GHz is possible. See the Applications Information section for matching circuit details. GND GND 1 2 ADL5801 18 VPRF 17 GND 16 LOIP 3 V2I LOIN 4 GND GND 5 6 RFIP 15 RFIN 14 13 GND VPDT DET 08079-127 7 8 9 10 11 12 VPLO GND ENBL VSET DETO GND Figure 27. Block Diagram RF DETECTOR An RF power detector is buffered from the V-to-I converter section. This detector has a power response range from approximately -25 dBm up to 0 dBm and provides a current output. The output current is designed to be connected to the VSET pin to boost the mixer core current when large RF signals are present at the mixer input. An external capacitor can be used to adjust the response time of this function. If not used, the DETO pin can be left open or connected to ground. LO AMPLIFIER AND SPLITTER The LO input is conditioned by a series of amplifiers to provide a well controlled and limited LO swing to the mixer core, resulting in excellent input IP3. The LO input is amplified using a broadband low noise amplifier (LNA) and is then followed by LO limiting amplifiers. The LNA input impedance is nominally 50 . The LO circuit exhibits low additive noise, resulting in an excellent mixer noise figure and output noise under RF blocking. For optimal performance, the LO inputs should be driven differentially but at lower frequencies; single-ended drive is acceptable. Rev. 0 | Page 11 of 20 ADL5801 BIAS CIRCUIT A band gap reference circuit generates the reference currents used by mixers. The bias circuit can be enabled and disabled using the ENBL pin. If the ENBL pin is grounded or left open, the part is enabled. Pulling the ENBL pin high shuts off the bias circuit and disables the part. However, the ENBL pin does not alter the current in the LO section and, therefore, does not provide a true power-down feature. In addition, if the VSET pin is connected to the positive supply through a resistor to increase the mixer core current, this continues to provide bias current to the mixer core unless the resistor supply is also removed. Rev. 0 | Page 12 of 20 ADL5801 APPLICATIONS INFORMATION BASIC CONNECTIONS The ADL5801 is designed to translate between radio frequencies (RF) and intermediate frequencies (IF). For both upconversion and downconversion applications, RFIP (Pin 16) and RFIN (Pin 15) must be configured as the input interfaces. IFOP (Pin 20) and IFON (Pin 21) must be configured as the output interfaces. Individual bypass capacitors are needed in close proximity to each supply pin (Pin 7, Pin 13, Pin 18, and Pin 24), the VSET control pin (Pin 10), and the DETO detector output pin (Pin 11). When the on-chip detector is chosen to form a closed loop, automatically controlling the VSET pin, R7 can be populated with a 0 resistor. Alternatively, simply use a jumper between the VSET and DETO test points for evaluation. Figure 28 illustrates the basic connections for ADL5801 operation. IFOP T1 T5 T8 RF AND LO PORTS The RF and LO input ports are designed for a differential input impedance of approximately 50 . Figure 29 and Figure 30 illustrate the RF and LO interfaces, respectively. It is recommended that each of the RF and LO differential ports be driven through a balun for optimum performance. It is also necessary to ac couple both RF and LO ports. Using proper value capacitors may help improve the input return loss over desired frequencies. Table 4 lists the recommended components for various RF and LO frequency bands. The characterization data is available in the Typical Performance Characteristics section. IFON R11 VPOS R50 C2 C3 24 23 22 21 R13 C50 R3 L1 L3 C13 20 19 R2 L2 VPOS C19 C20 VPLO GND 1 GND 2 GND NC IFON IFOP GND C10 VPOS VPRF 18 GND 17 C8 R14 LOIN LOIP T2 R16 T4 T7 C4 3 LOIP L4 R8 RFIP R4 T3 T6 T9 R12 RFIN RFIP 16 ADL5801 4 LOIN RFIN 15 C9 GND 14 VPDT 13 R10 C5 5 GND L5 6 GND VPOS VPLO GND ENBL VSET DETO GND 7 8 9 10 11 12 VPOS C6 C7 ENBL R7 C12 C18 C17 R9 VSET DETO C1 Figure 28. Basic Connections Schematic Rev. 0 | Page 13 of 20 08079-128 ADL5801 GND 17 C8 RFIP 16 RFIP ADL5801 RFIN 15 C9 GND 14 T3 08079-129 The self-resonant frequency of the selected choke inductors must be higher than the intended IF frequency. A variety of suitable choke inductors is commercially available from manufacturers such as Coilcraft(R) and Murata. An impedance transforming network may be required to transform the final load impedance to 200 at the IF outputs. IFOP T1 T5 T8 Figure 29. RF Interface VPOS 1 GND GND C50 R3 L3 R2 2 C13 C4 3 LOIP 23 22 21 20 19 08079-131 ADL5801 LOIP T2 4 GND NC IFON IFOP GND LOIN C5 5 ADL5801 GND GND Figure 31. Biasing the IF Port Open-Collector Outputs Using a Center-Tapped Impedance Transformer 08079-130 6 ZL IMPEDANCE TRANSFORMING NETWORK T1 T5 T8 Figure 30. LO Interface Table 4. Suggested Components for the RF and LO Interfaces RF and LO Frequency 900 MHz 1900 MHz 2500 MHz T1, T3, T5 Mini-Circuits(R) TC1-1-13M+ Mini-Circuits TC1-1-13M+ Mini-Circuits TC1-1-43+ C8, C9 5.6 pF 5.6 pF 2 pF C4, C5 100 pF 100 pF 8 pF R3 VPOS C20 L1 L3 C13 23 22 21 20 19 08079-132 R2 VPOS L2 C19 IF PORT The IF port features an open-collector, differential output interface. It is necessary to bias the open collector outputs using one of the schemes presented in Figure 31 and Figure 32. Figure 31 shows the use of center-tapped impedance transformers. The turns ratio of the transformer should be selected to provide the desired impedance transformation. In the case of a 50 load impedance, a 4:1 impedance ratio transformer should be used to transform the 50 load into a 200 differential load at the IF output pins. Figure 32 shows a differential IF interface where pull-up choke inductors are used to bias the open-collector outputs. The shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the IF frequency of operation not to load down the output current before it reaches the intended load. Additionally, the dc current handling capability of the selected choke inductors must be at least 45 mA. GND NC IFON IFOP GND ADL5801 Figure 32. Biasing the IF Port Open-Collector Outputs Using Pull-Up Choke Inductors Rev. 0 | Page 14 of 20 ADL5801 EVALUATION BOARD An evaluation board is available for the ADL5801. The standard evaluation board is fabricated using Rogers(R) RO3003 material. Each RF, LO, and IF port is configured for single-ended signaling via a balun transformer. The schematic for the evaluation board is shown in Figure 33. Table 5 describes the various configuration options for the evaluation board. Layout for the board is shown in Figure 34 and Figure 35. IFOP T1 T5 T8 IFON R11 VPOS R50 C2 C3 24 23 22 21 R13 C50 R3 L1 L3 C13 20 19 R2 L2 VPOS C19 C20 VPLO GND 1 NC IFON IFOP GND C10 VPOS GND GND LOIP VPRF 18 GND 17 C8 2 R14 LOIN LOIP R16 C4 3 L4 R8 RFIP RFIN RFIP 16 ADL5801 T2 T4 T7 4 LOIN GND GND 7 8 9 10 11 RFIN 15 C9 GND 14 VPDT 13 C5 5 L5 T3 T6 T9 R12 6 VPOS C11 R10 VPLO GND ENBL VSET DETO GND 12 VPOS C6 C7 ENBL C18 C17 R9 VSET DETO C1 R7 C12 08079-133 Figure 33. Evaluation Board Schematic Rev. 0 | Page 15 of 20 ADL5801 Table 5. Evaluation Board Configuration Components C2, C3, C6, C7, C10, C11 Function Power supply decoupling. Nominal supply decoupling consists of a 0.1 F capacitor to ground in parallel with 100 pF capacitors to ground, positioned as close to the device as possible. Series resistors are provided for enhanced supply decoupling using optional ferrite chip inductors. RF input interfaces. Input channels are ac-coupled through C8 and C9. R8 and R12 provide options when additional matching is needed. T3 is a 1:1 balun used to interface to the 50 differential inputs. T6 and T9 provide options when high frequency baluns are used and require smaller balun footprints. IF output interfaces. The 200 open collector IF output interfaces are biased through the center tap of a 4:1 impedance transformer at T1. C50 provides local bypassing with R50 available for additional supply bypassing. L1 and L2 provide options when pull-up choke inductors are used to bias the open-collector outputs. C13, L3, R2, and R3 are provided for IF filtering and matching options. T5 and T8 provide options when high frequency baluns are used and require smaller balun footprints. LO interface. C4 and C5 provide ac coupling for the local oscillator input. T2 is a 1:1 balun that allows single-ended interfacing to the differential 50 local oscillator input. T4 and T7 provide options when high frequency baluns are used and require smaller balun footprints. DETO interface. C1 and C12 provide decoupling for the DETO pin. R7 provides access to the VSET pin when automatic input IP3 control is needed. VSET bias control. C17 and C18 provide decoupling for the VSET pin. R9 and R10 form an optional resistor divider network between VPOS and GND, allowing for a fixed bias setting. Supply 3.8 V at the VSET pin when the DETO pin is not connected for automatic input IP3 control. Default Conditions C2, C6, C10, C11 = 0.1 F (size 0402) C3, C7 = 100 pF (size 0402) C8, C9 = 5.6 pF (size 0402) L4, L5, R12 = 0 (size 0402) R4, R8 = open (size 0402) T3 = TC1-1-13M+ (Mini-Circuits) C13 = open (size 0402) C19, C20 = 100 pF (size 0402) C50 = 0.1 F (size 0402) L1, L2 = open (size 0805) L3 = open (size 0402) R2, R3, R13, R50 = 0 (size 0402) R11 = open (size 0402) T1 = TC4-1W+ (Mini-Circuits) C4, C5 = 100 pF (size 0402) R14 = 0 (size 0402) R16 = open (size 0402) T2 = TC1-1-13M+ (Mini-Circuits) C1 = 0.1 F (size 0603) C12 = 100 pF (size 0402) R7 = open (size 0402) C17 = 100 pF (size 0402) C18 = 0.1 F (size 0603) R9, R10 = open (size 0402) C8, C9, L4, L5, R4, R8, R12, T3, T6, T9, RFIN, RFIP C13, C19, C20, C50, L1, L2, L3, R2, R3, R11, R13, R50, T1, T5, T8, IFON, IFOP C4, C5, R14, R16, T2, T4, T7, LOIN, LOIP C1, C12, R7, DETO C17, C18, R9, R10, VSET Figure 34. Evaluation Board Top Layer 08079-134 Figure 35. Evaluation Board Bottom Layer Rev. 0 | Page 16 of 20 08079-135 ADL5801 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 0.60 MAX 19 18 EXPOSED PAD (BO TTOMVIEW) PIN 1 INDICATOR 24 1 PIN 1 INDICATOR TOP VIEW 3.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 2.65 2.50 SQ 2.35 6 13 12 7 0.23 MIN 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF 2.50 REF COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8 Figure 36. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-3) Dimensions shown in millimeters ORDERING GUIDE Model1 ADL5801ACPZ-R7 ADL5801-EVALZ 1 Temperature Range -40C to +85C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Package Option CP-24-3 Z = RoHS Complaint Part. Rev. 0 | Page 17 of 20 082908-A SEATING PLANE COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Ordering Quantity 1,500 per Reel 1 ADL5801 NOTES Rev. 0 | Page 18 of 20 ADL5801 NOTES Rev. 0 | Page 19 of 20 ADL5801 NOTES (c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08079-0-2/10(0) Rev. 0 | Page 20 of 20 |
Price & Availability of ADL5801
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |